diff --git a/kernel/chips/w83781d.c b/kernel/chips/w83781d.c index 124ff1ba..68081bc2 100644 --- a/kernel/chips/w83781d.c +++ b/kernel/chips/w83781d.c @@ -234,111 +234,6 @@ static inline u8 DIV_TO_REG(long val, enum chips type) return ((u8) i); } -/* Initial limits */ -#define W83781D_INIT_IN_0 (vid==3500?280:vid/10) -#define W83781D_INIT_IN_1 (vid==3500?280:vid/10) -#define W83781D_INIT_IN_2 330 -#define W83781D_INIT_IN_3 (((500) * 100)/168) -#define W83781D_INIT_IN_4 (((1200) * 10)/38) -#define W83781D_INIT_IN_5 (((-1200) * -604)/2100) -#define W83781D_INIT_IN_6 (((-500) * -604)/909) -#define W83781D_INIT_IN_7 (((500) * 100)/168) -#define W83781D_INIT_IN_8 300 -#define W83781D_INIT_IN_9 250 /* 2.5 Volt for the DDR interface. */ -/* Initial limits for 782d/783s negative voltages */ -/* Note level shift. Change min/max below if you change these. */ -#define W83782D_INIT_IN_5 ((((-1200) + 1491) * 100)/514) -#define W83782D_INIT_IN_6 ((( (-500) + 771) * 100)/314) - -#define W83781D_INIT_IN_PERCENTAGE 10 - -#define W83781D_INIT_IN_MIN_0 \ - (W83781D_INIT_IN_0 - W83781D_INIT_IN_0 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MAX_0 \ - (W83781D_INIT_IN_0 + W83781D_INIT_IN_0 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MIN_1 \ - (W83781D_INIT_IN_1 - W83781D_INIT_IN_1 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MAX_1 \ - (W83781D_INIT_IN_1 + W83781D_INIT_IN_1 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MIN_2 \ - (W83781D_INIT_IN_2 - W83781D_INIT_IN_2 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MAX_2 \ - (W83781D_INIT_IN_2 + W83781D_INIT_IN_2 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MIN_3 \ - (W83781D_INIT_IN_3 - W83781D_INIT_IN_3 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MAX_3 \ - (W83781D_INIT_IN_3 + W83781D_INIT_IN_3 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MIN_4 \ - (W83781D_INIT_IN_4 - W83781D_INIT_IN_4 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MAX_4 \ - (W83781D_INIT_IN_4 + W83781D_INIT_IN_4 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MIN_5 \ - (W83781D_INIT_IN_5 - W83781D_INIT_IN_5 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MAX_5 \ - (W83781D_INIT_IN_5 + W83781D_INIT_IN_5 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MIN_6 \ - (W83781D_INIT_IN_6 - W83781D_INIT_IN_6 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MAX_6 \ - (W83781D_INIT_IN_6 + W83781D_INIT_IN_6 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MIN_7 \ - (W83781D_INIT_IN_7 - W83781D_INIT_IN_7 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MAX_7 \ - (W83781D_INIT_IN_7 + W83781D_INIT_IN_7 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MIN_8 \ - (W83781D_INIT_IN_8 - W83781D_INIT_IN_8 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MAX_8 \ - (W83781D_INIT_IN_8 + W83781D_INIT_IN_8 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MIN_9 \ - (W83781D_INIT_IN_9 - W83781D_INIT_IN_9 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -#define W83781D_INIT_IN_MAX_9 \ - (W83781D_INIT_IN_9 + W83781D_INIT_IN_9 * W83781D_INIT_IN_PERCENTAGE \ - / 100) -/* Initial limits for 782d/783s negative voltages */ -/* These aren't direct multiples because of level shift */ -/* Beware going negative - check */ -#define W83782D_INIT_IN_MIN_5_TMP \ - (((-1200 * (100 + W83781D_INIT_IN_PERCENTAGE)) + (1491 * 100))/514) -#define W83782D_INIT_IN_MIN_5 \ - ((W83782D_INIT_IN_MIN_5_TMP > 0) ? W83782D_INIT_IN_MIN_5_TMP : 0) -#define W83782D_INIT_IN_MAX_5 \ - (((-1200 * (100 - W83781D_INIT_IN_PERCENTAGE)) + (1491 * 100))/514) -#define W83782D_INIT_IN_MIN_6_TMP \ - ((( -500 * (100 + W83781D_INIT_IN_PERCENTAGE)) + (771 * 100))/314) -#define W83782D_INIT_IN_MIN_6 \ - ((W83782D_INIT_IN_MIN_6_TMP > 0) ? W83782D_INIT_IN_MIN_6_TMP : 0) -#define W83782D_INIT_IN_MAX_6 \ - ((( -500 * (100 - W83781D_INIT_IN_PERCENTAGE)) + (771 * 100))/314) - -#define W83781D_INIT_FAN_MIN_1 3000 -#define W83781D_INIT_FAN_MIN_2 3000 -#define W83781D_INIT_FAN_MIN_3 3000 - -#define W83781D_INIT_TEMP_OVER 600 -#define W83781D_INIT_TEMP_HYST 1270 /* must be 127 for ALARM to work */ -#define W83781D_INIT_TEMP2_OVER 600 -#define W83781D_INIT_TEMP2_HYST 500 -#define W83781D_INIT_TEMP3_OVER 600 -#define W83781D_INIT_TEMP3_HYST 500 - /* There are some complications in a module like this. First off, W83781D chips may be both present on the SMBus and the ISA bus, and we have to handle those cases separately at some places. Second, there might be several @@ -1480,154 +1375,7 @@ static void w83781d_init_client(struct i2c_client *client) #endif /* W83781D_RT */ if(init) { - if (type == w83791d) { - w83781d_write_value(client, W83791D_REG_IN_MIN(0), - IN_TO_REG(W83781D_INIT_IN_MIN_0)); - w83781d_write_value(client, W83791D_REG_IN_MAX(0), - IN_TO_REG(W83781D_INIT_IN_MAX_0)); - w83781d_write_value(client, W83791D_REG_IN_MIN(1), - IN_TO_REG(W83781D_INIT_IN_MIN_1)); - w83781d_write_value(client, W83791D_REG_IN_MAX(1), - IN_TO_REG(W83781D_INIT_IN_MAX_1)); - w83781d_write_value(client, W83791D_REG_IN_MIN(2), - IN_TO_REG(W83781D_INIT_IN_MIN_2)); - w83781d_write_value(client, W83791D_REG_IN_MAX(2), - IN_TO_REG(W83781D_INIT_IN_MAX_2)); - w83781d_write_value(client, W83791D_REG_IN_MIN(3), - IN_TO_REG(W83781D_INIT_IN_MIN_3)); - w83781d_write_value(client, W83791D_REG_IN_MAX(3), - IN_TO_REG(W83781D_INIT_IN_MAX_3)); - w83781d_write_value(client, W83791D_REG_IN_MIN(4), - IN_TO_REG(W83781D_INIT_IN_MIN_4)); - w83781d_write_value(client, W83791D_REG_IN_MAX(4), - IN_TO_REG(W83781D_INIT_IN_MAX_4)); - w83781d_write_value(client, W83791D_REG_IN_MIN(5), - IN_TO_REG(W83781D_INIT_IN_MIN_5)); - w83781d_write_value(client, W83791D_REG_IN_MAX(5), - IN_TO_REG(W83781D_INIT_IN_MAX_5)); - w83781d_write_value(client, W83791D_REG_IN_MIN(6), - IN_TO_REG(W83781D_INIT_IN_MIN_6)); - w83781d_write_value(client, W83791D_REG_IN_MAX(6), - IN_TO_REG(W83781D_INIT_IN_MAX_6)); - w83781d_write_value(client, W83791D_REG_IN_MIN(7), - IN_TO_REG(W83781D_INIT_IN_MIN_7)); - w83781d_write_value(client, W83791D_REG_IN_MAX(7), - IN_TO_REG(W83781D_INIT_IN_MAX_7)); - w83781d_write_value(client, W83791D_REG_IN_MIN(8), - IN_TO_REG(W83781D_INIT_IN_MIN_8)); - w83781d_write_value(client, W83791D_REG_IN_MAX(8), - IN_TO_REG(W83781D_INIT_IN_MAX_8)); - w83781d_write_value(client, W83791D_REG_IN_MIN(9), - IN_TO_REG(W83781D_INIT_IN_MIN_9)); - w83781d_write_value(client, W83791D_REG_IN_MAX(9), - IN_TO_REG(W83781D_INIT_IN_MAX_9)); - } else { - w83781d_write_value(client, W83781D_REG_IN_MIN(0), - IN_TO_REG(W83781D_INIT_IN_MIN_0)); - w83781d_write_value(client, W83781D_REG_IN_MAX(0), - IN_TO_REG(W83781D_INIT_IN_MAX_0)); - if (type != w83783s && type != w83697hf) { - w83781d_write_value(client, W83781D_REG_IN_MIN(1), - IN_TO_REG(W83781D_INIT_IN_MIN_1)); - w83781d_write_value(client, W83781D_REG_IN_MAX(1), - IN_TO_REG(W83781D_INIT_IN_MAX_1)); - } - - w83781d_write_value(client, W83781D_REG_IN_MIN(2), - IN_TO_REG(W83781D_INIT_IN_MIN_2)); - w83781d_write_value(client, W83781D_REG_IN_MAX(2), - IN_TO_REG(W83781D_INIT_IN_MAX_2)); - w83781d_write_value(client, W83781D_REG_IN_MIN(3), - IN_TO_REG(W83781D_INIT_IN_MIN_3)); - w83781d_write_value(client, W83781D_REG_IN_MAX(3), - IN_TO_REG(W83781D_INIT_IN_MAX_3)); - w83781d_write_value(client, W83781D_REG_IN_MIN(4), - IN_TO_REG(W83781D_INIT_IN_MIN_4)); - w83781d_write_value(client, W83781D_REG_IN_MAX(4), - IN_TO_REG(W83781D_INIT_IN_MAX_4)); - if (type == w83781d || type == as99127f) { - w83781d_write_value(client, W83781D_REG_IN_MIN(5), - IN_TO_REG(W83781D_INIT_IN_MIN_5)); - w83781d_write_value(client, W83781D_REG_IN_MAX(5), - IN_TO_REG(W83781D_INIT_IN_MAX_5)); - } else { - w83781d_write_value(client, W83781D_REG_IN_MIN(5), - IN_TO_REG(W83782D_INIT_IN_MIN_5)); - w83781d_write_value(client, W83781D_REG_IN_MAX(5), - IN_TO_REG(W83782D_INIT_IN_MAX_5)); - } - if (type == w83781d || type == as99127f) { - w83781d_write_value(client, W83781D_REG_IN_MIN(6), - IN_TO_REG(W83781D_INIT_IN_MIN_6)); - w83781d_write_value(client, W83781D_REG_IN_MAX(6), - IN_TO_REG(W83781D_INIT_IN_MAX_6)); - } else { - w83781d_write_value(client, W83781D_REG_IN_MIN(6), - IN_TO_REG(W83782D_INIT_IN_MIN_6)); - w83781d_write_value(client, W83781D_REG_IN_MAX(6), - IN_TO_REG(W83782D_INIT_IN_MAX_6)); - } - if ((type == w83782d) || (type == w83627hf) || - (type == w83697hf)) { - w83781d_write_value(client, W83781D_REG_IN_MIN(7), - IN_TO_REG(W83781D_INIT_IN_MIN_7)); - w83781d_write_value(client, W83781D_REG_IN_MAX(7), - IN_TO_REG(W83781D_INIT_IN_MAX_7)); - w83781d_write_value(client, W83781D_REG_IN_MIN(8), - IN_TO_REG(W83781D_INIT_IN_MIN_8)); - w83781d_write_value(client, W83781D_REG_IN_MAX(8), - IN_TO_REG(W83781D_INIT_IN_MAX_8)); - w83781d_write_value(client, W83781D_REG_VBAT, - (w83781d_read_value(client, W83781D_REG_VBAT) | 0x01)); - } - } - - w83781d_write_value(client, W83781D_REG_FAN_MIN(1), - FAN_TO_REG(W83781D_INIT_FAN_MIN_1, 2)); - w83781d_write_value(client, W83781D_REG_FAN_MIN(2), - FAN_TO_REG(W83781D_INIT_FAN_MIN_2, 2)); - if (type != w83697hf) { - w83781d_write_value(client, W83781D_REG_FAN_MIN(3), - FAN_TO_REG(W83781D_INIT_FAN_MIN_3, 2)); - } - - w83781d_write_value(client, W83781D_REG_TEMP_OVER, - TEMP_TO_REG(W83781D_INIT_TEMP_OVER)); - w83781d_write_value(client, W83781D_REG_TEMP_HYST, - TEMP_TO_REG(W83781D_INIT_TEMP_HYST)); - - if (type == as99127f) { - w83781d_write_value(client, W83781D_REG_TEMP2_OVER, - AS99127_TEMP_ADD_TO_REG - (W83781D_INIT_TEMP2_OVER)); - w83781d_write_value(client, W83781D_REG_TEMP2_HYST, - AS99127_TEMP_ADD_TO_REG - (W83781D_INIT_TEMP2_HYST)); - } else { - w83781d_write_value(client, W83781D_REG_TEMP2_OVER, - TEMP_ADD_TO_REG - (W83781D_INIT_TEMP2_OVER)); - w83781d_write_value(client, W83781D_REG_TEMP2_HYST, - TEMP_ADD_TO_REG - (W83781D_INIT_TEMP2_HYST)); - } w83781d_write_value(client, W83781D_REG_TEMP2_CONFIG, 0x00); - - if (type == as99127f) { - w83781d_write_value(client, W83781D_REG_TEMP3_OVER, - AS99127_TEMP_ADD_TO_REG - (W83781D_INIT_TEMP3_OVER)); - w83781d_write_value(client, W83781D_REG_TEMP3_HYST, - AS99127_TEMP_ADD_TO_REG - (W83781D_INIT_TEMP3_HYST)); - } else if (type != w83783s && type != w83697hf) { - w83781d_write_value(client, W83781D_REG_TEMP3_OVER, - TEMP_ADD_TO_REG - (W83781D_INIT_TEMP3_OVER)); - w83781d_write_value(client, W83781D_REG_TEMP3_HYST, - TEMP_ADD_TO_REG - (W83781D_INIT_TEMP3_HYST)); - } if (type != w83783s && type != w83697hf) { w83781d_write_value(client, W83781D_REG_TEMP3_CONFIG, 0x00);