From de722b68e401f2756c0339a831b3d51be4306b5a Mon Sep 17 00:00:00 2001 From: Philip Edelbrock Date: Tue, 15 Dec 1998 04:55:51 +0000 Subject: [PATCH] (Phil) Added some eeprom docs/tools and fixed some typos while I was at it. git-svn-id: http://lm-sensors.org/svn/lm-sensors/trunk@79 7894878c-1315-0410-8ee3-d5d059ff63e0 --- doc/eeprom | 83 ++++++++++ doc/piix4 | 2 +- kernel/chips/eeprom.c | 2 +- prog/eeprom/decode-dimms.pl | 293 ++++++++++++++++++++++++++++++++++++ src/eeprom.c | 2 +- 5 files changed, 379 insertions(+), 3 deletions(-) create mode 100644 doc/eeprom create mode 100755 prog/eeprom/decode-dimms.pl diff --git a/doc/eeprom b/doc/eeprom new file mode 100644 index 00000000..b4071e48 --- /dev/null +++ b/doc/eeprom @@ -0,0 +1,83 @@ +Some quick notes about the eeprom.o module and decode_dimms.pl. + +EEPROM Module +------------- + +This is a simple EEPROM module meant to enable reading the first 128 bytes +of an EEPROM (on a SDRAM DIMM). This module will probably need to be at +least expanded. A /dev file interface would probably be more effective. +This module was a programming exercise to get used to the new project +organization laid out by Frodo, but it should be at least completely +effective for decoding the contents of EEPROMs on DIMMs. + +Lacking functionality: + +* Read past byte 128. There is no technical restriction for not doing +this, but making a zillion dataxx-xx files would be a bit rediculous. +EEPROMs on DIMMs shouldn't use the contents past byte 128, so we are fine. + +* Enable Writing. Again, no technical reason why not, but making it easy +to change the contents of the EEPROMs (on DIMMs anyway) also makes it easy +to disable the DIMMs until the values are restored somehow. + +Use: + +After inserting the module (and any other required smbus/i2c modules), you +should have some EEPROM directories in /proc/sys/dev/sensors/ of names such +as "eeprom-i2c-0-50". Inside each of these is a series of files which +represent 16 bytes blocks from the EEPROM. The data is in decimal (base +10) delimited by spaces. + +Note: + +EEPROMs reported are not nessesarily all from DIMMs. Xeon processors, for +example, have serial EEPROMs in them connected to the SMBus which will be +found by the module. Take care to ignore the output of decode_dimms.pl for +these EEPROMs. + + +DECODE_DIMMS.PL +--------------- + +This Perl script attempts to make sense of the first 128 bytes of a SDRAM +DIMM. Using the 'Serial Presence Detect (SPD)' Spec (Rev1.2a)** from +Intel. When finished, it will decode and report all the values defined in +the spec. Much of the information is technical timing and interfacing info +(probably not all used by the Bios or clocking IC. + +Note: During testing, we noticed that many DIMMs have trucated SPD records. +I'm not sure if these conform to an old spec, or if the manufacturers are +simply just taking short-cuts. But, many DIMMs have all zeros stored past +byte 21. I asked an Intel SDRAM tester, Sat Kolli (skolli@smartm.com), +about this and this is what he had to say: + +"[...] Now in terms of SPD contents, you are right that people do all kinds +of things. The way to insure that any module works is to look for the most +basic information, such as module bank density, number of banks, and device +addresses. That will give you the module size and what devices are used. It +is very difficult to verify if the module is PC-100, because of +inconsistencies between spd data from different manufacturers. You could +read the timing information or the special Intel bytes (126 & 127) but I do +not know how many program that information.These inconsistencies may be +minimized if you or your customers stay with some of the better known +manufacturers." (Thanks goes to Sat Kolli for his comments and help) + +Use: + +After inserting the nessesary modules, run the script! + +Notes: + +The script assumes that Perl can be found at /usr/bin/perl. If different, +you will need to adjust the first line of the file accordingly, or else +you will get a strange "decode_dimms.pl: no such file or directory" error. + +Also note that the script assumes that _all_ the eeproms belong to DIMMs, +which may not be the case. + + +------------------------------------------------------------------------ +** PDF is available from Intel or our web site: +http://www.netroedge.com/~lm78 + +"eeprom" doc created Dec. 14, 1998 by Philip Edelbrock diff --git a/doc/piix4 b/doc/piix4 index 80909e3d..09a588ac 100644 --- a/doc/piix4 +++ b/doc/piix4 @@ -1,6 +1,6 @@ The PIIX4 (properly known as the 82371AB) is an Intel chip with a lot of functionality. Among other things, it implements the PCI bus. One of its -minor functions is implementing a System Management MBus. This is a true +minor functions is implementing a System Management Bus. This is a true SMBus - you can not access it on I2C levels. The good news is that it natively understands SMBus commands and you do not have to worry about timing problems. The bad news is that non-SMBus devices connected to it diff --git a/kernel/chips/eeprom.c b/kernel/chips/eeprom.c index 892e9cb3..affade9e 100644 --- a/kernel/chips/eeprom.c +++ b/kernel/chips/eeprom.c @@ -286,7 +286,7 @@ void eeprom_update_client(struct i2c_client *client) #endif } for (i=0;idata[i] = (u8)smbus_read_byte(client->adapter,client->addr); + data->data[i] = (u8)smbus_read_byte(client->adapter,client->addr); } data->last_updated = jiffies; diff --git a/prog/eeprom/decode-dimms.pl b/prog/eeprom/decode-dimms.pl new file mode 100755 index 00000000..7736371a --- /dev/null +++ b/prog/eeprom/decode-dimms.pl @@ -0,0 +1,293 @@ +#!/usr/bin/perl +# +# Copyright 1998, Philip Edelbrock +# +# Version 0.2 +# +# EEPROM data decoding for SDRAM DIMM modules. +# +# Two assumptions: lm_sensors-2.0.2 installed, +# and Perl is at /usr/bin/perl +# +# +# Reference: PC SDRAM Serial Presence +# Detect (SPD) Specification, Intel, +# Dec '97, Rev 1.2A +# + +print "SDRAM Serial Presence Detect Tester/Decoder\n"; +print "Written by Philip Edelbrock. Copyright 1998.\n"; +print "Version 0.2\n\n"; + +$dimm_count=0; +$_=`ls /proc/sys/dev/sensors/`; +@dimm_list=split(); + +for $i ( 0 .. $#dimm_list ) { + $_=$dimm_list[$i]; + if (/^eeprom-/) { + $dimm_count=$dimm_count + 1; + + print "\nDecoding EEPROM: /proc/sys/dev/sensors/$dimm_list[$i]\n"; + if (/^[^-]+-[^-]+-[^-]+-([^-]+)$/) { + $dimm_num=$1 - 49; + print "Guessing DIMM is in bank $dimm_num\n"; + } +# Decode first 16 bytes + print "\t\t----=== The Following is Required Data and is Applicable to all DIMM Types ===----\n"; + + $_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data0-15`; + @bytes=split(" "); + print "\t# of bytes written to SDRAM EEPROM:\t\t$bytes[0]\n"; + + print "\tTotal number of bytes in EEPROM:\t\t"; + if ($bytes[1] < 13) { + print 2**$bytes[1]; + print "\n"; + } elsif ($bytes[1] == 0) { + print "RFU\n"; + } else { print "ERROR!\n"; } + + print "\tFundemental Memory type:\t\t\t"; + if ($bytes[2] == 2) { print "EDO\n"; } elsif ($bytes[2] == 4) { print "SDRAM\n"; + } else { print "???\n"; } + + print "\tNumber of Row Address Bits (SDRAM only):\t"; + if ($bytes[3] == 0) { print "Undefined!\n" } + elsif ($bytes[3] == 1) { print "1/16\n" } + elsif ($bytes[3] == 2) { print "2/17\n" } + elsif ($bytes[3] == 3) { print "3/18\n" } + else { print $bytes[3]; print "\n"; } + + print "\tNumber of Col Address Bits (SDRAM only):\t"; + if ($bytes[4] == 0) { print "Undefined!\n" } + elsif ($bytes[4] == 1) { print "1/16\n" } + elsif ($bytes[4] == 2) { print "2/17\n" } + elsif ($bytes[4] == 3) { print "3/18\n" } + else { print $bytes[4]; print "\n"; } + + print "\tNumber of Module Rows:\t\t\t\t"; + if ($bytes[5] == 0 ) { print "Undefined!\n"; } else { print $bytes[5]; print "\n"; } + + print "\tData Width (SDRAM only):\t\t\t"; + if ($bytes[7] > 1) { print "Undefined!\n" } else { + $temp=($bytes[7]*256) + $bytes[6]; + print $temp; print "\n"; } + + print "\tModule Interface Signal Levels:\t\t\t"; + if ($bytes[8] == 0) { print "5.0 Volt/TTL\n";} elsif ($bytes[8] == 1) { + print "LVTTL\n";} elsif ($bytes[8] == 2) { print "HSTL 1.5\n";} elsif ($bytes[8] == 3) { + print "SSTL 3.3\n";} elsif ($bytes[8] == 4) { print "SSTL 2.5\n";} else { print "Undefined!\n";} + + print "\tCycle Time (SDRAM):\t\t\t\t"; + $temp=($bytes[9] >> 4) + (($bytes[9] - (($bytes[9] >> 4)<< 4)) * 0.1); + print $temp; print "ns\n"; + + print "\tAccess Time (SDRAM):\t\t\t\t"; + $temp=($bytes[10] >> 4) + (($bytes[10] - (($bytes[10] >> 4)<< 4)) * 0.1); + print $temp; print "ns\n"; + + print "\tModule Configuration Type:\t\t\t"; + if ($bytes[11] == 0) { print "No Parity\n"; } elsif ($bytes[11] == 1) { print "Parity\n"; + } elsif ($bytes[11] == 2) { print "ECC\n"; } else { print "Undefined!"; } + + print "\tRefresh Type:\t\t\t\t\t"; + if ($bytes[12] > 126) { print "Self Refreshing\n"; $temp=$bytes[12] - 127; + } else { print "Not Self Refreshing\n"; $temp=$bytes[12];} + + print "\tRefresh Rate:\t\t\t\t\t"; + if ($temp == 0) { print "Normal (15.625uS)\n"; } elsif ($temp == 1) { print "Reduced (3.9uS)\n"; + } elsif ($temp == 2) { print "Reduced (7.8uS)\n"; } elsif ($temp == 3) { print "Extended (31.3uS)\n"; + } elsif ($temp == 4) { print "Extended (62.5uS)\n"; } elsif ($temp == 5) { print "Extended (125uS)\n"; + } else { print "Undefined!";} + + print "\tPrimary SDRAM Component Bank Config:\t\t"; + if ($bytes[13]>126) {$temp=$bytes[13]-127; print "Bank2 = 2 x Bank1\n";} else { + $temp=$bytes[13]; print "No Bank2 OR Bank2 = Bank1 width\n";} + + print "\tPrimary SDRAM Component Widths:\t\t\t"; + if ($temp == 0) { print "Undefined!\n"; } else { print "$temp\n"; } + + print "\tError Checking SDRAM Component Bank Config:\t"; + if ($bytes[14]>126) {$temp=$bytes[14]-127; print "Bank2 = 2 x Bank1\n";} else { + $temp=$bytes[14]; print "No Bank2 OR Bank2 = Bank1 width\n";} + + print "\tError Checking SDRAM Component Widths:\t\t"; + if ($temp == 0) { print "Undefined!\n"; } else { print "$temp\n"; } + + print "\tMin Clock Delay for Back to Back Random Access:\t"; + if ($bytes[15] == 0) { print "Undefined!\n"; } else { print "$bytes[15]\n"; } + + print "\t\t----=== The Following Apply to SDRAM DIMMs ONLY ===----\n"; + +# Decode next 16 bytes + $_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data16-31`; + @bytes=split(" "); + + print "\tBurst lengths supported:\t\t\t"; + $temp=""; + if (($bytes[0] & 1) > 0) { print "${temp}Burst Length = 1\n"; $temp="\t\t\t\t\t\t\t";} + if (($bytes[0] & 2) > 0) { print "${temp}Burst Length = 2\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[0] & 4) > 0) { print "${temp}Burst Length = 4\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[0] & 8) > 0) { print "${temp}Burst Length = 8\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[0] & 16) > 0) { print "${temp}Undefined! (bit 4)\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[0] & 32) > 0) { print "${temp}Undefined! (bit 5)\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[0] & 64) > 0) { print "${temp}Undefined! (bit 6)\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[0] & 128) > 0) { print "${temp}Burst Length = Page\n"; $temp="\t\t\t\t\t\t\t"; } + if ($bytes[0] == 0) { print "(None Supported)\n";} + + print "\tNumber of Device Banks:\t\t\t\t"; + if ($bytes[1] == 0) { print "Undefined/Reserved!\n"; } else { print "$bytes[1]\n"; } + + print "\tSupported CAS Latencies:\t\t\t"; + $temp=""; + if (($bytes[2] & 1) > 0) { print "${temp}CAS Latency = 1\n"; $temp="\t\t\t\t\t\t\t";} + if (($bytes[2] & 2) > 0) { print "${temp}CAS Latency = 2\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[2] & 4) > 0) { print "${temp}CAS Latency = 3\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[2] & 8) > 0) { print "${temp}CAS Latency = 4\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[2] & 16) > 0) { print "${temp}CAS Latency = 5\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[2] & 32) > 0) { print "${temp}CAS Latency = 6\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[2] & 64) > 0) { print "${temp}CAS Latency = 7\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[2] & 128) > 0) { print "${temp}Undefined (bit 7)\n"; $temp="\t\t\t\t\t\t\t"; } + if ($bytes[2] == 0) { print "(None Supported)\n";} + + print "\tSupported CS Latencies:\t\t\t\t"; + $temp=""; + if (($bytes[3] & 1) > 0) { print "${temp}CS Latency = 0\n"; $temp="\t\t\t\t\t\t\t";} + if (($bytes[3] & 2) > 0) { print "${temp}CS Latency = 1\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[3] & 4) > 0) { print "${temp}CS Latency = 2\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[3] & 8) > 0) { print "${temp}CS Latency = 3\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[3] & 16) > 0) { print "${temp}CS Latency = 4\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[3] & 32) > 0) { print "${temp}CS Latency = 5\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[3] & 64) > 0) { print "${temp}CS Latency = 6\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[3] & 128) > 0) { print "${temp}Undefined (bit 7)\n"; $temp="\t\t\t\t\t\t\t"; } + if ($bytes[3] == 0) { print "(None Supported)\n";} + + print "\tSupported WE Latencies:\t\t\t\t"; + $temp=""; + if (($bytes[4] & 1) > 0) { print "${temp}WE Latency = 0\n"; $temp="\t\t\t\t\t\t\t";} + if (($bytes[4] & 2) > 0) { print "${temp}WE Latency = 1\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[4] & 4) > 0) { print "${temp}WE Latency = 2\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[4] & 8) > 0) { print "${temp}WE Latency = 3\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[4] & 16) > 0) { print "${temp}WE Latency = 4\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[4] & 32) > 0) { print "${temp}WE Latency = 5\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[4] & 64) > 0) { print "${temp}WE Latency = 6\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[4] & 128) > 0) { print "${temp}Undefined (bit 7)\n"; $temp="\t\t\t\t\t\t\t"; } + if ($bytes[4] == 0) { print "(None Supported)\n";} + + print "\tSDRAM Module Attributes:\t\t\t"; + $temp=""; + if (($bytes[5] & 1) > 0) { print "${temp}Buffered Address/Control Inputs\n"; $temp="\t\t\t\t\t\t\t";} + if (($bytes[5] & 2) > 0) { print "${temp}Registered Address/Control Inputs\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[5] & 4) > 0) { print "${temp}On card PLL (clock)\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[5] & 8) > 0) { print "${temp}Buffered DQMB Inputs\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[5] & 16) > 0) { print "${temp}Registered DQMB Inputs\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[5] & 32) > 0) { print "${temp}Differential Clock Input\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[5] & 64) > 0) { print "${temp}Redundant Row Address\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[5] & 128) > 0) { print "${temp}Undefined (bit 7)\n"; $temp="\t\t\t\t\t\t\t"; } + if ($bytes[5] == 0) { print "(None Reported)\n";} + + print "\tSDRAM Device Attributes (General):\t\t"; + $temp=""; + if (($bytes[6] & 1) > 0) { print "${temp}Supports Early RAS# Recharge\n"; $temp="\t\t\t\t\t\t\t";} + if (($bytes[6] & 2) > 0) { print "${temp}Supports Auto-Precharge\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[6] & 4) > 0) { print "${temp}Supports Precharge All\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[6] & 8) > 0) { print "${temp}Supports Write1/Read Burst\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[6] & 16) > 0) { print "${temp}Lower VCC Tolerance:5%\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[6] & 16) == 0) { print "${temp}Lower VCC Tolerance:10%\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[6] & 32) > 0) { print "${temp}Upper VCC Tolerance:5%\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[6] & 32) == 0) { print "${temp}Upper VCC Tolerance:10%\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[6] & 64) > 0) { print "${temp}Undefined (bit 6)\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[6] & 128) > 0) { print "${temp}Undefined (bit 7)\n"; $temp="\t\t\t\t\t\t\t"; } + + print "\tSDRAM Cycle Time (2ns highest CAS):\t\t"; + $temp=$bytes[7] >> 4; + if ($temp == 0) { print "Undefined!\n"; } else { + if ($temp < 4 ) {$temp=$temp + 15;} + print $temp + (($bytes[7] & 15) / 10); + print "nS\n"; + } + + print "\tSDRAM Access from Clock Time (2nd highest CAS):\t"; + $temp=$bytes[8] >> 4; + if ($temp == 0) { print "Undefined!\n"; } else { + if ($temp < 4 ) {$temp=$temp + 15;} + print $temp + (($bytes[8] & 15) / 10.0); + print "nS\n"; + } + + print "\t\t----=== The Following are Optional (may be Bogus) ===----\n"; + + print "\tSDRAM Cycle Time (3rd highest CAS):\t\t"; + $temp=$bytes[9] >> 2; + if ($temp == 0) { print "Undefined!\n"; } else { + print $temp + (($bytes[9] & 3) / 4.0); + print "nS\n"; + } + + print "\tSDRAM Access from Clock Time (3rd highest CAS):\t"; + $temp=$bytes[10] >> 2; + if ($temp == 0) { print "Undefined!\n"; } else { + print $temp + (($bytes[10] & 3) / 4.0); + print "nS\n"; + } + + print "\t\t----=== The Following are Required (for SDRAMs) ===----\n"; + + print "\tMinumum Row Precharge Time:\t\t\t"; + if ($bytes[11] == 0) { print "Undefined!\n"; } else { print "$bytes[11]nS\n"; } + + print "\tRow Active to Row Active Min:\t\t\t"; + if ($bytes[12] == 0) { print "Undefined!\n"; } else { print "$bytes[12]nS\n"; } + + print "\tRAS to CAS Delay:\t\t\t\t"; + if ($bytes[13] == 0) { print "Undefined!\n"; } else { print "$bytes[13]nS\n"; } + + print "\tMin RAS Pulse Width:\t\t\t\t"; + if ($bytes[14] == 0) { print "Undefined!\n"; } else { print "$bytes[14]nS\n"; } + + + print "\t\t----=== The Following are Required and Apply to ALL DIMMs ===----\n"; + + print "\tRow Densities:\t\t\t\t\t"; + $temp=""; + if (($bytes[15] & 1) > 0) { print "${temp}4 MByte\n"; $temp="\t\t\t\t\t\t\t";} + if (($bytes[15] & 2) > 0) { print "${temp}8 MByte\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[15] & 4) > 0) { print "${temp}16 MByte\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[15] & 8) > 0) { print "${temp}32 MByte\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[15] & 16) > 0) { print "${temp}64 MByte\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[15] & 32) > 0) { print "${temp}128 MByte\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[15] & 64) > 0) { print "${temp}256 MByte\n"; $temp="\t\t\t\t\t\t\t"; } + if (($bytes[15] & 128) > 0) { print "${temp}512 MByte\n"; $temp="\t\t\t\t\t\t\t"; } + if ($bytes[15] == 0) { print "(Undefined! -- None Reported!)\n";} + + +# Decode next 16 bytes (32-47) + $_=`cat /proc/sys/dev/sensors/$dimm_list[$i]/data32-47`; + @bytes=split(" "); + + print "\tCommand and Address Signal Setup Time:\t\t"; + if ($bytes[0] > 127) { $temp=($bytes[0]-128)>>4; $temp2=-1; } else { $temp=$bytes[0]>>4; $temp2=1;} + print $temp2 * ($temp + (($bytes[0] & 15) / 10.0)); + print "nS\n"; + + print "\tCommand and Address Signal Hold Time:\t\t"; + if ($bytes[1] > 127) { $temp=($bytes[1]-128)>>4; $temp2=-1; } else { $temp=$bytes[1]>>4; $temp2=1;} + print $temp2 * ($temp + (($bytes[1] & 15) / 10.0)); + print "nS\n"; + + print "\tData Signal Setup Time:\t\t\t\t"; + if ($bytes[2] > 127) { $temp=($bytes[2]-128)>>4; $temp2=-1; } else { $temp=$bytes[2]>>4; $temp2=1;} + print $temp2 * ($temp + (($bytes[2] & 15) / 10.0)); + print "nS\n"; + + print "\tData Signal Hold Time:\t\t\t\t"; + if ($bytes[3] > 127) { $temp=($bytes[3]-128)>>4; $temp2=-1; } else { $temp=$bytes[3]>>4; $temp2=1;} + print $temp2 * ($temp + (($bytes[3] & 15) / 10.0)); + print "nS\n"; + +# That's it for the lower part of an SDRAM EEPROM's memory! + + } +} +print "\n\nNumber of SDRAM DIMMs detected and decoded: $dimm_count\n"; diff --git a/src/eeprom.c b/src/eeprom.c index 892e9cb3..affade9e 100644 --- a/src/eeprom.c +++ b/src/eeprom.c @@ -286,7 +286,7 @@ void eeprom_update_client(struct i2c_client *client) #endif } for (i=0;idata[i] = (u8)smbus_read_byte(client->adapter,client->addr); + data->data[i] = (u8)smbus_read_byte(client->adapter,client->addr); } data->last_updated = jiffies;