mirror of
https://github.com/lm-sensors/lm-sensors.git
synced 2026-10-21 11:39:31 +00:00
Martin Knoblauch
0e972677f2
git-svn-id: http://lm-sensors.org/svn/lm-sensors/trunk@1226 7894878c-1315-0410-8ee3-d5d059ff63e0
172 lines
8.5 KiB
Plaintext
172 lines
8.5 KiB
Plaintext
Kernel driver `fscscy.o'
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======================
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Status: Beta
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Tested with motherboard D1230
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Should also work with D1204, D1306 and D1307
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Think twice before you're using the write mode of some
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variables, especially the watchdog (Not my comment, but it makes
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good sense to observe :-)
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Supported chips:
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* Fujitsu Siemens Scylla chip
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Prefix `fscscy'
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Addresses scanned: I2C 0x73
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Author: Martin Knoblauch <mkn@teraport.de>
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Acknowledgement:
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This code has been greatly inspired by Hermann Jung <hej@odn.de>
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and his work on the Poseidon driver (fscpos)
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Module Parameters
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-----------------
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* force: short array (min = 1, max = 48)
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List of adapter,address pairs to boldly assume to be present
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* ignore: short array (min = 1, max = 48)
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List of adapter,address pairs not to scan
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* ignore_range: short array (min = 1, max = 48)
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List of adapter,start-addr,end-addr triples not to scan
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* probe: short array (min = 1, max = 48)
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List of adapter,address pairs to scan additionally
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* probe_range: short array (min = 1, max = 48)
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List of adapter,start-addr,end-addr triples to scan additionally
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Description
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-----------
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This driver implements support for the Fujitsu Siemens Scylla chip.
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The code is based on the "fscpos" driver for the FSC Poseidon chip.
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In fact, it seems the Scylla is a superset of the "Poseidon", "Poseidon II"
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and "Hydra" chips.
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The register readings/setting have been deduced from the 'Register Set
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Specification BMC Poseidon based Systemboard' by Fujitsu Siemens and the
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"sbbmon.ini" file from the Fujitsu-Siemens ServerView software.
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The scylla chip implements a hardware based system management,
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e.g. for controlling fan speed and core voltage.
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There is also a watchdog counter on the chip which can trigger
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an alarm and even shutdown the system.
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The chip provides four temperature values (cpu0/1, motherboard and auxiliary),
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three current values (12 volt, 5 volt and battery) and up to
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six fans (power supply, cpu and auxiliary).
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Temperatures are measured in degrees Celcius. The resolution is 1 degree.
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FAN rotation speeds are reported in RPM (rotations per minute).
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The value can be divided by a programmable divider (1, 2, 4 or 8) which
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is stored on the chip.
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Voltage sensors (also known as IN sensors) report their values in volts.
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All values are reported as final values from the driver.
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There is no need for further calculations.
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Chip Features
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-------------
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Chip `fscscy'
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LABEL LABEL CLASS COMPUTE CLASS ACCESS MAGNITUDE
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rev NONE NONE R 0
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event NONE NONE R 0
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control NONE NONE RW 0
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volt12 NONE NONE R 2
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volt5 NONE NONE R 2
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voltbatt NONE NONE R 2
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temp1 NONE NONE R 0
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temp2 NONE NONE R 0
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temp3 NONE NONE R 0
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temp4 NONE NONE R 0
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temp1_state temp1 temp1 RW 0
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temp2_state temp2 temp2 RW 0
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temp3_state temp3 temp3 RW 0
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temp4_state temp4 temp4 RW 0
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temp1_max temp1 temp1 R 0
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temp2_max temp2 temp2 R 0
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temp3_max temp3 temp3 R 0
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temp4_max temp4 temp4 R 0
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fan1 NONE NONE R 0
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fan2 NONE NONE R 0
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fan3 NONE NONE R 0
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fan4 NONE NONE R 0
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fan5 NONE NONE R 0
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fan6 NONE NONE R 0
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fan1_min fan1 fan1 RW 0
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fan2_min fan2 fan2 RW 0
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fan3_min fan3 fan3 RW 0
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fan4_min fan4 fan4 RW 0
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fan5_min fan5 fan5 RW 0
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fan6_min fan6 fan6 RW 0
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fan1_state fan1 fan1 RW 0
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fan2_state fan2 fan2 RW 0
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fan3_state fan3 fan3 RW 0
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fan4_state fan4 fan4 RW 0
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fan5_state fan5 fan5 RW 0
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fan6_state fan6 fan6 RW 0
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fan1_ripple fan1 fan1 RW 0
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fan2_ripple fan2 fan2 RW 0
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fan3_ripple fan3 fan3 RW 0
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fan4_ripple fan4 fan4 RW 0
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fan5_ripple fan5 fan5 RW 0
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fan6_ripple fan6 fan6 RW 0
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wdog_preset NONE NONE RW 0
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wdog_state wdog_preset wdog_preset RW 0
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wdog_control wdog_preset wdog_preset RW 0
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LABEL FEATURE SYMBOL SYSCTL FILE:OFFSET
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rev FSCSCY_SYSCTL_REV rev:1
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event FSCSCY_SYSCTL_EVENT event:1
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control FSCSCY_SYSCTL_CONTROL control:1
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volt12 FSCSCY_SYSCTL_VOLTAGE1 volt0:1
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volt5 FSCSCY_SYSCTL_VOLTAGE2 volt1:1
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voltbatt FSCSCY_SYSCTL_VOLTAGE3 volt2:1
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temp1 FSCSCY_SYSCTL_TEMP1 temp0:2
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temp2 FSCSCY_SYSCTL_TEMP2 temp1:2
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temp3 FSCSCY_SYSCTL_TEMP3 temp2:2
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temp4 FSCSCY_SYSCTL_TEMP4 temp3:2
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temp1_state FSCSCY_SYSCTL_TEMP1_STATE temp0:1
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temp2_state FSCSCY_SYSCTL_TEMP2_STATE temp1:1
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temp3_state FSCSCY_SYSCTL_TEMP3_STATE temp2:1
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temp4_state FSCSCY_SYSCTL_TEMP4_STATE temp3:1
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temp1_max FSCSCY_SYSCTL_TEMP1_MAX temp0:3
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temp2_max FSCSCY_SYSCTL_TEMP2_MAX temp1:3
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temp3_max FSCSCY_SYSCTL_TEMP3_MAX temp2:3
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temp4_max FSCSCY_SYSCTL_TEMP4_MAX temp3:3
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fan1 FSCSCY_SYSCTL_FAN1 fan0:4
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fan2 FSCSCY_SYSCTL_FAN2 fan1:4
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fan3 FSCSCY_SYSCTL_FAN3 fan2:4
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fan4 FSCSCY_SYSCTL_FAN4 fan3:4
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fan5 FSCSCY_SYSCTL_FAN5 fan4:4
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fan6 FSCSCY_SYSCTL_FAN6 fan5:4
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fan1_min FSCSCY_SYSCTL_FAN1_MIN fan0:2
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fan2_min FSCSCY_SYSCTL_FAN2_MIN fan1:2
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fan3_min FSCSCY_SYSCTL_FAN3_MIN fan2:2
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fan4_min FSCSCY_SYSCTL_FAN4_MIN fan3:2
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fan5_min FSCSCY_SYSCTL_FAN5_MIN fan4:2
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fan6_min FSCSCY_SYSCTL_FAN6_MIN fan5:2
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fan1_state FSCSCY_SYSCTL_FAN1_STATE fan0:1
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fan2_state FSCSCY_SYSCTL_FAN2_STATE fan1:1
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fan3_state FSCSCY_SYSCTL_FAN3_STATE fan2:1
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fan4_state FSCSCY_SYSCTL_FAN4_STATE fan3:1
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fan5_state FSCSCY_SYSCTL_FAN5_STATE fan4:1
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fan6_state FSCSCY_SYSCTL_FAN6_STATE fan5:1
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fan1_ripple FSCSCY_SYSCTL_FAN1_RIPPLE fan0:3
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fan2_ripple FSCSCY_SYSCTL_FAN2_RIPPLE fan1:3
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fan3_ripple FSCSCY_SYSCTL_FAN3_RIPPLE fan2:3
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fan4_ripple FSCSCY_SYSCTL_FAN3_RIPPLE fan3:3
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fan5_ripple FSCSCY_SYSCTL_FAN3_RIPPLE fan4:3
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fan6_ripple FSCSCY_SYSCTL_FAN3_RIPPLE fan5:3
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wdog_preset FSCSCY_SYSCTL_WDOG_PRESET wdog:1
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wdog_state FSCSCY_SYSCTL_WDOG_STATE wdog:2
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wdog_control FSCSCY_SYSCTL_WDOG_CONTROL wdog:3
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