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@@ -0,0 +1,767 @@
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/*
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* Handling of Ethernet PHY's
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* PHY's communicate with an EMAC either through
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* a Media-Independent Interface (MII), or a Reduced Media-Independent Interface (RMII).
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* The EMAC can poll for PHY ports on 32 different addresses. Each of the PHY ports
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* shall be treated independently.
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*
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*/
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/* Standard includes. */
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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/* FreeRTOS includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include "queue.h"
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#include "semphr.h"
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/* FreeRTOS+TCP includes. */
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#include "FreeRTOS_IP.h"
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#include "FreeRTOS_Sockets.h"
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#include "phyHandling.h"
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#define phyMIN_PHY_ADDRESS 0
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#define phyMAX_PHY_ADDRESS 31
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#if defined( PHY_LS_HIGH_CHECK_TIME_MS ) || defined( PHY_LS_LOW_CHECK_TIME_MS )
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#warning please use the new defines with 'ipconfig' prefix
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#endif
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#ifndef ipconfigPHY_LS_HIGH_CHECK_TIME_MS
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/* Check if the LinkStatus in the PHY is still high after 15 seconds of not
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* receiving packets. */
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#define ipconfigPHY_LS_HIGH_CHECK_TIME_MS 15000UL
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#endif
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#ifndef ipconfigPHY_LS_LOW_CHECK_TIME_MS
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/* Check if the LinkStatus in the PHY is still low every second. */
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#define ipconfigPHY_LS_LOW_CHECK_TIME_MS 1000UL
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#endif
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/* As the following 3 macro's are OK in most situations, and so they're not
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* included in 'FreeRTOSIPConfigDefaults.h'.
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* Users can change their values in the project's 'FreeRTOSIPConfig.h'. */
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#ifndef phyPHY_MAX_RESET_TIME_MS
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#define phyPHY_MAX_RESET_TIME_MS 1000UL
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#endif
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#ifndef phyPHY_MAX_NEGOTIATE_TIME_MS
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#define phyPHY_MAX_NEGOTIATE_TIME_MS 3000UL
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#endif
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#ifndef phySHORT_DELAY_MS
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#define phySHORT_DELAY_MS 50UL
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#endif
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/* Naming and numbering of basic PHY registers. */
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#define phyREG_00_BMCR 0x00U /* Basic Mode Control Register. */
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#define phyREG_01_BMSR 0x01U /* Basic Mode Status Register. */
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#define phyREG_02_PHYSID1 0x02U /* PHYS ID 1 */
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#define phyREG_03_PHYSID2 0x03U /* PHYS ID 2 */
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#define phyREG_04_ADVERTISE 0x04U /* Advertisement control reg */
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/* Naming and numbering of extended PHY registers. */
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#define PHYREG_10_PHYSTS 0x10U /* 16 PHY status register Offset */
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#define phyREG_19_PHYCR 0x19U /* 25 RW PHY Control Register */
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#define phyREG_1F_PHYSPCS 0x1FU /* 31 RW PHY Special Control Status */
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/* Bit fields for 'phyREG_00_BMCR', the 'Basic Mode Control Register'. */
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#define phyBMCR_FULL_DUPLEX 0x0100U /* Full duplex. */
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#define phyBMCR_AN_RESTART 0x0200U /* Auto negotiation restart. */
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#define phyBMCR_ISOLATE 0x0400U /* 1 = Isolates 0 = Normal operation. */
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#define phyBMCR_AN_ENABLE 0x1000U /* Enable auto negotiation. */
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#define phyBMCR_SPEED_100 0x2000U /* Select 100Mbps. */
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#define phyBMCR_RESET 0x8000U /* Reset the PHY. */
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/* Bit fields for 'phyREG_19_PHYCR', the 'PHY Control Register'. */
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#define PHYCR_MDIX_EN 0x8000U /* Enable Auto MDIX. */
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#define PHYCR_MDIX_FORCE 0x4000U /* Force MDIX crossed. */
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#define phyBMSR_AN_COMPLETE 0x0020U /* Auto-Negotiation process completed */
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#define phyBMSR_LINK_STATUS 0x0004U
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#define phyPHYSTS_LINK_STATUS 0x0001U /* PHY Link mask */
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#define phyPHYSTS_SPEED_STATUS 0x0002U /* PHY Speed mask */
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#define phyPHYSTS_DUPLEX_STATUS 0x0004U /* PHY Duplex mask */
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/* Bit fields for 'phyREG_1F_PHYSPCS
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* 001 = 10BASE-T half-duplex
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* 101 = 10BASE-T full-duplex
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* 010 = 100BASE-TX half-duplex
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* 110 = 100BASE-TX full-duplex
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*/
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#define phyPHYSPCS_SPEED_MASK 0x000CU
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#define phyPHYSPCS_SPEED_10 0x0004U
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#define phyPHYSPCS_FULL_DUPLEX 0x0010U
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/*
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* Description of all capabilities that can be advertised to
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* the peer (usually a switch or router).
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*/
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#define phyADVERTISE_CSMA 0x0001U /* Supports IEEE 802.3u: Fast Ethernet at 100 Mbit/s */
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#define phyADVERTISE_10HALF 0x0020U /* Try for 10mbps half-duplex. */
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#define phyADVERTISE_10FULL 0x0040U /* Try for 10mbps full-duplex. */
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#define phyADVERTISE_100HALF 0x0080U /* Try for 100mbps half-duplex. */
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#define phyADVERTISE_100FULL 0x0100U /* Try for 100mbps full-duplex. */
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#define phyADVERTISE_ALL \
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( phyADVERTISE_10HALF | phyADVERTISE_10FULL | \
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phyADVERTISE_100HALF | phyADVERTISE_100FULL | \
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phyADVERTISE_CSMA )
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/* Send a reset command to a set of PHY-ports. */
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static uint32_t xPhyReset( EthernetPhy_t * pxPhyObject,
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uint32_t ulPhyMask );
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static BaseType_t xHas_1F_PHYSPCS( uint32_t ulPhyID )
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{
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BaseType_t xResult;
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switch( ulPhyID )
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{
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case PHY_ID_LAN8720:
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case PHY_ID_LAN8742A:
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case PHY_ID_KSZ8041:
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/*
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* case PHY_ID_KSZ8051: // same ID as 8041
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* case PHY_ID_KSZ8081: // same ID as 8041
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*/
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case PHY_ID_KSZ8081MNXIA:
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case PHY_ID_KSZ8863:
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default:
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/* Most PHY's have a 1F_PHYSPCS */
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xResult = pdTRUE;
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break;
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case PHY_ID_DP83848I:
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xResult = pdFALSE;
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break;
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}
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return xResult;
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}
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/*-----------------------------------------------------------*/
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static BaseType_t xHas_19_PHYCR( uint32_t ulPhyID )
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{
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BaseType_t xResult;
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switch( ulPhyID )
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{
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case PHY_ID_LAN8742A:
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case PHY_ID_DP83848I:
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xResult = pdTRUE;
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break;
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default:
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/* Most PHY's do not have a 19_PHYCR */
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xResult = pdFALSE;
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break;
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}
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return xResult;
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}
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/*-----------------------------------------------------------*/
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/* Initialise the struct and assign a PHY-read and -write function. */
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void vPhyInitialise( EthernetPhy_t * pxPhyObject,
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xApplicationPhyReadHook_t fnPhyRead,
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xApplicationPhyWriteHook_t fnPhyWrite )
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{
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memset( ( void * ) pxPhyObject, 0, sizeof( *pxPhyObject ) );
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pxPhyObject->fnPhyRead = fnPhyRead;
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pxPhyObject->fnPhyWrite = fnPhyWrite;
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}
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/*-----------------------------------------------------------*/
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/* Discover all PHY's connected by polling 32 indexes ( zero-based ) */
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BaseType_t xPhyDiscover( EthernetPhy_t * pxPhyObject )
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{
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BaseType_t xPhyAddress;
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pxPhyObject->xPortCount = 0;
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for( xPhyAddress = phyMIN_PHY_ADDRESS; xPhyAddress <= phyMAX_PHY_ADDRESS; xPhyAddress++ )
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{
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uint32_t ulLowerID;
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pxPhyObject->fnPhyRead( xPhyAddress, phyREG_03_PHYSID2, &ulLowerID );
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/* A valid PHY id can not be all zeros or all ones. */
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if( ( ulLowerID != ( uint16_t ) ~0U ) && ( ulLowerID != ( uint16_t ) 0U ) )
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{
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uint32_t ulUpperID;
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uint32_t ulPhyID;
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pxPhyObject->fnPhyRead( xPhyAddress, phyREG_02_PHYSID1, &ulUpperID );
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ulPhyID = ( ( ( uint32_t ) ulUpperID ) << 16 ) | ( ulLowerID & 0xFFF0 );
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pxPhyObject->ucPhyIndexes[ pxPhyObject->xPortCount ] = xPhyAddress;
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pxPhyObject->ulPhyIDs[ pxPhyObject->xPortCount ] = ulPhyID;
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pxPhyObject->xPortCount++;
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/* See if there is more storage space. */
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if( pxPhyObject->xPortCount == ipconfigPHY_MAX_PORTS )
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{
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break;
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}
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}
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}
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if( pxPhyObject->xPortCount > 0 )
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{
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FreeRTOS_printf( ( "PHY ID %lX\n", pxPhyObject->ulPhyIDs[ 0 ] ) );
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}
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return pxPhyObject->xPortCount;
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}
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/*-----------------------------------------------------------*/
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/* Send a reset command to a set of PHY-ports. */
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static uint32_t xPhyReset( EthernetPhy_t * pxPhyObject,
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uint32_t ulPhyMask )
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{
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uint32_t ulDoneMask, ulConfig;
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TickType_t xRemainingTime;
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TimeOut_t xTimer;
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BaseType_t xPhyIndex;
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/* A bit-mask of PHY ports that are ready. */
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ulDoneMask = 0UL;
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/* Set the RESET bits high. */
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for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )
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{
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BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];
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/* Read Control register. */
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pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig );
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pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, ulConfig | phyBMCR_RESET );
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}
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xRemainingTime = ( TickType_t ) pdMS_TO_TICKS( phyPHY_MAX_RESET_TIME_MS );
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vTaskSetTimeOutState( &xTimer );
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/* The reset should last less than a second. */
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for( ; ; )
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{
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for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )
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{
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BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];
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pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig );
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if( ( ulConfig & phyBMCR_RESET ) == 0 )
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{
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FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET %d ready\n", ( int ) xPhyIndex ) );
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ulDoneMask |= ( 1UL << xPhyIndex );
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}
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}
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if( ulDoneMask == ulPhyMask )
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{
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break;
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}
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if( xTaskCheckForTimeOut( &xTimer, &xRemainingTime ) != pdFALSE )
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{
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FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET timed out ( done 0x%02lX )\n", ulDoneMask ) );
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break;
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}
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/* Block for a while */
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vTaskDelay( pdMS_TO_TICKS( phySHORT_DELAY_MS ) );
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}
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/* Clear the reset bits. */
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for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )
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{
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if( ( ulDoneMask & ( 1UL << xPhyIndex ) ) == 0UL )
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{
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BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];
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/* The reset operation timed out, clear the bit manually. */
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pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig );
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pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, ulConfig & ~phyBMCR_RESET );
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}
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}
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vTaskDelay( pdMS_TO_TICKS( phySHORT_DELAY_MS ) );
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return ulDoneMask;
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}
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/*-----------------------------------------------------------*/
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BaseType_t xPhyConfigure( EthernetPhy_t * pxPhyObject,
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const PhyProperties_t * pxPhyProperties )
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{
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uint32_t ulConfig, ulAdvertise;
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BaseType_t xPhyIndex;
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if( pxPhyObject->xPortCount < 1 )
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{
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FreeRTOS_printf( ( "xPhyConfigure: No PHY's detected.\n" ) );
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return -1;
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}
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/* The expected ID for the 'LAN8742A' is 0x0007c130. */
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/* The expected ID for the 'LAN8720' is 0x0007c0f0. */
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/* The expected ID for the 'DP83848I' is 0x20005C90. */
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/* Set advertise register. */
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if( ( pxPhyProperties->ucSpeed == ( uint8_t ) PHY_SPEED_AUTO ) && ( pxPhyProperties->ucDuplex == ( uint8_t ) PHY_DUPLEX_AUTO ) )
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{
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ulAdvertise = phyADVERTISE_ALL;
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/* Reset auto-negotiation capability. */
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}
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else
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{
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/* Always select protocol 802.3u. */
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ulAdvertise = phyADVERTISE_CSMA;
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if( pxPhyProperties->ucSpeed == ( uint8_t ) PHY_SPEED_AUTO )
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{
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if( pxPhyProperties->ucDuplex == ( uint8_t ) PHY_DUPLEX_FULL )
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{
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ulAdvertise |= phyADVERTISE_10FULL | phyADVERTISE_100FULL;
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}
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else
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{
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ulAdvertise |= phyADVERTISE_10HALF | phyADVERTISE_100HALF;
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}
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}
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else if( pxPhyProperties->ucDuplex == ( uint8_t ) PHY_DUPLEX_AUTO )
|
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{
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if( pxPhyProperties->ucSpeed == ( uint8_t ) PHY_SPEED_10 )
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{
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ulAdvertise |= phyADVERTISE_10FULL | phyADVERTISE_10HALF;
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}
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else
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{
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ulAdvertise |= phyADVERTISE_100FULL | phyADVERTISE_100HALF;
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}
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}
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else if( pxPhyProperties->ucSpeed == ( uint8_t ) PHY_SPEED_100 )
|
||||
{
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if( pxPhyProperties->ucDuplex == ( uint8_t ) PHY_DUPLEX_FULL )
|
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{
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ulAdvertise |= phyADVERTISE_100FULL;
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}
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else
|
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{
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ulAdvertise |= phyADVERTISE_100HALF;
|
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}
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}
|
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else
|
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{
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if( pxPhyProperties->ucDuplex == ( uint8_t ) PHY_DUPLEX_FULL )
|
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{
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ulAdvertise |= phyADVERTISE_10FULL;
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}
|
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else
|
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{
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ulAdvertise |= phyADVERTISE_10HALF;
|
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}
|
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}
|
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}
|
||||
|
||||
/* Send a reset command to a set of PHY-ports. */
|
||||
xPhyReset( pxPhyObject, xPhyGetMask( pxPhyObject ) );
|
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|
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for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )
|
||||
{
|
||||
BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];
|
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uint32_t ulPhyID = pxPhyObject->ulPhyIDs[ xPhyIndex ];
|
||||
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/* Write advertise register. */
|
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pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_04_ADVERTISE, ulAdvertise );
|
||||
|
||||
/*
|
||||
* AN_EN AN1 AN0 Forced Mode
|
||||
* 0 0 0 10BASE-T, Half-Duplex
|
||||
* 0 0 1 10BASE-T, Full-Duplex
|
||||
* 0 1 0 100BASE-TX, Half-Duplex
|
||||
* 0 1 1 100BASE-TX, Full-Duplex
|
||||
* AN_EN AN1 AN0 Advertised Mode
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* 1 0 0 10BASE-T, Half/Full-Duplex
|
||||
* 1 0 1 100BASE-TX, Half/Full-Duplex
|
||||
* 1 1 0 10BASE-T Half-Duplex
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* 100BASE-TX, Half-Duplex
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* 1 1 1 10BASE-T, Half/Full-Duplex
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* 100BASE-TX, Half/Full-Duplex
|
||||
*/
|
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/* Read Control register. */
|
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pxPhyObject->fnPhyRead( xPhyAddress, phyREG_00_BMCR, &ulConfig );
|
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|
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ulConfig &= ~( phyBMCR_SPEED_100 | phyBMCR_FULL_DUPLEX );
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ulConfig |= phyBMCR_AN_ENABLE;
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if( ( pxPhyProperties->ucSpeed == ( uint8_t ) PHY_SPEED_100 ) || ( pxPhyProperties->ucSpeed == ( uint8_t ) PHY_SPEED_AUTO ) )
|
||||
{
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ulConfig |= phyBMCR_SPEED_100;
|
||||
}
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||||
else if( pxPhyProperties->ucSpeed == ( uint8_t ) PHY_SPEED_10 )
|
||||
{
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||||
ulConfig &= ~phyBMCR_SPEED_100;
|
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}
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||||
|
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if( ( pxPhyProperties->ucDuplex == ( uint8_t ) PHY_DUPLEX_FULL ) || ( pxPhyProperties->ucDuplex == ( uint8_t ) PHY_DUPLEX_AUTO ) )
|
||||
{
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ulConfig |= phyBMCR_FULL_DUPLEX;
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||||
}
|
||||
else if( pxPhyProperties->ucDuplex == ( uint8_t ) PHY_DUPLEX_HALF )
|
||||
{
|
||||
ulConfig &= ~phyBMCR_FULL_DUPLEX;
|
||||
}
|
||||
|
||||
if( xHas_19_PHYCR( ulPhyID ) )
|
||||
{
|
||||
uint32_t ulPhyControl;
|
||||
/* Read PHY Control register. */
|
||||
pxPhyObject->fnPhyRead( xPhyAddress, phyREG_19_PHYCR, &ulPhyControl );
|
||||
|
||||
/* Clear bits which might get set: */
|
||||
ulPhyControl &= ~( PHYCR_MDIX_EN | PHYCR_MDIX_FORCE );
|
||||
|
||||
if( pxPhyProperties->ucMDI_X == PHY_MDIX_AUTO )
|
||||
{
|
||||
ulPhyControl |= PHYCR_MDIX_EN;
|
||||
}
|
||||
else if( pxPhyProperties->ucMDI_X == PHY_MDIX_CROSSED )
|
||||
{
|
||||
/* Force direct link = Use crossed RJ45 cable. */
|
||||
ulPhyControl &= ~PHYCR_MDIX_FORCE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Force crossed link = Use direct RJ45 cable. */
|
||||
ulPhyControl |= PHYCR_MDIX_FORCE;
|
||||
}
|
||||
|
||||
/* update PHY Control Register. */
|
||||
pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_19_PHYCR, ulPhyControl );
|
||||
}
|
||||
|
||||
FreeRTOS_printf( ( "+TCP: advertise: %04lX config %04lX\n", ulAdvertise, ulConfig ) );
|
||||
}
|
||||
|
||||
/* Keep these values for later use. */
|
||||
pxPhyObject->ulBCRValue = ulConfig & ~phyBMCR_ISOLATE;
|
||||
pxPhyObject->ulACRValue = ulAdvertise;
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* xPhyFixedValue(): this function is called in case auto-negotiation is disabled.
|
||||
* The caller has set the values in 'xPhyPreferences' (ucDuplex and ucSpeed).
|
||||
* The PHY register phyREG_00_BMCR will be set for every connected PHY that matches
|
||||
* with ulPhyMask. */
|
||||
BaseType_t xPhyFixedValue( EthernetPhy_t * pxPhyObject,
|
||||
uint32_t ulPhyMask )
|
||||
{
|
||||
BaseType_t xPhyIndex;
|
||||
uint32_t ulValue, ulBitMask = ( uint32_t ) 1U;
|
||||
|
||||
ulValue = ( uint32_t ) 0U;
|
||||
|
||||
if( pxPhyObject->xPhyPreferences.ucDuplex == PHY_DUPLEX_FULL )
|
||||
{
|
||||
ulValue |= phyBMCR_FULL_DUPLEX;
|
||||
}
|
||||
|
||||
if( pxPhyObject->xPhyPreferences.ucSpeed == PHY_SPEED_100 )
|
||||
{
|
||||
ulValue |= phyBMCR_SPEED_100;
|
||||
}
|
||||
|
||||
for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )
|
||||
{
|
||||
if( ( ulPhyMask & ulBitMask ) != 0lu )
|
||||
{
|
||||
BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];
|
||||
|
||||
/* Enable Auto-Negotiation. */
|
||||
pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, ulValue );
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* xPhyStartAutoNegotiation() is the alternative xPhyFixedValue():
|
||||
* It sets the BMCR_AN_RESTART bit and waits for the auto-negotiation completion
|
||||
* ( phyBMSR_AN_COMPLETE ). */
|
||||
BaseType_t xPhyStartAutoNegotiation( EthernetPhy_t * pxPhyObject,
|
||||
uint32_t ulPhyMask )
|
||||
{
|
||||
uint32_t xPhyIndex, ulDoneMask, ulBitMask;
|
||||
uint32_t ulPHYLinkStatus, ulRegValue;
|
||||
TickType_t xRemainingTime;
|
||||
TimeOut_t xTimer;
|
||||
|
||||
if( ulPhyMask == ( uint32_t ) 0U )
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
for( xPhyIndex = 0; xPhyIndex < ( uint32_t ) pxPhyObject->xPortCount; xPhyIndex++ )
|
||||
{
|
||||
if( ( ulPhyMask & ( 1lu << xPhyIndex ) ) != 0lu )
|
||||
{
|
||||
BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];
|
||||
|
||||
/* Enable Auto-Negotiation. */
|
||||
pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_04_ADVERTISE, pxPhyObject->ulACRValue );
|
||||
pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, pxPhyObject->ulBCRValue | phyBMCR_AN_RESTART );
|
||||
}
|
||||
}
|
||||
|
||||
xRemainingTime = ( TickType_t ) pdMS_TO_TICKS( phyPHY_MAX_NEGOTIATE_TIME_MS );
|
||||
vTaskSetTimeOutState( &xTimer );
|
||||
ulDoneMask = 0;
|
||||
|
||||
/* Wait until the auto-negotiation will be completed */
|
||||
for( ; ; )
|
||||
{
|
||||
ulBitMask = ( uint32_t ) 1U;
|
||||
|
||||
for( xPhyIndex = 0; xPhyIndex < ( uint32_t ) pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )
|
||||
{
|
||||
if( ( ulPhyMask & ulBitMask ) != 0lu )
|
||||
{
|
||||
if( ( ulDoneMask & ulBitMask ) == 0lu )
|
||||
{
|
||||
BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];
|
||||
|
||||
pxPhyObject->fnPhyRead( xPhyAddress, phyREG_01_BMSR, &ulRegValue );
|
||||
|
||||
if( ( ulRegValue & phyBMSR_AN_COMPLETE ) != 0 )
|
||||
{
|
||||
ulDoneMask |= ulBitMask;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if( ulPhyMask == ulDoneMask )
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
if( xTaskCheckForTimeOut( &xTimer, &xRemainingTime ) != pdFALSE )
|
||||
{
|
||||
FreeRTOS_printf( ( "xPhyStartAutoNegotiation: phyBMCR_RESET timed out ( done 0x%02lX )\n", ulDoneMask ) );
|
||||
break;
|
||||
}
|
||||
|
||||
vTaskDelay( pdMS_TO_TICKS( phySHORT_DELAY_MS ) );
|
||||
}
|
||||
|
||||
if( ulDoneMask != ( uint32_t ) 0U )
|
||||
{
|
||||
ulBitMask = ( uint32_t ) 1U;
|
||||
pxPhyObject->ulLinkStatusMask &= ~( ulDoneMask );
|
||||
|
||||
for( xPhyIndex = 0; xPhyIndex < ( uint32_t ) pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )
|
||||
{
|
||||
BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];
|
||||
uint32_t ulPhyID = pxPhyObject->ulPhyIDs[ xPhyIndex ];
|
||||
|
||||
if( ( ulDoneMask & ulBitMask ) == ( uint32_t ) 0U )
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Clear the 'phyBMCR_AN_RESTART' bit. */
|
||||
pxPhyObject->fnPhyWrite( xPhyAddress, phyREG_00_BMCR, pxPhyObject->ulBCRValue );
|
||||
|
||||
pxPhyObject->fnPhyRead( xPhyAddress, phyREG_01_BMSR, &ulRegValue );
|
||||
|
||||
if( ( ulRegValue & phyBMSR_LINK_STATUS ) != 0 )
|
||||
{
|
||||
ulPHYLinkStatus |= phyBMSR_LINK_STATUS;
|
||||
pxPhyObject->ulLinkStatusMask |= ulBitMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
ulPHYLinkStatus &= ~( phyBMSR_LINK_STATUS );
|
||||
}
|
||||
|
||||
if( ulPhyID == PHY_ID_KSZ8081MNXIA )
|
||||
{
|
||||
uint32_t ulControlStatus;
|
||||
|
||||
pxPhyObject->fnPhyRead( xPhyAddress, 0x1E, &ulControlStatus );
|
||||
|
||||
switch( ulControlStatus & 0x07 )
|
||||
{
|
||||
case 0x01:
|
||||
case 0x05:
|
||||
/* [001] = 10BASE-T half-duplex */
|
||||
/* [101] = 10BASE-T full-duplex */
|
||||
/* 10 Mbps. */
|
||||
ulRegValue |= phyPHYSTS_SPEED_STATUS;
|
||||
break;
|
||||
|
||||
case 0x02:
|
||||
case 0x06:
|
||||
/* [010] = 100BASE-TX half-duplex */
|
||||
/* [110] = 100BASE-TX full-duplex */
|
||||
break;
|
||||
}
|
||||
|
||||
switch( ulControlStatus & 0x07 )
|
||||
{
|
||||
case 0x05:
|
||||
case 0x06:
|
||||
/* [101] = 10BASE-T full-duplex */
|
||||
/* [110] = 100BASE-TX full-duplex */
|
||||
/* Full duplex. */
|
||||
ulRegValue |= phyPHYSTS_DUPLEX_STATUS;
|
||||
break;
|
||||
|
||||
case 0x01:
|
||||
case 0x02:
|
||||
/* [001] = 10BASE-T half-duplex */
|
||||
/* [010] = 100BASE-TX half-duplex */
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if( xHas_1F_PHYSPCS( ulPhyID ) )
|
||||
{
|
||||
/* 31 RW PHY Special Control Status */
|
||||
uint32_t ulControlStatus;
|
||||
|
||||
pxPhyObject->fnPhyRead( xPhyAddress, phyREG_1F_PHYSPCS, &ulControlStatus );
|
||||
ulRegValue = 0;
|
||||
|
||||
if( ( ulControlStatus & phyPHYSPCS_FULL_DUPLEX ) != 0 )
|
||||
{
|
||||
ulRegValue |= phyPHYSTS_DUPLEX_STATUS;
|
||||
}
|
||||
|
||||
if( ( ulControlStatus & phyPHYSPCS_SPEED_MASK ) == phyPHYSPCS_SPEED_10 )
|
||||
{
|
||||
ulRegValue |= phyPHYSTS_SPEED_STATUS;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Read the result of the auto-negotiation. */
|
||||
pxPhyObject->fnPhyRead( xPhyAddress, PHYREG_10_PHYSTS, &ulRegValue );
|
||||
}
|
||||
|
||||
FreeRTOS_printf( ( "Autonego ready: %08lx: %s duplex %u mbit %s status\n",
|
||||
ulRegValue,
|
||||
( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) ? "full" : "half",
|
||||
( ulRegValue & phyPHYSTS_SPEED_STATUS ) ? 10 : 100,
|
||||
( ( ulPHYLinkStatus |= phyBMSR_LINK_STATUS ) != 0 ) ? "high" : "low" ) );
|
||||
|
||||
if( ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) != ( uint32_t ) 0U )
|
||||
{
|
||||
pxPhyObject->xPhyProperties.ucDuplex = PHY_DUPLEX_FULL;
|
||||
}
|
||||
else
|
||||
{
|
||||
pxPhyObject->xPhyProperties.ucDuplex = PHY_DUPLEX_HALF;
|
||||
}
|
||||
|
||||
if( ( ulRegValue & phyPHYSTS_SPEED_STATUS ) != 0 )
|
||||
{
|
||||
pxPhyObject->xPhyProperties.ucSpeed = PHY_SPEED_10;
|
||||
}
|
||||
else
|
||||
{
|
||||
pxPhyObject->xPhyProperties.ucSpeed = PHY_SPEED_100;
|
||||
}
|
||||
}
|
||||
} /* if( ulDoneMask != ( uint32_t) 0U ) */
|
||||
|
||||
return 0;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xPhyCheckLinkStatus( EthernetPhy_t * pxPhyObject,
|
||||
BaseType_t xHadReception )
|
||||
{
|
||||
uint32_t ulStatus, ulBitMask = 1U;
|
||||
BaseType_t xPhyIndex;
|
||||
BaseType_t xNeedCheck = pdFALSE;
|
||||
|
||||
if( xHadReception > 0 )
|
||||
{
|
||||
/* A packet was received. No need to check for the PHY status now,
|
||||
* but set a timer to check it later on. */
|
||||
vTaskSetTimeOutState( &( pxPhyObject->xLinkStatusTimer ) );
|
||||
pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_HIGH_CHECK_TIME_MS );
|
||||
|
||||
for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )
|
||||
{
|
||||
if( ( pxPhyObject->ulLinkStatusMask & ulBitMask ) == 0UL )
|
||||
{
|
||||
pxPhyObject->ulLinkStatusMask |= ulBitMask;
|
||||
FreeRTOS_printf( ( "xPhyCheckLinkStatus: PHY LS now %02lX\n", pxPhyObject->ulLinkStatusMask ) );
|
||||
xNeedCheck = pdTRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if( xTaskCheckForTimeOut( &( pxPhyObject->xLinkStatusTimer ), &( pxPhyObject->xLinkStatusRemaining ) ) != pdFALSE )
|
||||
{
|
||||
/* Frequent checking the PHY Link Status can affect for the performance of Ethernet controller.
|
||||
* As long as packets are received, no polling is needed.
|
||||
* Otherwise, polling will be done when the 'xLinkStatusTimer' expires. */
|
||||
for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )
|
||||
{
|
||||
BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];
|
||||
|
||||
if( pxPhyObject->fnPhyRead( xPhyAddress, phyREG_01_BMSR, &ulStatus ) == 0 )
|
||||
{
|
||||
if( !!( pxPhyObject->ulLinkStatusMask & ulBitMask ) != !!( ulStatus & phyBMSR_LINK_STATUS ) )
|
||||
{
|
||||
if( ( ulStatus & phyBMSR_LINK_STATUS ) != 0 )
|
||||
{
|
||||
pxPhyObject->ulLinkStatusMask |= ulBitMask;
|
||||
}
|
||||
else
|
||||
{
|
||||
pxPhyObject->ulLinkStatusMask &= ~( ulBitMask );
|
||||
}
|
||||
|
||||
FreeRTOS_printf( ( "xPhyCheckLinkStatus: PHY LS now %02lX\n", pxPhyObject->ulLinkStatusMask ) );
|
||||
xNeedCheck = pdTRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
vTaskSetTimeOutState( &( pxPhyObject->xLinkStatusTimer ) );
|
||||
|
||||
if( ( pxPhyObject->ulLinkStatusMask & ( ulBitMask >> 1 ) ) != 0 )
|
||||
{
|
||||
/* The link status is high, so don't poll the PHY too often. */
|
||||
pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_HIGH_CHECK_TIME_MS );
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The link status is low, polling may be done more frequently. */
|
||||
pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_LOW_CHECK_TIME_MS );
|
||||
}
|
||||
}
|
||||
|
||||
return xNeedCheck;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,81 @@
|
||||
This is a FreeeRTOS+TCP driver that works for both STM32F4xx and STM32F7xx parts.
|
||||
|
||||
The code of stm32fxx_hal_eth.c is based on both drivers as provided by ST.
|
||||
|
||||
These modules should be included:
|
||||
|
||||
NetworkInterface.c
|
||||
stm32fxx_hal_eth.c
|
||||
|
||||
It is assumed that one of these words are defined:
|
||||
|
||||
STM32F7xx
|
||||
STM32F407xx
|
||||
STM32F417xx
|
||||
STM32F427xx
|
||||
STM32F437xx
|
||||
STM32F429xx
|
||||
STM32F439xx
|
||||
|
||||
The driver has been tested on both Eval and Discovery boards with both STM32F4 and STM32F7.
|
||||
|
||||
Recommended settings for STM32Fxx Network Interface:
|
||||
|
||||
// Defined in FreeRTOSIPConfig.h
|
||||
|
||||
#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 1
|
||||
#define ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM 1
|
||||
#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1
|
||||
#define ipconfigZERO_COPY_RX_DRIVER 1
|
||||
#define ipconfigZERO_COPY_TX_DRIVER 1
|
||||
#define ipconfigUSE_LINKED_RX_MESSAGES 1
|
||||
|
||||
// Defined in stm32f4xx_hal_conf.h
|
||||
#define ETH_RXBUFNB 3 or 4
|
||||
#define ETH_TXBUFNB 2 or 3
|
||||
#define ETH_RX_BUF_SIZE ( ipconfigNETWORK_MTU + 36 )
|
||||
#define ETH_TX_BUF_SIZE ( ipconfigNETWORK_MTU + 36 )
|
||||
|
||||
The best size for 'ETH_RXBUFNB' and 'ETH_TXBUFNB' depends on the speed of the CPU. These macro's define the number of DMA buffers for reception and for transmission.
|
||||
In general, if the CPU is very fast, you will need less buffers. You can obtain an estimate empirically.
|
||||
|
||||
The optimal value of 'ETH_RX_BUF_SIZE' and 'ETH_TX_BUF_SIZE' depends on the actual value of 'ipconfigNETWORK_MTU'.
|
||||
When MTU is 1500, MTU+36 becomes a well-aligned buffer of 1536 bytes ( 0x600 ).
|
||||
When MTU is 1200, MTU+48 will make 1248 ( 0x4E0 ), which is also well aligned.
|
||||
|
||||
Having well aligned buffers is important for CPU with memory cache. Often the caching system divides memory in blocks of 32 bytes. When two buffers share the same cache buffer, you are bound to see data errors.
|
||||
|
||||
Without memory caching, let the size be at least a multiple of 8 ( for DMA ), and make it at least "ipconfigNETWORK_MTU + 14".
|
||||
|
||||
STM32F7xx only:
|
||||
|
||||
Networkinterface.c will place the 2 DMA tables in a special section called 'first_data'.
|
||||
In case 'BufferAllocation_1.c' is used, the network packets will also be declared in this section 'first_data'.
|
||||
As long as the part has no caching, this section can be placed anywhere in RAM.
|
||||
On an STM32F7 with an L1 data cache, it shall be placed in the first 64KB of RAM, which is always uncached.
|
||||
The linker script must be changed for this, for instance as follows:
|
||||
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; // create a global symbol at data start
|
||||
+ *(.first_data) // .first_data sections
|
||||
*(.data) // .data sections
|
||||
*(.data*) // .data* sections
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; // define a global symbol at data end
|
||||
} >RAM AT> FLASH
|
||||
|
||||
|
||||
The driver contains these files:
|
||||
|
||||
stm32fxx_hal_eth.c
|
||||
stm32f2xx_hal_eth.h
|
||||
stm32f4xx_hal_eth.h
|
||||
stm32f7xx_hal_eth.h
|
||||
stm32fxx_hal_eth.h
|
||||
|
||||
These files are copied from ST's HAL library. These work both for STM32F4 and STM32F7.
|
||||
Please remove or rename these files from the HAL distribution that you are using.
|
||||
|
||||
@@ -0,0 +1,6 @@
|
||||
/*
|
||||
* The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to
|
||||
* a single module that works for both parts: "stm32fxx_hal_eth"
|
||||
*/
|
||||
|
||||
#include "stm32fxx_hal_eth.h"
|
||||
@@ -0,0 +1,6 @@
|
||||
/*
|
||||
* The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to
|
||||
* a single module that works for both parts: "stm32fxx_hal_eth"
|
||||
*/
|
||||
|
||||
#include "stm32fxx_hal_eth.h"
|
||||
@@ -0,0 +1,6 @@
|
||||
/*
|
||||
* The Ethernet header files for STM32F2, STM32F4 and STM32F7 have been merged to
|
||||
* a single module that works for both parts: "stm32fxx_hal_eth"
|
||||
*/
|
||||
|
||||
#include "stm32fxx_hal_eth.h"
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,128 @@
|
||||
/*
|
||||
* Handling of Ethernet PHY's
|
||||
* PHY's communicate with an EMAC either through
|
||||
* a Media-Independent Interface (MII), or a Reduced Media-Independent Interface (RMII).
|
||||
* The EMAC can poll for PHY ports on 32 different addresses. Each of the PHY ports
|
||||
* shall be treated independently.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef PHYHANDLING_H
|
||||
|
||||
#define PHYHANDLING_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef ipconfigPHY_MAX_PORTS
|
||||
/* There can be at most 32 PHY ports, but in most cases there are 4 or less. */
|
||||
#define ipconfigPHY_MAX_PORTS 4
|
||||
#endif
|
||||
|
||||
/* A generic user-provided function that reads from the PHY-port at 'xAddress'( 0-based ). A 16-bit value shall be stored in
|
||||
* '*pulValue'. xRegister is the register number ( 0 .. 31 ). In fact all PHY registers are 16-bit.
|
||||
* Return non-zero in case the action failed. */
|
||||
typedef BaseType_t ( * xApplicationPhyReadHook_t )( BaseType_t xAddress,
|
||||
BaseType_t xRegister,
|
||||
uint32_t * pulValue );
|
||||
|
||||
/* A generic user-provided function that writes 'ulValue' to the
|
||||
* PHY-port at 'xAddress' ( 0-based ). xRegister is the register number ( 0 .. 31 ).
|
||||
* Return non-zero in case the action failed. */
|
||||
typedef BaseType_t ( * xApplicationPhyWriteHook_t )( BaseType_t xAddress,
|
||||
BaseType_t xRegister,
|
||||
uint32_t ulValue );
|
||||
|
||||
typedef struct xPhyProperties
|
||||
{
|
||||
uint8_t ucSpeed;
|
||||
uint8_t ucMDI_X; /* MDI-X : Medium Dependent Interface - Crossover */
|
||||
uint8_t ucDuplex;
|
||||
uint8_t ucSpare;
|
||||
} PhyProperties_t;
|
||||
|
||||
typedef struct xEthernetPhy
|
||||
{
|
||||
xApplicationPhyReadHook_t fnPhyRead;
|
||||
xApplicationPhyWriteHook_t fnPhyWrite;
|
||||
uint32_t ulPhyIDs[ ipconfigPHY_MAX_PORTS ];
|
||||
uint8_t ucPhyIndexes[ ipconfigPHY_MAX_PORTS ];
|
||||
TimeOut_t xLinkStatusTimer;
|
||||
TickType_t xLinkStatusRemaining;
|
||||
BaseType_t xPortCount;
|
||||
uint32_t ulBCRValue;
|
||||
uint32_t ulACRValue;
|
||||
uint32_t ulLinkStatusMask;
|
||||
PhyProperties_t xPhyPreferences;
|
||||
PhyProperties_t xPhyProperties;
|
||||
} EthernetPhy_t;
|
||||
|
||||
/* Some defines used internally here to indicate preferences about speed, MDIX
|
||||
* (wired direct or crossed), and duplex (half or full). */
|
||||
|
||||
/* Values for PhyProperties_t::ucSpeed : */
|
||||
#define PHY_SPEED_10 1
|
||||
#define PHY_SPEED_100 2
|
||||
#define PHY_SPEED_AUTO 3
|
||||
|
||||
/* Values for PhyProperties_t::ucMDI_X : */
|
||||
#define PHY_MDIX_DIRECT 1
|
||||
#define PHY_MDIX_CROSSED 2
|
||||
#define PHY_MDIX_AUTO 3
|
||||
|
||||
/* Values for PhyProperties_t::ucDuplex : */
|
||||
#define PHY_DUPLEX_HALF 1
|
||||
#define PHY_DUPLEX_FULL 2
|
||||
#define PHY_DUPLEX_AUTO 3
|
||||
|
||||
/* ID's of supported PHY's : */
|
||||
#define PHY_ID_LAN8742A 0x0007c130
|
||||
#define PHY_ID_LAN8720 0x0007c0f0
|
||||
|
||||
#define PHY_ID_KSZ8041 0x000010A1
|
||||
#define PHY_ID_KSZ8051 0x000010A1
|
||||
#define PHY_ID_KSZ8081 0x000010A1
|
||||
|
||||
#define PHY_ID_KSZ8863 0x00221430
|
||||
#define PHY_ID_KSZ8081MNXIA 0x00221560
|
||||
|
||||
#define PHY_ID_DP83848I 0x20005C90
|
||||
|
||||
|
||||
/* Initialise the struct and assign a PHY-read and -write function. */
|
||||
void vPhyInitialise( EthernetPhy_t * pxPhyObject,
|
||||
xApplicationPhyReadHook_t fnPhyRead,
|
||||
xApplicationPhyWriteHook_t fnPhyWrite );
|
||||
|
||||
/* Discover all PHY's connected by polling 32 indexes ( zero-based ) */
|
||||
BaseType_t xPhyDiscover( EthernetPhy_t * pxPhyObject );
|
||||
|
||||
/* Send a reset command to the connected PHY ports and send configuration. */
|
||||
BaseType_t xPhyConfigure( EthernetPhy_t * pxPhyObject,
|
||||
const PhyProperties_t * pxPhyProperties );
|
||||
|
||||
/* Give a command to start auto negotiation on a set of PHY port's. */
|
||||
BaseType_t xPhyStartAutoNegotiation( EthernetPhy_t * pxPhyObject,
|
||||
uint32_t ulPhyMask );
|
||||
|
||||
/* Do not use auto negotiation but use predefined values from 'pxPhyObject->xPhyPreferences'. */
|
||||
BaseType_t xPhyFixedValue( EthernetPhy_t * pxPhyObject,
|
||||
uint32_t ulPhyMask );
|
||||
|
||||
/* Check the current Link Status.
|
||||
* 'xHadReception' : make this true if a packet has been received since the
|
||||
* last call to this function. */
|
||||
BaseType_t xPhyCheckLinkStatus( EthernetPhy_t * pxPhyObject,
|
||||
BaseType_t xHadReception );
|
||||
|
||||
/* Get the bitmask of a given 'EthernetPhy_t'. */
|
||||
#define xPhyGetMask( pxPhyObject ) \
|
||||
( ( ( ( uint32_t ) 1u ) << ( pxPhyObject )->xPortCount ) - 1u )
|
||||
|
||||
#ifdef __cplusplus
|
||||
} /* extern "C" */
|
||||
#endif
|
||||
|
||||
#endif /* ifndef PHYHANDLING_H */
|
||||
Reference in new issue
Block a user