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FreeRTOS w/blink works

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cpq committed 2021-05-11 20:44:14 +01:00
1 parent c44549bfa5
commit 151e375091
5 files changed
+46 -33
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examples/stm32/stm32f1/boot.s
+26 -22
View File
@@ -1,29 +1,33 @@
.cpu cortex-m3
.thumb
.word _estack /* stack top address */
.word _reset /* 1 Reset */
.word spin /* 2 NMI */
.word spin /* 3 Hard Fault */
.word spin /* 4 MM Fault */
.word spin /* 5 Bus Fault */
.word spin /* 6 Usage Fault */
.word spin /* 7 RESERVED */
.word spin /* 8 RESERVED */
.word spin /* 9 RESERVED*/
.word spin /* 10 RESERVED */
.word spin /* 11 SV call */
.word spin /* 12 Debug reserved */
.word spin /* 13 RESERVED */
.word spin /* 14 PendSV */
.word spin /* 15 SysTick */
.word spin /* 16 IRQ0 */
.word spin /* 17 IRQ1 */
.word spin /* 18 IRQ2 */
.word spin /* 19 ... */
/* On to IRQ67 */
.word _estack // 0 Stack top address
.word _reset // 1 Reset
.word pass // 2 NMI
.word halt // 3 Hard Fault
.word halt // 4 MM Fault
.word halt // 5 Bus Fault
.word halt // 6 Usage Fault
.word halt // 7 RESERVED
.word halt // 8 RESERVED
.word halt // 9 RESERVED
.word halt // 10 RESERVED
.word SVC_handler // 11 SV call
.word halt // 12 Debug reserved
.word halt // 13 RESERVED
.word pending_SV_handler // 14 PendSV
.word SysTick_handler // 15 SysTick
.word pass // 16 IRQ0
.word halt // 17 IRQ1
// On to IRQ67
.word halt,halt,halt,halt,halt,halt,halt,halt,halt,halt
.word halt,halt,halt,halt,halt,halt,halt,halt,halt,halt
.word halt,halt,halt,halt,halt,halt,halt,halt,halt,halt
.word halt,halt,halt,halt,halt,halt,halt,halt,halt,halt
.word halt,halt,halt,halt,halt,halt,halt,halt,halt,halt
spin: b spin
halt: b halt
pass: BX lr
.thumb_func
.global _reset
examples/stm32/stm32f1/device.h
+11
View File
@@ -13,6 +13,17 @@ static inline void led_toggle(void) {
}
static inline void init_hardware(void) {
RCC->CR |= (RCC_CR_HSEON);
while (!(RCC->CR & RCC_CR_HSERDY)) (void) 0;
RCC->CFGR &= ~(RCC_CFGR_SW);
RCC->CFGR |= (RCC_CFGR_SW_HSE);
RCC->CFGR &= ~(RCC_CFGR_PLLMULL);
RCC->CFGR |= (RCC_CFGR_PLLMULL9);
RCC->CR |= (RCC_CR_PLLON);
while (!(RCC->CR & RCC_CR_PLLRDY)) (void) 0;
RCC->CFGR &= ~(RCC_CFGR_SW);
RCC->CFGR |= (RCC_CFGR_SW_PLL);
RCC->APB2ENR |= BIT(2) | BIT(3) | BIT(4); // Init GPIO banks A,B,C
gpio_init(LED1, OUTPUT); // Set LED
}
examples/stm32/stm32f1/mcu.h
+2
View File
@@ -15,6 +15,8 @@ static inline void setreg(volatile uint32_t *r, uint32_t clear_mask, uint32_t se
// RCC registers, TRM section 7.3, memory map section 3.3
struct rcc { volatile uint32_t CR, CFGR, CIR, APB2RSTR, APB1RSTR, AHBENR, APB2ENR, APB1ENR, BDCR, CSR; };
#define RCC ((struct rcc *) 0x40021000)
enum {RCC_CR_HSEON = BIT(16), RCC_CR_HSERDY = BIT(17), RCC_CR_PLLON = BIT(24), RCC_CR_PLLRDY = BIT(25)};
enum {RCC_CFGR_SW = 3, RCC_CFGR_SW_HSI = 0, RCC_CFGR_SW_HSE = 1, RCC_CFGR_SW_PLL = 2, RCC_CFGR_PLLMULL = (15U << 18), RCC_CFGR_PLLMULL9 = (7U << 18)};
static inline void init_ram(void) {
extern uint32_t _bss_start, _bss_end;