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prefix PHY-related constants
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@@ -48,7 +48,12 @@ static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_64BIT_ALIGNED;
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_64BIT_ALIGNED;
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static struct mg_tcpip_if *s_ifp; // MIP interface
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enum { PHY_BCR = 0, PHY_BSR = 1, PHY_ID1 = 2, PHY_ID2 = 3 };
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enum {
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MG_PHYREG_BCR = 0,
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MG_PHYREG_BSR = 1,
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MG_PHYREG_ID1 = 2,
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MG_PHYREG_ID2 = 3
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};
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static uint16_t enet_phy_read(uint8_t addr, uint8_t reg) {
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ENET->EIR |= MG_BIT(23); // MII interrupt clear
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@@ -65,8 +70,8 @@ static void enet_phy_write(uint8_t addr, uint8_t reg, uint16_t val) {
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}
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static uint32_t enet_phy_id(uint8_t addr) {
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uint16_t phy_id1 = enet_phy_read(addr, PHY_ID1);
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uint16_t phy_id2 = enet_phy_read(addr, PHY_ID2);
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uint16_t phy_id1 = enet_phy_read(addr, MG_PHYREG_ID1);
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uint16_t phy_id2 = enet_phy_read(addr, MG_PHYREG_ID2);
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return (uint32_t) phy_id1 << 16 | phy_id2;
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}
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@@ -100,8 +105,9 @@ static bool mg_tcpip_driver_imxrt_init(struct mg_tcpip_if *ifp) {
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int cr = (d == NULL || d->mdc_cr < 0) ? 24 : d->mdc_cr;
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ENET->MSCR = (1 << 8) | ((cr & 0x3f) << 1); // HOLDTIME 2 clks
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enet_phy_write(d->phy_addr, PHY_BCR, MG_BIT(15)); // Reset PHY
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enet_phy_write(d->phy_addr, PHY_BCR, MG_BIT(12)); // Set autonegotiation
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enet_phy_write(d->phy_addr, MG_PHYREG_BCR, MG_BIT(15)); // Reset PHY
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enet_phy_write(d->phy_addr, MG_PHYREG_BCR,
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MG_BIT(12)); // Set autonegotiation
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// PHY: Enable 50 MHz external ref clock at XI (preserve defaults)
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uint32_t id = enet_phy_id(d->phy_addr);
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@@ -167,7 +173,7 @@ static size_t mg_tcpip_driver_imxrt_tx(const void *buf, size_t len,
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static bool mg_tcpip_driver_imxrt_up(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_imxrt_data *d =
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(struct mg_tcpip_driver_imxrt_data *) ifp->driver_data;
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uint32_t bsr = enet_phy_read(d->phy_addr, PHY_BSR);
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uint32_t bsr = enet_phy_read(d->phy_addr, MG_PHYREG_BSR);
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bool up = bsr & MG_BIT(2) ? 1 : 0;
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if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up
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// tmp = reg with flags set to the most likely situation: 100M full-duplex
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