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Reorganized NXP examples
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@@ -0,0 +1 @@
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See the example at https://github.com/mongoose-examples/frdm-mcxe247
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@@ -0,0 +1,42 @@
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# Environment setup: https://mongoose.ws/documentation/tutorials/tools/
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CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
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CFLAGS += -Wformat-truncation -fno-common -Wno-conversion -Wno-sign-conversion
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CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
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CFLAGS += -Wno-cast-function-type -Wno-old-style-declaration
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CFLAGS += -Wno-unused-parameter
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CFLAGS += -I. -Imongoose -Icmsis_core/CMSIS/Core/Include/
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CFLAGS += -Icmsis_mcxe247/devices/MCXE247/ -Icmsis_mcxe247/devices/MCXE247/periph0/ -Icmsis_mcxe247/devices/MCXE247/drivers/
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CFLAGS += -DCPU_MCXE247VLQ -DCPU_MCXE247VLQ_cm4
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CFLAGS += -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard $(CFLAGS_EXTRA)
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LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs=nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
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SOURCES = main.c hal.c mongoose/mongoose.c
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SOURCES += cmsis_mcxe247/devices/MCXE247/gcc/startup_MCXE247.S
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SOURCES += cmsis_mcxe247/devices/MCXE247/drivers/fsl_clock.c
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CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS
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all build: firmware.bin
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mongoose/mongoose.c mongoose/mongoose.h:
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mkdir -p mongoose
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cp ../../../../mongoose.[ch] mongoose/
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firmware.bin: firmware.elf
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arm-none-eabi-objcopy -O binary $< $@
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arm-none-eabi-size --format=berkeley $<
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firmware.elf: cmsis_core cmsis_mcxe247 $(SOURCES) $(wildcard *.h) link.ld Makefile
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arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
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cmsis_core:
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git clone -q -c advice.detachedHead=false --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
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cmsis_mcxe247:
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curl -sL https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MCXE247_DFP.26.06.00.pack -o NXP.MCXE247_DFP.26.06.00.pack
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unzip -q NXP.MCXE247_DFP.26.06.00.pack -d $@
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rm NXP.MCXE247_DFP.26.06.00.pack
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clean:
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rm -rf firmware.* cmsis_* mongoose/mongoose.*
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@@ -0,0 +1,125 @@
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// Copyright (c) 2026 Cesanta Software Limited
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// All rights reserved
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#include "hal.h"
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bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now) {
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uint64_t diff = now - *t; // Wrap-safe elapsed time since last expiry
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if (period == 0) return false; // Avoid division by zero
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if (diff < period) return false; // Period has not elapsed yet
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*t += (diff / period) * period; // Preserve cadence, skip missed periods
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return true;
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}
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static volatile uint64_t s_ticks; // Milliseconds since boot
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void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
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s_ticks++;
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}
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uint64_t hal_get_tick(void) {
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return s_ticks;
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};
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uint32_t SystemCoreClock = SYS_FREQUENCY;
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void SystemInit(void) { // Called automatically by startup code
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hal_system_init(); // Enable FPU
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hal_clock_init();
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SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
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}
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void ExitRun0Mode(void) {
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}
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struct stat;
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__attribute__((weak)) int _fstat(int fd, struct stat *st) {
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(void) fd, (void) st;
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return -1;
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}
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extern unsigned char _end[]; // End of data section, start of heap. See link.ld
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static unsigned char *s_current_heap_end = _end;
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size_t hal_ram_used(void) {
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return (size_t) (s_current_heap_end - _end);
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}
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size_t hal_ram_free(void) {
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unsigned char endofstack;
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return (size_t) (&endofstack - s_current_heap_end);
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}
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void *_sbrk(int incr) {
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unsigned char *prev_heap;
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unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
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prev_heap = s_current_heap_end;
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// Check how much space we got from the heap end to the stack end
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if (s_current_heap_end + incr > heap_end) return (void *) -1;
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s_current_heap_end += incr;
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return prev_heap;
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}
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__attribute__((weak)) int _open(const char *path) {
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(void) path;
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return -1;
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}
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__attribute__((weak)) int _close(int fd) {
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(void) fd;
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return -1;
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}
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__attribute__((weak)) int _isatty(int fd) {
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(void) fd;
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return 1;
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}
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__attribute__((weak)) int _lseek(int fd, int ptr, int dir) {
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(void) fd, (void) ptr, (void) dir;
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return 0;
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}
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__attribute__((weak)) void _exit(int status) {
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(void) status;
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for (;;) asm volatile("BKPT #0");
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}
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__attribute__((weak)) void _kill(int pid, int sig) {
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(void) pid, (void) sig;
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}
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__attribute__((weak)) int _getpid(void) {
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return -1;
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}
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__attribute__((weak)) int _write(int fd, char *ptr, int len) {
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(void) fd, (void) ptr, (void) len;
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return -1;
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}
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__attribute__((weak)) int _read(int fd, char *ptr, int len) {
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(void) fd, (void) ptr, (void) len;
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return -1;
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}
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__attribute__((weak)) int _link(const char *a, const char *b) {
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(void) a, (void) b;
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return -1;
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}
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__attribute__((weak)) int _unlink(const char *a) {
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(void) a;
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return -1;
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}
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__attribute__((weak)) int _stat(const char *path, struct stat *st) {
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(void) path, (void) st;
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return -1;
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}
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__attribute__((weak)) int mkdir(const char *path, int mode) {
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(void) path, (void) mode;
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return -1;
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}
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__attribute__((weak)) void _init(void) {
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}
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@@ -0,0 +1,289 @@
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// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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// MCXE24x Series Reference Manual (MCXE24XRM)
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// FRDM-MCXE247 Board User Manual: UM12286
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include "MCXE247.h"
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#include <fsl_clock.h>
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#define BIT(x) (1UL << (x))
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#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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void hal_init(void);
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size_t hal_ram_free(void);
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size_t hal_ram_used(void);
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bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now);
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uint64_t hal_get_tick(void);
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static inline void spin(volatile uint32_t count) {
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while (count--)
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(void)0;
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}
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#define SYS_FREQUENCY 80000000UL
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enum { HAL_GPIO_MODE_INPUT, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_MODE_AF };
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enum { HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_OTYPE_OPEN_DRAIN };
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enum { HAL_GPIO_SPEED_LOW, HAL_GPIO_SPEED_HIGH };
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enum { HAL_GPIO_PULL_NONE, HAL_GPIO_PULL_DOWN, HAL_GPIO_PULL_UP };
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static inline GPIO_Type *hal_gpio_bank(uint16_t pin) {
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static GPIO_Type *const g[] = GPIO_BASE_PTRS;
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return g[PINBANK(pin)];
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}
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static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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static PORT_Type *const p[] = PORT_BASE_PTRS;
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PORT_Type *port = p[PINBANK(pin)];
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GPIO_Type *gpio = hal_gpio_bank(pin);
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uint32_t mask = (uint32_t)BIT(PINNO(pin));
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bool dopull = pull > 0;
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if (gpio == GPIOA) {
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CLOCK_EnableClock(kCLOCK_PortA);
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} else if (gpio == GPIOB) {
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CLOCK_EnableClock(kCLOCK_PortB);
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} else if (gpio == GPIOC) {
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CLOCK_EnableClock(kCLOCK_PortC);
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} else if (gpio == GPIOD) {
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CLOCK_EnableClock(kCLOCK_PortD);
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} else if (gpio == GPIOE) {
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CLOCK_EnableClock(kCLOCK_PortE);
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}
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if (dopull)
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--pull;
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port->PCR[PINNO(pin)] = PORT_PCR_MUX(af) | PORT_PCR_DSE(1) |
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PORT_PCR_PE(dopull) | PORT_PCR_PS(pull);
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if (mode == HAL_GPIO_MODE_INPUT) {
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gpio->PDDR &= ~mask;
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} else if (mode == HAL_GPIO_MODE_OUTPUT) {
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gpio->PDDR |= mask;
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}
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(void) type, (void) speed;
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}
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static inline void hal_gpio_input(uint16_t pin) {
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hal_gpio_init(pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_LOW,
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HAL_GPIO_PULL_NONE, 1);
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}
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static inline void hal_gpio_output(uint16_t pin) {
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hal_gpio_init(pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_LOW,
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HAL_GPIO_PULL_NONE, 1);
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}
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static inline bool hal_gpio_read(uint16_t pin) {
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GPIO_Type *gpio = hal_gpio_bank(pin);
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return gpio->PDIR & PINNO(pin);
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}
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static inline void hal_gpio_write(uint16_t pin, bool value) {
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GPIO_Type *gpio = hal_gpio_bank(pin);
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if (value) {
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gpio->PDOR |= (1 << PINNO(pin));
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} else {
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gpio->PDOR &= ~(1 << PINNO(pin));
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}
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}
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static inline void hal_gpio_toggle(uint16_t pin) {
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GPIO_Type *gpio = hal_gpio_bank(pin);
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uint32_t mask = (uint32_t)BIT(PINNO(pin));
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gpio->PTOR = mask;
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}
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static inline void hal_uart_init(LPUART_Type *uart, unsigned long baud) {
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uint8_t af = 3; // Alternate function
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uint16_t pr = 0, pt = 0; // pins
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uint32_t freq = 8000000; // 8MHz (System Oscillator clock)
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uint32_t lpuart_clk;
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if (uart == LPUART2)
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lpuart_clk = kCLOCK_Lpuart2, pt = PIN('E', 12), pr = PIN('D', 17);
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if (uart == LPUART1)
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lpuart_clk = kCLOCK_Lpuart1, pt = PIN('C', 9), pr = PIN('C', 8);
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CLOCK_SetIpSrc(lpuart_clk, kCLOCK_IpSrcSysOscAsync);
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hal_gpio_init(pt, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_LOW,
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HAL_GPIO_PULL_UP, af);
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hal_gpio_init(pr, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_LOW,
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HAL_GPIO_PULL_UP, af);
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CLOCK_EnableClock(lpuart_clk);
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uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults
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uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
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// use an oversample ratio of 23
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CLRSET(uart->BAUD,
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LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK,
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LPUART_BAUD_OSR(23 - 1) | LPUART_BAUD_SBR(freq / (23 * baud)));
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CLRSET(uart->CTRL,
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LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
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LPUART_CTRL_IDLECFG_MASK,
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LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) |
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LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit
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uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
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}
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static inline void hal_uart_write_byte(LPUART_Type *uart, uint8_t byte) {
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uart->DATA = byte;
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while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0)
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spin(1);
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}
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static inline void hal_uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
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while (len-- > 0)
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hal_uart_write_byte(uart, *(uint8_t *)buf++);
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}
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static inline void hal_ethernet_init(void) {
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// enable peripheral clock
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uint32_t reg = (*(volatile uint32_t *)(uint32_t)kCLOCK_Enet);
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reg = (reg & ~(PCC_CLKCFG_PCS_MASK | PCC_CLKCFG_FRAC_MASK | PCC_CLKCFG_PCD_MASK)) | PCC_CLKCFG_PCS(6) |
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PCC_CLKCFG_PCD(1) | PCC_CLKCFG_FRAC(1);
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(*(volatile uint32_t *)(uint32_t)kCLOCK_Enet) = reg & ~PCC_CLKCFG_CGC_MASK;
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(*(volatile uint32_t *)(uint32_t)kCLOCK_Enet) = reg;
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CLOCK_EnableClock(kCLOCK_Enet);
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// init pins
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hal_gpio_init(PIN('C', 3), HAL_GPIO_MODE_OUTPUT, 0, 0, HAL_GPIO_PULL_NONE, 1); // PHY_RST
|
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hal_gpio_write(PIN('C', 3), 1);
|
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hal_gpio_init(PIN('B', 4), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_MDIO
|
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hal_gpio_init(PIN('C', 0), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 4); // MII_RMII_RXD1
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hal_gpio_init(PIN('C', 1), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_RXD0
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hal_gpio_init(PIN('C', 17), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_RX_DV
|
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hal_gpio_init(PIN('C', 2), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_TXD0
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hal_gpio_init(PIN('D', 11), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_TX_CLK
|
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hal_gpio_init(PIN('D', 12), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_TX_EN
|
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hal_gpio_init(PIN('D', 7), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_TXD1
|
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hal_gpio_init(PIN('E', 8), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_MDC
|
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|
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// reset PHY
|
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hal_gpio_write(PIN('C', 3), 0);
|
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spin(50000);
|
||||
hal_gpio_write(PIN('C', 3), 1);
|
||||
|
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NVIC_EnableIRQ(ENET_Receive_IRQn);
|
||||
}
|
||||
|
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static inline void hal_rtc_init(void) {
|
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// Configure RTC clock to generate seeds
|
||||
// Reconfigure it there as needed.
|
||||
SIM->LPOCLKS = 0x13; // LPO32K_CLK, LPO32KCLKEN, LPO1KCLKEN
|
||||
CLOCK_EnableClock(kCLOCK_Rtc0);
|
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// If Time Invalid Flag set, reset the RTC
|
||||
if (RTC->SR & RTC_SR_TIF_MASK) {
|
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RTC->CR |= RTC_CR_SWR_MASK;
|
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RTC->CR &= ~RTC_CR_SWR_MASK;
|
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}
|
||||
RTC->IER &= ~(RTC_IER_TSIC_MASK | RTC_IER_TSIE_MASK);
|
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RTC->SR |= RTC_SR_TCE_MASK; // Enable timer
|
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}
|
||||
|
||||
static inline void hal_clock_init(void) {
|
||||
// init SysOsc
|
||||
SCG->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
|
||||
SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1);
|
||||
SCG->SOSCCFG = BIT(2) | SCG_SOSCCFG_RANGE(2); // work mode, range
|
||||
SCG->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
|
||||
while ((SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0) spin(1);
|
||||
|
||||
// init FIRC
|
||||
SCG->SIRCCSR = 0U;
|
||||
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(0) | SCG_SIRCDIV_SIRCDIV2(2);
|
||||
SCG->SIRCCFG = SCG_SIRCCFG_RANGE(1);
|
||||
SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | BIT(0);
|
||||
while ((SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0) spin(1);
|
||||
// Change to use SIRC as system clock source
|
||||
SCG->RCCR = SCG_RCCR_DIVSLOW(3) | SCG_RCCR_SCS(2);
|
||||
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) != 2) spin(1);
|
||||
SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(1) | SCG_FIRCDIV_FIRCDIV2(1);
|
||||
SCG->FIRCCFG = SCG_FIRCCFG_RANGE(0);
|
||||
SCG->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK;
|
||||
while ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0) spin(1);
|
||||
SCG->RCCR = SCG_RCCR_DIVSLOW(3) | SCG_RCCR_SCS(3); // Change to FIRC
|
||||
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) != 3) spin(1);
|
||||
|
||||
// init SIRC
|
||||
SCG->SIRCCSR = 0U;
|
||||
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(2);
|
||||
SCG->SIRCCFG = SCG_SIRCCFG_RANGE(1);
|
||||
SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | BIT(2);
|
||||
while ((SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0) spin(1);
|
||||
|
||||
// init SysPLL
|
||||
SCG->SPLLCSR = SCG_SPLLCSR_SPLLERR_MASK;
|
||||
SCG->SPLLDIV = SCG_SPLLDIV_SPLLDIV1(2) | SCG_SPLLDIV_SPLLDIV2(0);
|
||||
SCG->SPLLCFG = SCG_SPLLCFG_PREDIV(0) | SCG_SPLLCFG_MULT(24);
|
||||
SCG->SPLLCSR = (uint32_t)SCG_SPLLCSR_SPLLEN_MASK ;
|
||||
while ((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) == 0) spin(1);
|
||||
|
||||
// Set SCG to SPLL mode
|
||||
SCG->RCCR = SCG_RCCR_DIVSLOW(4) | SCG_RCCR_DIVBUS(1) | SCG_RCCR_DIVCORE(1) | SCG_RCCR_SCS(6);
|
||||
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) != 6) spin(1);
|
||||
// Set SCG CLKOUT selection.
|
||||
SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(3);
|
||||
}
|
||||
|
||||
// TRNG is part of ELS, which requires flash partitioning to work
|
||||
// Use our PRNG when the OS does not provide an alternative
|
||||
#define MG_HAL_ENABLE_PRNG 1
|
||||
static inline uint32_t hal_entropy_init(void) {
|
||||
hal_rtc_init(); // Initialize RTC
|
||||
spin(100000);
|
||||
uint32_t seed = RTC->TPR; // get seed
|
||||
spin(100000);
|
||||
seed |= (RTC->TPR << 16);
|
||||
return seed;
|
||||
}
|
||||
|
||||
static inline bool hal_entropy_get(uint32_t *ent) {
|
||||
*ent = RTC->TPR;
|
||||
return true;
|
||||
}
|
||||
|
||||
#if defined(__MCUXPRESSO)
|
||||
#undef MG_HAL_DISABLE_SYSTEM_INIT
|
||||
#define MG_HAL_DISABLE_SYSTEM_INIT 1
|
||||
#undef MG_HAL_SBRK_NONE
|
||||
#define MG_HAL_SBRK_NONE 1
|
||||
#endif
|
||||
|
||||
static inline void hal_system_init(void) {
|
||||
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
|
||||
SCB->CPACR |= (3 << 20) | (3 << 22); // Enable FPU access
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
// Disable watchdog
|
||||
if ((WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0) {
|
||||
WDOG->CNT = WDOG_UPDATE_KEY;
|
||||
} else {
|
||||
WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU;
|
||||
WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU;
|
||||
}
|
||||
WDOG->TOVAL = 0xFFFFU;
|
||||
WDOG->CS = (uint32_t) ((WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
|
||||
|
||||
LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
|
||||
LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;
|
||||
// Wait until the command completes
|
||||
while (LMEM->PCCCR & LMEM_PCCCR_GO_MASK) spin(1);
|
||||
// Enable cache
|
||||
LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
|
||||
__ISB();
|
||||
|
||||
// Errata ERR050877 workaround. Enable FZ mode in the FPSCR
|
||||
__set_FPSCR(__get_FPSCR() | FPSCR_FZ_MASK);
|
||||
|
||||
SYSMPU->CESR &= ~SYSMPU_CESR_VLD(1); // disable MPU
|
||||
}
|
||||
@@ -0,0 +1,35 @@
|
||||
OUTPUT_FORMAT("elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash(RX) : ORIGIN = 0x0, LENGTH = 0x180000
|
||||
flash2(RX) : ORIGIN = 0x10000000, LENGTH = 0x80000
|
||||
sram(RWX) : ORIGIN = 0x1ffe0000, LENGTH = 0x3f000
|
||||
}
|
||||
|
||||
__StackTop = ORIGIN(sram) + LENGTH(sram);
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.vectors : { FILL(256) KEEP(*(.isr_vector)) } > flash
|
||||
. = 0x400 ;
|
||||
.FlashConfig : { KEEP(*(.FlashConfig)) } > flash
|
||||
.text : { *(.text.* *.text.*) } > flash
|
||||
.rodata : { *(.rodata*) } > flash
|
||||
|
||||
.data : {
|
||||
__data_start__ = .;
|
||||
*(.first_data)
|
||||
*(.data SORT(.data.*))
|
||||
__data_end__ = .;
|
||||
} > sram AT > flash
|
||||
__etext = LOADADDR(.data);
|
||||
|
||||
.bss : { __bss_start__ = .; *(.bss SORT(.bss.*) COMMON) __bss_end__ = .; } > sram
|
||||
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
|
||||
}
|
||||
@@ -0,0 +1,101 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "mongoose.h"
|
||||
#include "hal.h"
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG LPUART2
|
||||
#endif
|
||||
|
||||
#define LED1 PIN('C', 13) // Red
|
||||
#define LED2 PIN('B', 11) // Green
|
||||
#define LED3 PIN('C', 12) // Blue
|
||||
|
||||
static uint32_t s_rng_seed;
|
||||
|
||||
static void hal_rng_init(void) {
|
||||
s_rng_seed = hal_entropy_init();
|
||||
}
|
||||
|
||||
static uint32_t hal_rng_read(void) {
|
||||
uint32_t seed = s_rng_seed, entropy;
|
||||
if (hal_entropy_get(&entropy)) {
|
||||
entropy *= 0x85ebca6b;
|
||||
entropy ^= entropy << 16;
|
||||
entropy ^= entropy >> 5;
|
||||
seed ^= entropy;
|
||||
seed *= 0x5bd1e995;
|
||||
seed ^= seed << 13;
|
||||
seed ^= seed >> 17;
|
||||
seed ^= seed << 5;
|
||||
seed += entropy;
|
||||
seed ^= seed >> 16;
|
||||
}
|
||||
s_rng_seed = seed;
|
||||
return seed;
|
||||
}
|
||||
|
||||
static void log_fn(char ch, void *param) {
|
||||
hal_uart_write_buf(param, &ch, 1);
|
||||
}
|
||||
|
||||
static void blink_task(void) {
|
||||
static uint64_t blink_timer = 0;
|
||||
if (hal_timer_expired(&blink_timer, 500, hal_get_tick())) {
|
||||
hal_gpio_toggle(LED1);
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t mg_millis(void) {
|
||||
return hal_get_tick();
|
||||
}
|
||||
|
||||
#if MG_ENABLE_CUSTOM_RANDOM
|
||||
bool mg_random(void *buf, size_t len) {
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = hal_rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) {
|
||||
if (ev == MG_EV_HTTP_MSG) { // New HTTP request received
|
||||
struct mg_http_message *hm = (struct mg_http_message *) ev_data;
|
||||
if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) {
|
||||
mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), hal_get_tick());
|
||||
} else {
|
||||
mg_http_reply(c, 200, "", "Hi from Mongoose, tick %llu\n",
|
||||
hal_get_tick());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
hal_clock_init();
|
||||
hal_rng_init();
|
||||
hal_gpio_output(LED1);
|
||||
hal_gpio_write(LED1, true);
|
||||
hal_gpio_output(LED2);
|
||||
hal_gpio_write(LED2, true);
|
||||
hal_gpio_output(LED3);
|
||||
hal_gpio_write(LED3, true);
|
||||
hal_uart_init(UART_DEBUG, 115200);
|
||||
mg_log_set_fn(log_fn, UART_DEBUG);
|
||||
|
||||
hal_ethernet_init();
|
||||
|
||||
// Start a minimal web server
|
||||
struct mg_mgr mgr;
|
||||
mg_mgr_init(&mgr);
|
||||
mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL);
|
||||
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
blink_task();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,36 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_ARMGCC
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_DRIVER_MCXE 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
|
||||
#define MG_DRIVER_MDC_CR 15 // RMII MDC clock divider, from 0 to 7
|
||||
#define MG_TCPIP_PHY_ADDR 0 // PHY address
|
||||
|
||||
// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
|
||||
// By default, those are set to zero, meaning that DHCP is used
|
||||
//
|
||||
//#define MG_TCPIP_IP MG_IPV4(192, 168, 1, 10)
|
||||
//#define MG_TCPIP_GW MG_IPV4(192, 168, 1, 1)
|
||||
//#define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0)
|
||||
|
||||
// Set custom MAC address. By default, it is randomly generated
|
||||
// Use the unique ID of the board
|
||||
#define MGUID ((uint32_t*)0x40048054UL)
|
||||
#define MG_SET_MAC_ADDRESS(mac) \
|
||||
do { \
|
||||
mac[0] = 2; \
|
||||
mac[1] = MGUID[0] & 255; \
|
||||
mac[2] = (MGUID[0] >> 10) & 255; \
|
||||
mac[3] = (MGUID[0] >> 19) & 255; \
|
||||
mac[4] = MGUID[1] & 255; \
|
||||
mac[5] = MGUID[2] & 255; \
|
||||
} while (0)
|
||||
//
|
||||
// Using custom function:
|
||||
// extern void my_function(unsigned char *mac);
|
||||
// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)
|
||||
Reference in new issue
Block a user