mirror of
https://github.com/cesanta/mongoose.git
synced 2026-11-09 16:21:45 +00:00
Reorganized NXP examples
This commit is contained in:
robert committed
1 parent
aae31aba9c
commit
201a81a315
1955 files changed
+5705
-1344015
No files matched your search
@@ -0,0 +1 @@
|
||||
See the example at https://github.com/mongoose-examples/frdm-rw612
|
||||
@@ -0,0 +1,42 @@
|
||||
# Environment setup: https://mongoose.ws/documentation/tutorials/tools/
|
||||
|
||||
CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
|
||||
CFLAGS += -Wformat-truncation -fno-common -Wno-conversion -Wno-sign-conversion
|
||||
CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
|
||||
CFLAGS += -Wno-cast-function-type -Wno-old-style-declaration
|
||||
CFLAGS += -Wno-unused-parameter
|
||||
CFLAGS += -I. -Imongoose -Icmsis_core/CMSIS/Core/Include/
|
||||
CFLAGS += -Icmsis_rw612/devices/RW612/ -Icmsis_rw612/devices/RW612/periph/ -Icmsis_rw612/devices/RW612/drivers/
|
||||
CFLAGS += -DCPU_RW612ETA2I -DCPU_RW612ETA2I_cm33_no_dsp
|
||||
CFLAGS += -DBOOT_HEADER_ENABLE=1
|
||||
CFLAGS += -mcpu=cortex-m33+nodsp -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 $(CFLAGS_EXTRA)
|
||||
LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs=nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
|
||||
|
||||
SOURCES = main.c hal.c startup.c flexspi.c flash_config.c mongoose/mongoose.c
|
||||
SOURCES += cmsis_rw612/devices/RW612/drivers/fsl_clock.c
|
||||
SOURCES += cmsis_rw612/devices/RW612/drivers/fsl_trng.c
|
||||
SOURCES += cmsis_rw612/devices/RW612/drivers/fsl_reset.c
|
||||
|
||||
all build: firmware.bin
|
||||
|
||||
mongoose/mongoose.c mongoose/mongoose.h:
|
||||
mkdir -p mongoose
|
||||
cp ../../../../mongoose.[ch] mongoose/
|
||||
|
||||
firmware.bin: firmware.elf
|
||||
arm-none-eabi-objcopy -O binary $< $@
|
||||
arm-none-eabi-size --format=berkeley $<
|
||||
|
||||
firmware.elf: cmsis_core cmsis_rw612 $(SOURCES) $(wildcard *.h) link.ld Makefile
|
||||
arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
|
||||
|
||||
cmsis_core:
|
||||
git clone -q -c advice.detachedHead=false --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
|
||||
|
||||
cmsis_rw612:
|
||||
curl -sL https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.RW612_DFP.25.12.00.pack -o NXP.RW612_DFP.25.12.00.pack
|
||||
unzip -q NXP.RW612_DFP.25.12.00.pack -d $@
|
||||
rm NXP.RW612_DFP.25.12.00.pack
|
||||
|
||||
clean:
|
||||
rm -rf firmware.* cmsis_* mongoose/mongoose.*
|
||||
@@ -0,0 +1,86 @@
|
||||
/*
|
||||
* Copyright 2021-2024 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#include "flash_config.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.flash_config"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(BOOT_HEADER_ENABLE) && (BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".flash_conf"), used))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".flash_conf"
|
||||
#endif
|
||||
const fc_flexspi_nor_config_t flexspi_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FC_BLOCK_TAG,
|
||||
.version = FC_BLOCK_VERSION,
|
||||
.readSampleClkSrc = 1,
|
||||
.csHoldTime = 3,
|
||||
.csSetupTime = 3,
|
||||
.deviceModeCfgEnable = 1,
|
||||
.deviceModeSeq = {.seqNum = 1, .seqId = 2},
|
||||
.deviceModeArg = 0x02,
|
||||
.configCmdEnable = 0,
|
||||
.deviceType = 0x1,
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = 5,
|
||||
.sflashA1Size = 0x4000000U,
|
||||
.sflashA2Size = 0,
|
||||
.sflashB1Size = 0,
|
||||
.sflashB2Size = 0,
|
||||
.lookupTable =
|
||||
{
|
||||
/* Read */
|
||||
[0] = FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0xEC, FC_RADDR_SDR, FC_FLEXSPI_4PAD, 0x20),
|
||||
[1] = FC_FLEXSPI_LUT_SEQ(FC_MODE8_SDR, FC_FLEXSPI_4PAD, 0xF0, FC_DUMMY_SDR, FC_FLEXSPI_4PAD, 0x04),
|
||||
[2] = FC_FLEXSPI_LUT_SEQ(FC_READ_SDR, FC_FLEXSPI_4PAD, 0x04, FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
|
||||
|
||||
/* Read Status */
|
||||
[4 * 1 + 0] =
|
||||
FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x05, FC_READ_SDR, FC_FLEXSPI_1PAD, 0x04),
|
||||
|
||||
/* Write Status */
|
||||
[4 * 2 + 0] =
|
||||
FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x31, FC_WRITE_SDR, FC_FLEXSPI_1PAD, 0x01),
|
||||
|
||||
/* Write Enable */
|
||||
[4 * 3 + 0] =
|
||||
FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x06, FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
|
||||
|
||||
/* Sector erase */
|
||||
[4 * 5 + 0] =
|
||||
FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x21, FC_RADDR_SDR, FC_FLEXSPI_1PAD, 0x20),
|
||||
|
||||
/* Block erase */
|
||||
[4 * 8 + 0] =
|
||||
FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0xDC, FC_RADDR_SDR, FC_FLEXSPI_1PAD, 0x20),
|
||||
|
||||
/* Page program */
|
||||
[4 * 9 + 0] =
|
||||
FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0x34, FC_RADDR_SDR, FC_FLEXSPI_1PAD, 0x20),
|
||||
[4 * 9 + 1] =
|
||||
FC_FLEXSPI_LUT_SEQ(FC_WRITE_SDR, FC_FLEXSPI_4PAD, 0x00, FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
|
||||
|
||||
/* chip erase */
|
||||
[4 * 11 + 0] =
|
||||
FC_FLEXSPI_LUT_SEQ(FC_CMD_SDR, FC_FLEXSPI_1PAD, 0xC7, FC_STOP_EXE, FC_FLEXSPI_1PAD, 0x00),
|
||||
},
|
||||
},
|
||||
.pageSize = 0x100,
|
||||
.sectorSize = 0x1000,
|
||||
.ipcmdSerialClkFreq = 0,
|
||||
.blockSize = 0x10000,
|
||||
.fcb_fill[0] = 0xFFFFFFFF,
|
||||
};
|
||||
#endif /* BOOT_HEADER_ENABLE */
|
||||
@@ -0,0 +1,221 @@
|
||||
/*
|
||||
* Copyright 2021-2023 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __FLASH_CONFIG__
|
||||
#define __FLASH_CONFIG__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief FLASH_CONFIG driver version 2.0.0. */
|
||||
#define FSL_FLASH_CONFIG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definition
|
||||
******************************************************************************/
|
||||
|
||||
/* FLEXSPI memory config block related defintions */
|
||||
#define FC_BLOCK_TAG (0x42464346)
|
||||
#define FC_BLOCK_VERSION (0x00000000)
|
||||
|
||||
#define FC_CMD_SDR 0x01
|
||||
#define FC_CMD_DDR 0x21
|
||||
#define FC_RADDR_SDR 0x02
|
||||
#define FC_RADDR_DDR 0x22
|
||||
#define FC_CADDR_SDR 0x03
|
||||
#define FC_CADDR_DDR 0x23
|
||||
#define FC_MODE1_SDR 0x04
|
||||
#define FC_MODE1_DDR 0x24
|
||||
#define FC_MODE2_SDR 0x05
|
||||
#define FC_MODE2_DDR 0x25
|
||||
#define FC_MODE4_SDR 0x06
|
||||
#define FC_MODE4_DDR 0x26
|
||||
#define FC_MODE8_SDR 0x07
|
||||
#define FC_MODE8_DDR 0x27
|
||||
#define FC_WRITE_SDR 0x08
|
||||
#define FC_WRITE_DDR 0x28
|
||||
#define FC_READ_SDR 0x09
|
||||
#define FC_READ_DDR 0x29
|
||||
#define FC_LEARN_SDR 0x0A
|
||||
#define FC_LEARN_DDR 0x2A
|
||||
#define FC_DATSZ_SDR 0x0B
|
||||
#define FC_DATSZ_DDR 0x2B
|
||||
#define FC_DUMMY_SDR 0x0C
|
||||
#define FC_DUMMY_DDR 0x2C
|
||||
#define FC_DUMMY_RWDS_SDR 0x0D
|
||||
#define FC_DUMMY_RWDS_DDR 0x2D
|
||||
#define FC_JMP_ON_CS 0x1F
|
||||
#define FC_STOP_EXE 0
|
||||
|
||||
#define FC_FLEXSPI_1PAD 0
|
||||
#define FC_FLEXSPI_2PAD 1
|
||||
#define FC_FLEXSPI_4PAD 2
|
||||
#define FC_FLEXSPI_8PAD 3
|
||||
|
||||
#define FC_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
/* !@brief Data pad used in Read command */
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pads = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
/* !@brief FLEXSPI clock configuration - In High speed boot mode mode */
|
||||
enum
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_80MHz = 4,
|
||||
kFlexSpiSerialClk_100MHz = 5,
|
||||
kFlexSpiSerialClk_120MHz = 6,
|
||||
kFlexSpiSerialClk_133MHz = 7,
|
||||
kFlexSpiSerialClk_166MHz = 8,
|
||||
kFlexSpiSerialClk_200MHz = 9,
|
||||
};
|
||||
|
||||
/* !@brief FLEXSPI clock configuration - In Normal boot SDR mode */
|
||||
enum
|
||||
{
|
||||
kFlexSpiSerialClk_SDR_24MHz = 1,
|
||||
kFlexSpiSerialClk_SDR_48MHz = 2,
|
||||
};
|
||||
|
||||
/* !@brief FLEXSPI clock configuration - In Normal boot DDR mode */
|
||||
enum
|
||||
{
|
||||
kFlexSpiSerialClk_DDR_48MHz = 1,
|
||||
};
|
||||
|
||||
/* !@brief Misc feature bit definitions */
|
||||
enum
|
||||
{
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, /* !< Bit for Differential clock enable */
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, /* !< Bit for Word Addressable enable */
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, /* !< Bit for Safe Configuration Frequency enable */
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, /* !< Bit for DDR clock confiuration indication. */
|
||||
};
|
||||
|
||||
/* !@brief Flash Configuration Command Type */
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, /* !< Generic command, for example: configure dummy cycles, drive strength, etc */
|
||||
kDeviceConfigCmdType_QuadEnable, /* !< Quad Enable command */
|
||||
kDeviceConfigCmdType_Spi2Xpi, /* !< Switch from SPI to DPI/QPI/OPI mode */
|
||||
kDeviceConfigCmdType_Xpi2Spi, /* !< Switch from DPI/QPI/OPI to SPI mode */
|
||||
kDeviceConfigCmdType_Spi2NoCmd, /* !< Switch to 0-4-4/0-8-8 mode */
|
||||
kDeviceConfigCmdType_Reset, /* !< Reset device command */
|
||||
};
|
||||
|
||||
typedef struct _fc_flexspi_dll_time
|
||||
{
|
||||
uint8_t time_100ps; /* !< Data valid time, in terms of 100ps */
|
||||
uint8_t delay_cells; /* !< Data valid time, in terms of delay cells */
|
||||
} fc_flexspi_dll_time_t;
|
||||
|
||||
/* !@brief FlexSPI LUT Sequence structure */
|
||||
typedef struct _fc_flexspi_lut_seq
|
||||
{
|
||||
uint8_t seqNum; /* !< Sequence Number, valid number: 1-16 */
|
||||
uint8_t seqId; /* !< Sequence Index, valid number: 0-15 */
|
||||
uint16_t reserved;
|
||||
} fc_flexspi_lut_seq_t;
|
||||
|
||||
/* !@brief FlexSPI Memory Configuration Block */
|
||||
typedef struct _fc_flexspi_mem_config
|
||||
{
|
||||
uint32_t tag; /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */
|
||||
uint32_t version; /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
|
||||
uint32_t reserved0; /* !< [0x008-0x00b] Reserved for future use */
|
||||
uint8_t readSampleClkSrc; /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
|
||||
uint8_t csHoldTime; /* !< [0x00d-0x00d] CS hold time, default value: 3 */
|
||||
uint8_t csSetupTime; /* !< [0x00e-0x00e] CS setup time, default value: 3 */
|
||||
uint8_t columnAddressWidth; /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
Serial NAND, need to refer to datasheet */
|
||||
uint8_t deviceModeCfgEnable; /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
|
||||
uint8_t deviceModeType; /* !< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
Generic configuration, etc. */
|
||||
uint16_t waitTimeCfgCommands; /* !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
DPI/QPI/OPI switch or reset command */
|
||||
fc_flexspi_lut_seq_t deviceModeSeq; /* !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] -
|
||||
LUt sequence number, [31:16] Reserved */
|
||||
uint32_t deviceModeArg; /* !< [0x018-0x01b] Argument/Parameter for device configuration */
|
||||
uint8_t configCmdEnable; /* !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */
|
||||
uint8_t configModeType[3]; /* !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */
|
||||
fc_flexspi_lut_seq_t configCmdSeqs[3]; /* !< [0x020-0x02b] Sequence info for Device Configuration command, similar
|
||||
as deviceModeSeq */
|
||||
uint32_t reserved1; /* !< [0x02c-0x02f] Reserved for future use */
|
||||
uint32_t configCmdArgs[3]; /* !< [0x030-0x03b] Arguments/Parameters for device Configuration commands */
|
||||
uint32_t reserved2; /* !< [0x03c-0x03f] Reserved for future use */
|
||||
uint32_t controllerMiscOption; /* !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for
|
||||
more details */
|
||||
uint8_t deviceType; /* !< [0x044-0x044] Device Type: See Flash Type Definition for more details */
|
||||
uint8_t sflashPadType; /* !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */
|
||||
uint8_t serialClkFreq; /* !< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
|
||||
Chapter for more details */
|
||||
uint8_t lutCustomSeqEnable; /* !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
be done using 1 LUT sequence, currently, only applicable to HyperFLASH */
|
||||
uint32_t reserved3[2]; /* !< [0x048-0x04f] Reserved for future use */
|
||||
uint32_t sflashA1Size; /* !< [0x050-0x053] Size of Flash connected to A1 */
|
||||
uint32_t sflashA2Size; /* !< [0x054-0x057] Size of Flash connected to A2 */
|
||||
uint32_t sflashB1Size; /* !< [0x058-0x05b] Size of Flash connected to B1 */
|
||||
uint32_t sflashB2Size; /* !< [0x05c-0x05f] Size of Flash connected to B2 */
|
||||
uint32_t csPadSettingOverride; /* !< [0x060-0x063] CS pad setting override value */
|
||||
uint32_t sclkPadSettingOverride; /* !< [0x064-0x067] SCK pad setting override value */
|
||||
uint32_t dataPadSettingOverride; /* !< [0x068-0x06b] data pad setting override value */
|
||||
uint32_t dqsPadSettingOverride; /* !< [0x06c-0x06f] DQS pad setting override value */
|
||||
uint32_t timeoutInMs; /* !< [0x070-0x073] Timeout threshold for read status command */
|
||||
uint32_t commandInterval; /* !< [0x074-0x077] CS deselect interval between two commands */
|
||||
fc_flexspi_dll_time_t dataValidTime[2]; /* !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */
|
||||
uint16_t busyOffset; /* !< [0x07c-0x07d] Busy offset, valid value: 0-31 */
|
||||
uint16_t busyBitPolarity; /* !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
busy flag is 0 when flash device is busy */
|
||||
uint32_t lookupTable[64]; /* !< [0x080-0x17f] Lookup table holds Flash command sequences */
|
||||
fc_flexspi_lut_seq_t lutCustomSeq[12]; /* !< [0x180-0x1af] Customizable LUT Sequences */
|
||||
uint32_t reserved4[4]; /* !< [0x1b0-0x1bf] Reserved for future use */
|
||||
} fc_flexspi_mem_config_t;
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _fc_flexspi_nor_config
|
||||
{
|
||||
#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
|
||||
uint8_t padding[0x400]; /* !< Padding for MDK and IAR */
|
||||
#endif
|
||||
fc_flexspi_mem_config_t memConfig; /* !< Common memory configuration info via FlexSPI */
|
||||
uint32_t pageSize; /* !< Page size of Serial NOR */
|
||||
uint32_t sectorSize; /* !< Sector size of Serial NOR */
|
||||
uint8_t ipcmdSerialClkFreq; /* !< Clock frequency for IP command */
|
||||
uint8_t isUniformBlockSize; /* !< Sector/Block size is the same */
|
||||
uint8_t isDataOrderSwapped; /* !< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */
|
||||
uint8_t reserved0[1]; /* !< Reserved for future use */
|
||||
uint8_t serialNorType; /* !< Serial NOR Flash type: 0/1/2/3 */
|
||||
uint8_t needExitNoCmdMode; /* !< Need to exit NoCmd mode before other IP command */
|
||||
uint8_t halfClkForNonReadCmd; /* !< Half the Serial Clock for non-read command: true/false */
|
||||
uint8_t needRestoreNoCmdMode; /* !< Need to Restore NoCmd mode after IP commmand execution */
|
||||
uint32_t blockSize; /* !< Block size */
|
||||
uint32_t flashStateCtx; /* !< Flash State Context */
|
||||
uint32_t reserve2[10]; /* !< Reserved for future use */
|
||||
uint32_t fcb_fill[0x280]; /* !< Fill */
|
||||
} fc_flexspi_nor_config_t;
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __FLASH_CONFIG__ */
|
||||
@@ -0,0 +1,82 @@
|
||||
#include "RW612.h"
|
||||
#include "fsl_flexspi.h" // peripheral structures
|
||||
|
||||
__attribute__((section(".iram"))) static void deinit_flash(FLEXSPI_Type *base) {
|
||||
CLKCTL0->PSCCTL0_SET =
|
||||
CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK; // Enable FLEXSPI clock again
|
||||
base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; // Enable FLEXSPI module
|
||||
// Wait until FLEXSPI is not busy
|
||||
while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) &&
|
||||
(base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
|
||||
(void)0;
|
||||
base->MCR0 |=
|
||||
FLEXSPI_MCR0_MDIS_MASK; // Disable module during the reset procedure
|
||||
}
|
||||
|
||||
__attribute__((section(".iram"))) static void init_flash(FLEXSPI_Type *base) {
|
||||
uint32_t status;
|
||||
uint32_t lastStatus;
|
||||
uint32_t retry;
|
||||
|
||||
// Loopback from DQS pad can maximize RD board flash speed.
|
||||
if ((base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) != FLEXSPI_MCR0_RXCLKSRC(1)) {
|
||||
base->MCR0 =
|
||||
(base->MCR0 & ~FLEXSPI_MCR0_RXCLKSRC_MASK) | FLEXSPI_MCR0_RXCLKSRC(1);
|
||||
}
|
||||
base->DLLCR[0] = 0x1U;
|
||||
base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; // Enable FLEXSPI module
|
||||
base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
|
||||
while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
|
||||
(void)0;
|
||||
|
||||
// Need to wait DLL locked if DLL enabled
|
||||
if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK)) {
|
||||
lastStatus = base->STS2;
|
||||
retry = 10;
|
||||
// Wait slave delay line locked and slave reference delay line locked.
|
||||
do {
|
||||
status = base->STS2;
|
||||
if ((status &
|
||||
(FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) ==
|
||||
(FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) {
|
||||
// Locked
|
||||
retry = 100;
|
||||
break;
|
||||
} else if (status == lastStatus) {
|
||||
retry--;
|
||||
} else {
|
||||
retry = 10;
|
||||
lastStatus = status;
|
||||
}
|
||||
} while (retry > 0);
|
||||
// According to ERR011377, need to delay at least 100 NOPs to ensure the DLL
|
||||
// is locked
|
||||
for (; retry > 0U; retry--)
|
||||
(void)0;
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((section(".iram"))) void
|
||||
set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider) {
|
||||
if ((CLKCTL0->FLEXSPIFCLKSEL != CLKCTL0_FLEXSPIFCLKSEL_SEL(src)) ||
|
||||
((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) !=
|
||||
(divider - 1))) {
|
||||
// Always deinit FLEXSPI and init FLEXSPI for the flash to make sure the
|
||||
// flash works correctly after the FLEXSPI root clock changed as the default
|
||||
// FLEXSPI configuration may does not work for the new root clock frequency.
|
||||
deinit_flash(base);
|
||||
|
||||
// Disable clock before changing clock source
|
||||
CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_MASK;
|
||||
// Update flexspi clock.
|
||||
CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);
|
||||
CLKCTL0->FLEXSPIFCLKDIV |=
|
||||
CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; // Reset the divider counter
|
||||
CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);
|
||||
while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK)
|
||||
(void)0;
|
||||
// Enable FLEXSPI clock again
|
||||
CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_MASK;
|
||||
init_flash(base);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,125 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now) {
|
||||
uint64_t diff = now - *t; // Wrap-safe elapsed time since last expiry
|
||||
if (period == 0) return false; // Avoid division by zero
|
||||
if (diff < period) return false; // Period has not elapsed yet
|
||||
*t += (diff / period) * period; // Preserve cadence, skip missed periods
|
||||
return true;
|
||||
}
|
||||
|
||||
static volatile uint64_t s_ticks; // Milliseconds since boot
|
||||
void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
|
||||
s_ticks++;
|
||||
}
|
||||
|
||||
uint64_t hal_get_tick(void) {
|
||||
return s_ticks;
|
||||
};
|
||||
|
||||
uint32_t SystemCoreClock = SYS_FREQUENCY;
|
||||
void SystemInit(void) { // Called automatically by startup code
|
||||
hal_system_init(); // Enable FPU
|
||||
hal_clock_init();
|
||||
SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
|
||||
}
|
||||
|
||||
void ExitRun0Mode(void) {
|
||||
}
|
||||
|
||||
struct stat;
|
||||
__attribute__((weak)) int _fstat(int fd, struct stat *st) {
|
||||
(void) fd, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
extern unsigned char _end[]; // End of data section, start of heap. See link.ld
|
||||
static unsigned char *s_current_heap_end = _end;
|
||||
|
||||
size_t hal_ram_used(void) {
|
||||
return (size_t) (s_current_heap_end - _end);
|
||||
}
|
||||
|
||||
size_t hal_ram_free(void) {
|
||||
unsigned char endofstack;
|
||||
return (size_t) (&endofstack - s_current_heap_end);
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
unsigned char *prev_heap;
|
||||
unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
|
||||
prev_heap = s_current_heap_end;
|
||||
// Check how much space we got from the heap end to the stack end
|
||||
if (s_current_heap_end + incr > heap_end) return (void *) -1;
|
||||
s_current_heap_end += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int mkdir(const char *path, int mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _init(void) {
|
||||
}
|
||||
@@ -0,0 +1,357 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "RW612.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "fsl_io_mux.h"
|
||||
#include "fsl_reset.h"
|
||||
#include "fsl_trng.h"
|
||||
|
||||
#define BIT(x) (1UL << (x))
|
||||
#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
|
||||
#define PIN(bank, num) ((bank << 8) | (num))
|
||||
#define PINNO(pin) (pin & 255)
|
||||
#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
void hal_init(void);
|
||||
size_t hal_ram_free(void);
|
||||
size_t hal_ram_used(void);
|
||||
bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now);
|
||||
uint64_t hal_get_tick(void);
|
||||
|
||||
static inline void spin(volatile uint32_t count) {
|
||||
while (count--)
|
||||
(void)0;
|
||||
}
|
||||
|
||||
#define SYS_FREQUENCY 260000000UL
|
||||
#define FRG_PLL_CLKDIV 13
|
||||
|
||||
enum { HAL_GPIO_MODE_INPUT, HAL_GPIO_MODE_OUTPUT };
|
||||
enum {
|
||||
HAL_GPIO_TYPE_NOPULL_WEAKEST = 0x0,
|
||||
HAL_GPIO_TYPE_NOPULL_WEAK = 0x4,
|
||||
HAL_GPIO_TYPE_NOPULL_STRONG = 0x8,
|
||||
HAL_GPIO_TYPE_NOPULL_STRONGEST = 0xC,
|
||||
HAL_GPIO_TYPE_PULLUP_WEAKEST = 0x1,
|
||||
HAL_GPIO_TYPE_PULLUP_WEAK = 0x5,
|
||||
HAL_GPIO_TYPE_PULLUP_STRONG = 0x9,
|
||||
HAL_GPIO_TYPE_PULLUP_STRONGEST = 0xD,
|
||||
HAL_GPIO_TYPE_PULLDOWN_WEAKEST = 0x2,
|
||||
HAL_GPIO_TYPE_PULLDOWN_WEAK = 0x6,
|
||||
HAL_GPIO_TYPE_PULLDOWN_STRONG = 0xA,
|
||||
HAL_GPIO_TYPE_PULLDOWN_STRONGEST = 0xE,
|
||||
HAL_GPIO_TYPE_NOPULL = HAL_GPIO_TYPE_NOPULL_STRONGEST,
|
||||
HAL_GPIO_TYPE_PULLUP = HAL_GPIO_TYPE_PULLUP_STRONGEST,
|
||||
HAL_GPIO_TYPE_PULLDOWN = HAL_GPIO_TYPE_PULLDOWN_STRONGEST,
|
||||
};
|
||||
|
||||
// Wrapper structure over the IO_MUX_* macros in fsl_io_mux.h
|
||||
// To use those macros with our gpio functions,
|
||||
// wrap them inside this structure as shown in the example from the
|
||||
// ethernet_init function.
|
||||
typedef struct
|
||||
{
|
||||
uint32_t pinLowMask, pinHighMask, gpioFcSetMask,
|
||||
gpioFcClrMask, fselSetMask, fselClrMask, ctimerSetMask,
|
||||
ctimerClrMask, sctimerSetMask, sctimerClrMask;
|
||||
} io_mux_config_t;
|
||||
|
||||
static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
io_mux_config_t *mux_config) {
|
||||
uint8_t bank = PINBANK(pin);
|
||||
uint8_t pin_no = PINNO(pin);
|
||||
if (mode == HAL_GPIO_MODE_INPUT) {
|
||||
GPIO->DIR[bank] &= ~(1 << pin_no);
|
||||
} else {
|
||||
GPIO->DIR[bank] |= (1 << pin_no);
|
||||
}
|
||||
|
||||
// configure pull
|
||||
pin_no += bank * 32;
|
||||
uint32_t shift = (pin_no % 16) * 2;
|
||||
uint32_t pull_val = (uint32_t)type & 3;
|
||||
uint32_t drive_val = ((uint32_t)type >> 2) & 3;
|
||||
volatile uint32_t *pull_reg, *drive_reg;
|
||||
if (pin_no < 22 || pin_no > 27) {
|
||||
pull_reg = &SOCCTRL->PAD_PU_PD_EN0 + pin_no / 16;
|
||||
drive_reg = &SOCCTRL->SR_CONFIG0 + pin_no / 16;
|
||||
} else {
|
||||
pull_reg = &AON_SOC_CIU->PAD_PU_PD_EN1;
|
||||
drive_reg = &AON_SOC_CIU->SR_CONFIG1;
|
||||
}
|
||||
*pull_reg = (*pull_reg & ~(3 << shift)) | (pull_val << shift);
|
||||
*drive_reg = (*drive_reg & ~(3 << shift)) | (drive_val << shift);
|
||||
|
||||
if (mux_config) {
|
||||
IO_MUX_SetPinMux(mux_config->pinLowMask, mux_config->pinHighMask,
|
||||
mux_config->gpioFcSetMask, mux_config->gpioFcClrMask,
|
||||
mux_config->fselSetMask, mux_config->fselClrMask,
|
||||
mux_config->ctimerSetMask, mux_config->ctimerClrMask,
|
||||
mux_config->sctimerSetMask, mux_config->sctimerClrMask
|
||||
);
|
||||
} else {
|
||||
// if no mux config is specified, assume default gpio settings and
|
||||
// no special function and just enable the IO
|
||||
IO_MUX_SetPinMux(bank ? 0 : BIT(PINNO(pin)), !bank ? 0 : BIT(PINNO(pin)),
|
||||
1 << 16, 0, 0, 0, 0, 0, 0, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void hal_gpio_input(uint16_t pin) {
|
||||
hal_gpio_init(pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_TYPE_PULLUP_STRONGEST, NULL);
|
||||
}
|
||||
static inline void hal_gpio_output(uint16_t pin) {
|
||||
hal_gpio_init(pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_TYPE_NOPULL_STRONGEST, NULL);
|
||||
}
|
||||
|
||||
static inline bool hal_gpio_read(uint16_t pin) {
|
||||
return GPIO->PIN[PINBANK(pin)] & (1 << PINNO(pin));
|
||||
}
|
||||
|
||||
static inline void hal_gpio_write(uint16_t pin, bool value) {
|
||||
if (value) {
|
||||
GPIO->SET[PINBANK(pin)] |= (1 << PINNO(pin));
|
||||
} else {
|
||||
GPIO->CLR[PINBANK(pin)] |= (1 << PINNO(pin));
|
||||
}
|
||||
}
|
||||
|
||||
static inline void hal_gpio_toggle(uint16_t pin) {
|
||||
hal_gpio_read(pin) ? hal_gpio_write(pin, false) : hal_gpio_write(pin, true);
|
||||
}
|
||||
|
||||
#if defined(__ZEPHYR__)
|
||||
#undef MG_HAL_DISABLE_SYSTEM_INIT
|
||||
#define MG_HAL_DISABLE_SYSTEM_INIT 1
|
||||
#undef MG_HAL_DISABLE_NEWLIB
|
||||
#define MG_HAL_DISABLE_NEWLIB 1
|
||||
#undef MG_HAL_DISABLE_CLOCK
|
||||
#define MG_HAL_DISABLE_CLOCK 1
|
||||
#undef MG_HAL_DISABLE_RANDOM
|
||||
#define MG_HAL_DISABLE_RANDOM 1
|
||||
#undef MG_HAL_DISABLE_MILLIS
|
||||
#define MG_HAL_DISABLE_MILLIS 1
|
||||
#undef MG_HAL_DISABLE_UART
|
||||
#define MG_HAL_DISABLE_UART 1
|
||||
#undef MG_HAL_DISABLE_ETHERNET
|
||||
#define MG_HAL_DISABLE_ETHERNET 1
|
||||
#undef MG_HAL_SYSTICK
|
||||
#define MG_HAL_SYSTICK MG_HAL_SYSTICK_NONE
|
||||
#endif
|
||||
|
||||
static inline void hal_uart_init(USART_Type *uart, unsigned long baud) {
|
||||
if (uart == USART0) {
|
||||
IO_MUX_SetPinMux(IO_MUX_FC0_USART_DATA);
|
||||
} else if (uart == USART1) {
|
||||
IO_MUX_SetPinMux(IO_MUX_FC1_USART_DATA);
|
||||
} else if (uart == USART2) {
|
||||
IO_MUX_SetPinMux(IO_MUX_FC2_USART_DATA);
|
||||
} else if (uart == USART3) {
|
||||
IO_MUX_SetPinMux(IO_MUX_FC3_USART_DATA);
|
||||
} else if (uart == USART14) {
|
||||
IO_MUX_SetPinMux(IO_MUX_FC14_USART_DATA);
|
||||
} else {
|
||||
return;
|
||||
}
|
||||
|
||||
uint32_t uart_index = ((uint32_t)uart - USART0_BASE) / 0x1000;
|
||||
|
||||
// set FRG clk
|
||||
CLKCTL1->FLEXCOMM[uart_index].FRGCLKSEL = kCLOCK_FrgPllDiv;
|
||||
CLKCTL1->FLEXCOMM[uart_index].FRGCTL =
|
||||
(CLKCTL1_FRGCTL_MULT(0) | CLKCTL1_FRGCTL_DIV(255));
|
||||
CLOCK_AttachClk(CLKCTL1_TUPLE_MUXA(0x508 + uart_index * 0x20, 4));
|
||||
|
||||
// set FLEXCOMM to USART mode
|
||||
CLOCK_EnableClock(CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, uart_index + 8));
|
||||
uint32_t mask = BIT(uart_index + 8);
|
||||
RSTCTL1->PRSTCTL0_SET = mask;
|
||||
while ((RSTCTL1->PRSTCTL0 & mask) == 0)
|
||||
spin(1);
|
||||
RSTCTL1->PRSTCTL0_CLR = mask;
|
||||
while ((RSTCTL1->PRSTCTL0 & mask) == mask)
|
||||
spin(1);
|
||||
((FLEXCOMM_Type *)uart)->PSELID = 1;
|
||||
|
||||
uart->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK |
|
||||
USART_FIFOCFG_ENABLETX_MASK; // empty and enable txFIFO
|
||||
uart->CFG = BIT(2) | BIT(0); // 8 bit data length and enable
|
||||
|
||||
// compute baud
|
||||
uint32_t uart_freq = SYS_FREQUENCY / FRG_PLL_CLKDIV;
|
||||
uint32_t best_diff = (uint32_t)-1, best_osr = 0xF, best_brg = (uint32_t)-1;
|
||||
uint32_t osr, brg, diff, current_baud;
|
||||
for (osr = 15; osr >= 4; osr--) {
|
||||
brg = (((uart_freq * 10) / ((osr + 1) * baud)) - 5) / 10;
|
||||
if (brg > 0xFFFF)
|
||||
continue;
|
||||
current_baud = uart_freq / ((osr + 1) * (brg + 1));
|
||||
diff =
|
||||
(baud < current_baud) ? (current_baud - baud) : (baud - current_baud);
|
||||
if (diff < best_diff) {
|
||||
best_diff = diff;
|
||||
best_osr = osr;
|
||||
best_brg = brg;
|
||||
}
|
||||
}
|
||||
uart->OSR = best_osr;
|
||||
uart->BRG = best_brg;
|
||||
}
|
||||
|
||||
static inline void hal_uart_write_byte(USART_Type *uart, uint8_t byte) {
|
||||
while ((uart->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) == 0)
|
||||
spin(1);
|
||||
uart->FIFOWR = byte;
|
||||
}
|
||||
static inline void hal_uart_write_buf(USART_Type *uart, char *buf, size_t len) {
|
||||
while (len-- > 0)
|
||||
hal_uart_write_byte(uart, *(uint8_t *)buf++);
|
||||
}
|
||||
|
||||
static inline void hal_rng_init(void) {
|
||||
trng_config_t config;
|
||||
TRNG_GetDefaultConfig(&config);
|
||||
TRNG_Init(TRNG, &config);
|
||||
}
|
||||
|
||||
static inline uint32_t hal_rng_read(void) {
|
||||
uint32_t value;
|
||||
TRNG_GetRandomData(TRNG, &value, sizeof(value));
|
||||
return value;
|
||||
}
|
||||
|
||||
static inline void hal_ethernet_init(void) {
|
||||
CLOCK_EnableClock(kCLOCK_TddrMciEnetClk);
|
||||
hal_gpio_init(PIN(0, 25), HAL_GPIO_MODE_OUTPUT, IO_MUX_PinConfigPullUpDriveWeak,
|
||||
&(io_mux_config_t){ IO_MUX_ENET_CLK }); // ENET_CLK on GPIO_25
|
||||
IO_MUX_SetPinMux(
|
||||
IO_MUX_ENET_RX); // ENET_RX on pin GPIO_62, GPIO_63, GPIO_22, GPIO_23
|
||||
IO_MUX_SetPinMux(IO_MUX_ENET_TX); // ENET_TX on pin GPIO_58, GPIO_59, GPIO_60
|
||||
IO_MUX_SetPinMux(IO_MUX_ENET_MDIO); // ENET_MDIO on pin GPIO_56, GPIO_57
|
||||
|
||||
// reset ENET peripheral
|
||||
RSTCTL0->PRSTCTL1_SET = BIT(25);
|
||||
while ((RSTCTL0->PRSTCTL1 & BIT(25)) == 0)
|
||||
spin(1);
|
||||
RSTCTL0->PRSTCTL1_CLR = BIT(25);
|
||||
while ((RSTCTL0->PRSTCTL1 & BIT(25)) == BIT(25))
|
||||
spin(1);
|
||||
RSTCTL0->PRSTCTL1_SET = BIT(26);
|
||||
while ((RSTCTL0->PRSTCTL1 & BIT(26)) == 0)
|
||||
spin(1);
|
||||
RSTCTL0->PRSTCTL1_CLR = BIT(26);
|
||||
while ((RSTCTL0->PRSTCTL1 & BIT(26)) == BIT(26))
|
||||
spin(1);
|
||||
|
||||
// Enable clocks
|
||||
CLOCK_EnableClock(kCLOCK_EnetIpg);
|
||||
CLOCK_EnableClock(kCLOCK_EnetIpgS);
|
||||
|
||||
NVIC_EnableIRQ(ENET_IRQn);
|
||||
}
|
||||
extern void set_flexspi_clock(FLEXSPI_Type *base, uint32_t src,
|
||||
uint32_t divider);
|
||||
static inline void hal_clock_init(void) {
|
||||
const clock_avpll_config_t avpllConfig_BOARD_BootClockRUN = {
|
||||
.ch1Freq =
|
||||
kCLOCK_AvPllChFreq12p288m, // AVPLL channel frequency 12.288 MHz
|
||||
.ch2Freq = kCLOCK_AvPllChFreq64m, // AVPLL channel frequency 64 MHz
|
||||
.enableCali = true, // AVPLL calibration is enabled
|
||||
};
|
||||
if ((PMU->CAU_SLP_CTRL & PMU_CAU_SLP_CTRL_SOC_SLP_RDY_MASK) == 0) {
|
||||
CLOCK_EnableClock(
|
||||
kCLOCK_RefClkCauSlp); // Enable the CAU sleep clock for PMU
|
||||
}
|
||||
if ((SYSCTL2->SOURCE_CLK_GATE & SYSCTL2_SOURCE_CLK_GATE_REFCLK_SYS_CG_MASK) !=
|
||||
0) {
|
||||
CLOCK_EnableClock(kCLOCK_RefClkSys); // Enable the REFCLK_SYS clock
|
||||
}
|
||||
CLOCK_InitT3RefClk(kCLOCK_T3MciIrc48m); // Initialize T3 PLL and enable
|
||||
// outputs that are not clock gated
|
||||
CLOCK_EnableClock(
|
||||
kCLOCK_T3PllMciIrcClk); // Enable FFRO - T3 PLL 48/60 MHz IRC clock output
|
||||
CLOCK_EnableClock(
|
||||
kCLOCK_T3PllMci256mClk); // Enable T3 PLL 256 MHz clock output
|
||||
|
||||
// Move FLEXSPI clock source to T3 256M / 4 to avoid instruction/data fetch
|
||||
// issue in XIP when updating PLL and main clock.
|
||||
set_flexspi_clock(FLEXSPI, 6, 4);
|
||||
CLOCK_AttachClk(kSYSOSC_to_MAIN_CLK); // Set core clock to safe system
|
||||
// oscillator for initialization
|
||||
CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk,
|
||||
1); // Set system CPU AHB clock divider to 1
|
||||
CLOCK_InitTcpuRefClk(
|
||||
3120000000UL,
|
||||
kCLOCK_TcpuFlexspiDiv10); // Initialize TCPU PLL and enable outputs
|
||||
CLOCK_EnableClock(kCLOCK_TcpuMciClk); // Enable TCPU PLL MCI clock output
|
||||
CLOCK_InitTddrRefClk(
|
||||
kCLOCK_TddrFlexspiDiv10); // Initialize TDDR PLL and enable outputs
|
||||
CLOCK_EnableClock(
|
||||
kCLOCK_TddrMciFlexspiClk); // Enable TDDR PLL FlexSPI clock output
|
||||
CLOCK_InitAvPll(&avpllConfig_BOARD_BootClockRUN); // Initialize AVPLL and
|
||||
// enable both channels
|
||||
CLOCK_AttachClk(kRC32K_to_CLK32K); // Switch CLK32K to RC32K
|
||||
CLOCK_AttachClk(
|
||||
kSYSTICK_DIV_to_SYSTICK_CLK); // Switch SYSTICK_CLK to SYSTICK_DIV
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U); // Set AUDIOPLLCLKDIV divider to 1
|
||||
CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk,
|
||||
FRG_PLL_CLKDIV); // Set FRGPLLCLKDIV divider
|
||||
CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U); // Set MAINPLLCLKDIV divider to 1
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U); // Set AUX0PLLCLKDIV divider to 1
|
||||
CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U); // Set SYSTICKFCLKDIV divider to 1
|
||||
CLOCK_SetClkDiv(kCLOCK_DivPmuFclk, 5U); // Set PMUFCLKDIV divider to 5
|
||||
CLOCK_AttachClk(
|
||||
kMAIN_PLL_to_MAIN_CLK); // Select the main clock source for system clock
|
||||
set_flexspi_clock(FLEXSPI, 2U, 2U); // set_flexspi_clock
|
||||
|
||||
CLOCK_EnableClock(kCLOCK_HsGpio0);
|
||||
RSTCTL1->PRSTCTL1_SET = BIT(0); // Reset GPIO_0
|
||||
while ((RSTCTL1->PRSTCTL1 & BIT(0)) == 0)
|
||||
spin(1);
|
||||
RSTCTL1->PRSTCTL1_CLR = BIT(0);
|
||||
while ((RSTCTL1->PRSTCTL1 & BIT(0)) == BIT(0))
|
||||
spin(1);
|
||||
|
||||
CLOCK_EnableClock(kCLOCK_HsGpio1);
|
||||
RSTCTL1->PRSTCTL1_SET = BIT(1); // Reset GPIO_1
|
||||
while ((RSTCTL1->PRSTCTL1 & BIT(1)) == 0)
|
||||
spin(1);
|
||||
RSTCTL1->PRSTCTL1_CLR = BIT(1);
|
||||
while ((RSTCTL1->PRSTCTL1 & BIT(1)) == BIT(1))
|
||||
spin(1);
|
||||
}
|
||||
|
||||
#if defined(__MCUXPRESSO)
|
||||
#undef MG_HAL_DISABLE_SYSTEM_INIT
|
||||
#define MG_HAL_DISABLE_SYSTEM_INIT 1
|
||||
#undef MG_HAL_SBRK_NONE
|
||||
#define MG_HAL_SBRK_NONE 1
|
||||
#endif
|
||||
|
||||
static inline void hal_system_init(void) {
|
||||
SCB->CPACR |=
|
||||
(3UL << 0 * 2) | (3UL << 1 * 2) | // Enable PowerQuad (CPO/CP1)
|
||||
(3UL << 10 * 2) | (3UL << 11 * 2); // Enable FPU
|
||||
SCB->NSACR |= ((3UL << 0) | (3UL << 10));
|
||||
CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK;
|
||||
CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK;
|
||||
while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0) spin(1);
|
||||
// Enable cache, enable write buffer
|
||||
CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK);
|
||||
|
||||
// Set whole FlexSPI0 space to write through
|
||||
CACHE64_POLSEL0->REG0_TOP = 0x07FFFC00U;
|
||||
CACHE64_POLSEL0->REG1_TOP = 0x0U;
|
||||
CACHE64_POLSEL0->POLSEL = 0x1U;
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
@@ -0,0 +1,36 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash(rx) : ORIGIN = 0x08000000, LENGTH = 0x4000000
|
||||
sram(rwx) : ORIGIN = 0x20000000, LENGTH = 0x130000
|
||||
}
|
||||
__StackTop = ORIGIN(sram) + LENGTH(sram);
|
||||
|
||||
SECTIONS {
|
||||
.boot_hdr : ALIGN(4) { FILL(0xFF); . = 0x400; __FLASH_BASE = .; KEEP(*(.flash_conf)) . = 0x1000; } > flash
|
||||
.vectors : { FILL(256) KEEP(*(.isr_vector)) } > flash
|
||||
.text : { *(.text.* *.text.*) } > flash
|
||||
.rodata : { *(.rodata*) } > flash
|
||||
|
||||
.iram : {
|
||||
_siram = .;
|
||||
*(.iram)
|
||||
_eiram = .;
|
||||
} > sram AT > flash
|
||||
_siiram = LOADADDR(.iram);
|
||||
|
||||
.data : {
|
||||
_sdata = .;
|
||||
*(.first_data)
|
||||
*(.data SORT(.data.*))
|
||||
_edata = .;
|
||||
} > sram AT > flash
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : { _sbss = .; *(.bss SORT(.bss.*) COMMON) _ebss = .; } > sram
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
|
||||
_image_start = LOADADDR(.text);
|
||||
_image_end = LOADADDR(.data) + SIZEOF(.data);
|
||||
_image_size = _image_end - _image_start;
|
||||
}
|
||||
@@ -0,0 +1,77 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "mongoose.h"
|
||||
#include "hal.h"
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG USART3
|
||||
#endif
|
||||
|
||||
#define LED1 PIN(0, 12) // Green
|
||||
#define LED2 PIN(0, 0) // Blue
|
||||
#define LED3 PIN(0, 1) // Red
|
||||
|
||||
static void log_fn(char ch, void *param) {
|
||||
hal_uart_write_buf(param, &ch, 1);
|
||||
}
|
||||
|
||||
static void blink_task(void) {
|
||||
static uint64_t blink_timer = 0;
|
||||
if (hal_timer_expired(&blink_timer, 500, hal_get_tick())) {
|
||||
hal_gpio_toggle(LED1);
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t mg_millis(void) {
|
||||
return hal_get_tick();
|
||||
}
|
||||
|
||||
#if MG_ENABLE_CUSTOM_RANDOM
|
||||
bool mg_random(void *buf, size_t len) {
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = hal_rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) {
|
||||
if (ev == MG_EV_HTTP_MSG) { // New HTTP request received
|
||||
struct mg_http_message *hm = (struct mg_http_message *) ev_data;
|
||||
if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) {
|
||||
mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), hal_get_tick());
|
||||
} else {
|
||||
mg_http_reply(c, 200, "", "Hi from Mongoose, tick %llu\n",
|
||||
hal_get_tick());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
hal_clock_init();
|
||||
hal_rng_init();
|
||||
hal_gpio_output(LED1);
|
||||
hal_gpio_write(LED1, true);
|
||||
hal_gpio_output(LED2);
|
||||
hal_gpio_write(LED2, true);
|
||||
hal_gpio_output(LED3);
|
||||
hal_gpio_write(LED3, true);
|
||||
hal_uart_init(UART_DEBUG, 115200);
|
||||
mg_log_set_fn(log_fn, UART_DEBUG);
|
||||
|
||||
hal_ethernet_init();
|
||||
|
||||
// Start a minimal web server
|
||||
struct mg_mgr mgr;
|
||||
mg_mgr_init(&mgr);
|
||||
mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL);
|
||||
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
blink_task();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,29 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_ARMGCC
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_DRIVER_RW612 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_OTA MG_OTA_RW612
|
||||
|
||||
// #define MG_DRIVER_MDC_CR 51 // RMII MDC clock divider
|
||||
// #define MG_DRIVER_MDC_HOLDTIME 3 // RMII MDC Holdtime (valid values [0-7])
|
||||
// #define MG_TCPIP_PHY_ADDR 2 // PHY address
|
||||
|
||||
// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
|
||||
// By default, those are set to zero, meaning that DHCP is used
|
||||
//
|
||||
// #define MG_TCPIP_IP MG_IPV4(192, 168, 1, 10)
|
||||
// #define MG_TCPIP_GW MG_IPV4(192, 168, 1, 1)
|
||||
// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0)
|
||||
|
||||
// Set custom MAC address. By default, it is randomly generated
|
||||
// Using a build-time constant:
|
||||
// #define MG_SET_MAC_ADDRESS(mac) do { mac[0] = 2; mac[1] = 3; mac[2] = 4; mac[3] = 5; mac[4] = 6; mac[5] = 7; } while (0)
|
||||
//
|
||||
// Using custom function:
|
||||
// extern void my_function(unsigned char *mac);
|
||||
// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)
|
||||
@@ -0,0 +1,338 @@
|
||||
#include "RW612.h"
|
||||
|
||||
void Reset_Handler(void); // Defined below
|
||||
void Dummy_Handler(void); // Defined below
|
||||
void SysTick_Handler(void); // Defined in main.c
|
||||
void SystemInit(void); // Defined in main.c, called by reset handler
|
||||
void __StackTop(void); // Defined in link.ld
|
||||
void _image_size(void);
|
||||
|
||||
#define WEAK __attribute__((weak, alias("Default_Handler")))
|
||||
|
||||
void Default_Handler(void);
|
||||
WEAK void NMI_Handler(void);
|
||||
WEAK void HardFault_Handler(void);
|
||||
WEAK void MemManage_Handler(void);
|
||||
WEAK void BusFault_Handler(void);
|
||||
WEAK void UsageFault_Handler(void);
|
||||
WEAK void SecureFault_Handler(void);
|
||||
WEAK void SVC_Handler(void);
|
||||
WEAK void DebugMon_Handler(void);
|
||||
WEAK void PendSV_Handler(void);
|
||||
WEAK void SysTick_Handler(void);
|
||||
WEAK void IntDefaultHandler(void);
|
||||
WEAK void WDT0_IRQHandler(void);
|
||||
WEAK void DMA0_IRQHandler(void);
|
||||
WEAK void GPIO_INTA_IRQHandler(void);
|
||||
WEAK void GPIO_INTB_IRQHandler(void);
|
||||
WEAK void PIN_INT0_IRQHandler(void);
|
||||
WEAK void PIN_INT1_IRQHandler(void);
|
||||
WEAK void PIN_INT2_IRQHandler(void);
|
||||
WEAK void PIN_INT3_IRQHandler(void);
|
||||
WEAK void UTICK_IRQHandler(void);
|
||||
WEAK void MRT_IRQHandler(void);
|
||||
WEAK void CTIMER0_IRQHandler(void);
|
||||
WEAK void CTIMER1_IRQHandler(void);
|
||||
WEAK void SCT0_IRQHandler(void);
|
||||
WEAK void CTIMER3_IRQHandler(void);
|
||||
WEAK void FLEXCOMM0_IRQHandler(void);
|
||||
WEAK void FLEXCOMM1_IRQHandler(void);
|
||||
WEAK void FLEXCOMM2_IRQHandler(void);
|
||||
WEAK void FLEXCOMM3_IRQHandler(void);
|
||||
WEAK void Reserved34_IRQHandler(void);
|
||||
WEAK void Reserved35_IRQHandler(void);
|
||||
WEAK void FLEXCOMM14_IRQHandler(void);
|
||||
WEAK void Reserved37_IRQHandler(void);
|
||||
WEAK void Reserved38_IRQHandler(void);
|
||||
WEAK void GFMRT_IRQHandler(void);
|
||||
WEAK void Reserved40_IRQHandler(void);
|
||||
WEAK void DMIC_IRQHandler(void);
|
||||
WEAK void WKDEEPSLEEP_IRQHandler(void);
|
||||
WEAK void HYPERVISOR_IRQHandler(void);
|
||||
WEAK void SECUREVIOLATION_IRQHandler(void);
|
||||
WEAK void HWVAD_IRQHandler(void);
|
||||
WEAK void Reserved46_IRQHandler(void);
|
||||
WEAK void Reserved47_IRQHandler(void);
|
||||
WEAK void RTC_IRQHandler(void);
|
||||
WEAK void Reserved49_IRQHandler(void);
|
||||
WEAK void Reserved50_IRQHandler(void);
|
||||
WEAK void PIN_INT4_IRQHandler(void);
|
||||
WEAK void PIN_INT5_IRQHandler(void);
|
||||
WEAK void PIN_INT6_IRQHandler(void);
|
||||
WEAK void PIN_INT7_IRQHandler(void);
|
||||
WEAK void CTIMER2_IRQHandler(void);
|
||||
WEAK void CTIMER4_IRQHandler(void);
|
||||
WEAK void OS_EVENT_TIMER_IRQHandler(void);
|
||||
WEAK void FLEXSPI_IRQHandler(void);
|
||||
WEAK void Reserved59_IRQHandler(void);
|
||||
WEAK void Reserved60_IRQHandler(void);
|
||||
WEAK void Reserved61_IRQHandler(void);
|
||||
WEAK void SDIO_IRQHandler(void);
|
||||
WEAK void SGPIO_INTA_IRQHandler(void);
|
||||
WEAK void SGPIO_INTB_IRQHandler(void);
|
||||
WEAK void Reserved65_IRQHandler(void);
|
||||
WEAK void USB_IRQHandler(void);
|
||||
WEAK void Reserved67_IRQHandler(void);
|
||||
WEAK void Reserved68_IRQHandler(void);
|
||||
WEAK void Reserved69_IRQHandler(void);
|
||||
WEAK void DMA1_IRQHandler(void);
|
||||
WEAK void PUF_IRQHandler(void);
|
||||
WEAK void POWERQUAD_IRQHandler(void);
|
||||
WEAK void Reserved73_IRQHandler(void);
|
||||
WEAK void Reserved74_IRQHandler(void);
|
||||
WEAK void Reserved75_IRQHandler(void);
|
||||
WEAK void Reserved76_IRQHandler(void);
|
||||
WEAK void LCD_IRQHandler(void);
|
||||
WEAK void CAPTIMER_IRQHandler(void);
|
||||
WEAK void Reserved79_IRQHandler(void);
|
||||
WEAK void W2MWKUP_DONE0_IRQHandler(void);
|
||||
WEAK void W2MWKUP_DONE1_IRQHandler(void);
|
||||
WEAK void W2MWKUP_DONE2_IRQHandler(void);
|
||||
WEAK void W2MWKUP_DONE3_IRQHandler(void);
|
||||
WEAK void W2MWKUP_DONE4_IRQHandler(void);
|
||||
WEAK void W2MWKUP_DONE5_IRQHandler(void);
|
||||
WEAK void W2MWKUP_DONE6_IRQHandler(void);
|
||||
WEAK void W2MWKUP_DONE7_IRQHandler(void);
|
||||
WEAK void W2MWKUP0_IRQHandler(void);
|
||||
WEAK void W2MWKUP1_IRQHandler(void);
|
||||
WEAK void WL_MCI_INT0_IRQHandler(void);
|
||||
WEAK void WL_MCI_INT1_IRQHandler(void);
|
||||
WEAK void WL_MCI_INT2_IRQHandler(void);
|
||||
WEAK void WL_MCI_INT3_IRQHandler(void);
|
||||
WEAK void WL_MCI_INT4_IRQHandler(void);
|
||||
WEAK void WL_MCI_INT5_IRQHandler(void);
|
||||
WEAK void WL_MCI_INT6_IRQHandler(void);
|
||||
WEAK void WL_MCI_INT7_IRQHandler(void);
|
||||
WEAK void B2MWKUP_DONE0_IRQHandler(void);
|
||||
WEAK void B2MWKUP_DONE1_IRQHandler(void);
|
||||
WEAK void B2MWKUP_DONE2_IRQHandler(void);
|
||||
WEAK void B2MWKUP_DONE3_IRQHandler(void);
|
||||
WEAK void B2MWKUP_DONE4_IRQHandler(void);
|
||||
WEAK void B2MWKUP_DONE5_IRQHandler(void);
|
||||
WEAK void B2MWKUP_DONE6_IRQHandler(void);
|
||||
WEAK void B2MWKUP_DONE7_IRQHandler(void);
|
||||
WEAK void B2MWKUP0_IRQHandler(void);
|
||||
WEAK void B2MWKUP1_IRQHandler(void);
|
||||
WEAK void BLE_MCI_INT0_IRQHandler(void);
|
||||
WEAK void BLE_MCI_INT1_IRQHandler(void);
|
||||
WEAK void BLE_MCI_INT2_IRQHandler(void);
|
||||
WEAK void BLE_MCI_INT3_IRQHandler(void);
|
||||
WEAK void BLE_MCI_INT4_IRQHandler(void);
|
||||
WEAK void BLE_MCI_INT5_IRQHandler(void);
|
||||
WEAK void BLE_MCI_INT6_IRQHandler(void);
|
||||
WEAK void BLE_MCI_INT7_IRQHandler(void);
|
||||
WEAK void PIN0_INT_IRQHandler(void);
|
||||
WEAK void PIN1_INT_IRQHandler(void);
|
||||
WEAK void ELS_IRQHandler(void);
|
||||
WEAK void ELS_GDET_IRQHandler(void);
|
||||
WEAK void ELS_GDET_UM_IRQHandler(void);
|
||||
WEAK void PKC_INT_IRQHandler(void);
|
||||
WEAK void PKC_ERR_IRQHandler(void);
|
||||
WEAK void CDOG_INT_IRQHandler(void);
|
||||
WEAK void GAU_DAC_IRQHandler(void);
|
||||
WEAK void GAU_ACOMP_WKUP_IRQHandler(void);
|
||||
WEAK void GAU_ACOMP_IRQHandler(void);
|
||||
WEAK void GAU_ADC1_IRQHandler(void);
|
||||
WEAK void GAU_ADC0_IRQHandler(void);
|
||||
WEAK void USIM_IRQHandler(void);
|
||||
WEAK void OTP_IRQHandler(void);
|
||||
WEAK void ENET_IRQHandler(void);
|
||||
WEAK void ENET_TIMER_IRQHandler(void);
|
||||
WEAK void PMIP_IRQHandler(void);
|
||||
WEAK void PMIP_CHANGE_IRQHandler(void);
|
||||
WEAK void ITRC_IRQHandler(void);
|
||||
WEAK void Reserved136_IRQHandler(void);
|
||||
WEAK void Reserved137_IRQHandler(void);
|
||||
WEAK void Reserved138_IRQHandler(void);
|
||||
WEAK void TRNG_IRQHandler(void);
|
||||
WEAK void ACC_C_INT_IRQHandler(void);
|
||||
WEAK void ACC_S_INT_IRQHandler(void);
|
||||
WEAK void WACC_IRQHandler(void);
|
||||
WEAK void BACC_IRQHandler(void);
|
||||
WEAK void GDMA_IRQHandler(void);
|
||||
|
||||
|
||||
#define WEAK_ALIAS __attribute__((weak, alias("Default_Handler")))
|
||||
|
||||
|
||||
__attribute__((section(".vectors"))) void (*const tab[16 + 156])(void) = {
|
||||
&__StackTop, // The initial stack pointer
|
||||
Reset_Handler, // The reset handler
|
||||
NMI_Handler, // NMI Handler
|
||||
HardFault_Handler, // Hard Fault Handler
|
||||
MemManage_Handler, // MPU Fault Handler
|
||||
BusFault_Handler, // Bus Fault Handler
|
||||
UsageFault_Handler, // Usage Fault Handler
|
||||
SecureFault_Handler, // Secure Fault Handler
|
||||
&_image_size, // Image size
|
||||
0, // Image type
|
||||
0, // Reserved
|
||||
SVC_Handler, // SVCall Handler
|
||||
DebugMon_Handler, // Debug Monitor Handler
|
||||
(void (*)())tab, // Image load address
|
||||
PendSV_Handler, // PendSV Handler
|
||||
SysTick_Handler, // SysTick Handler
|
||||
|
||||
// Chip Level - RW612
|
||||
WDT0_IRQHandler, // 16 : Windowed watchdog timer 0 (WDT0)(Cortex-M33 watchdog)
|
||||
DMA0_IRQHandler, // 17 : Direct memory access (DMA) controller 0 (secure or Cortex-M33 DMA)
|
||||
GPIO_INTA_IRQHandler, // 18 : GPIO interrupt A
|
||||
GPIO_INTB_IRQHandler, // 19 : GPIO interrupt B
|
||||
PIN_INT0_IRQHandler, // 20 : Pin interrupt 0 or pattern match engine slice 0
|
||||
PIN_INT1_IRQHandler, // 21 : Pin interrupt 1 or pattern match engine slice 1
|
||||
PIN_INT2_IRQHandler, // 22 : Pin interrupt 2 or pattern match engine slice 2
|
||||
PIN_INT3_IRQHandler, // 23 : Pin interrupt 3 or pattern match engine slice 3
|
||||
UTICK_IRQHandler, // 24 : Micro-tick Timer (UTICK)
|
||||
MRT_IRQHandler, // 25 : Multi-Rate Timer (MRT). Global MRT interrupts
|
||||
CTIMER0_IRQHandler, // 26 : Standard counter/timer CTIMER0
|
||||
CTIMER1_IRQHandler, // 27 : Standard counter/timer CTIMER1
|
||||
SCT0_IRQHandler, // 28 : SCTimer/PWM
|
||||
CTIMER3_IRQHandler, // 29 : Standard counter/timer CTIMER3
|
||||
FLEXCOMM0_IRQHandler, // 30 : Flexcomm Interface 0 (USART, SPI, I2C, I2S)
|
||||
FLEXCOMM1_IRQHandler, // 31 : Flexcomm Interface 1 (USART, SPI, I2C, I2S)
|
||||
FLEXCOMM2_IRQHandler, // 32 : Flexcomm Interface 2 (USART, SPI, I2C, I2S)
|
||||
FLEXCOMM3_IRQHandler, // 33 : Flexcomm Interface 3 (USART, SPI, I2C, I2S)
|
||||
Reserved34_IRQHandler, // 34 : Reserved interrupt
|
||||
Reserved35_IRQHandler, // 35 : Reserved interrupt
|
||||
FLEXCOMM14_IRQHandler, // 36 : Flexcomm Interface 14 (USART, SPI, I2C, I2S)
|
||||
Reserved37_IRQHandler, // 37 : Reserved interrupt
|
||||
Reserved38_IRQHandler, // 38 : Reserved interrupt
|
||||
GFMRT_IRQHandler, // 39 : Free Multi-rate timer (GFMRT). Global MRT interrupts
|
||||
Reserved40_IRQHandler, // 40 : Reserved interrupt
|
||||
DMIC_IRQHandler, // 41 : Digital microphone (DMIC) and DMIC subsystem
|
||||
WKDEEPSLEEP_IRQHandler, // 42 : Wake-up from deep sleep
|
||||
HYPERVISOR_IRQHandler, // 43 : Hypervisor service software interrupt
|
||||
SECUREVIOLATION_IRQHandler, // 44 : Secure violation
|
||||
HWVAD_IRQHandler, // 45 : Hardware Voice Activity Detector
|
||||
Reserved46_IRQHandler, // 46 : Reserved interrupt
|
||||
Reserved47_IRQHandler, // 47 : Reserved interrupt
|
||||
RTC_IRQHandler, // 48 : RTC alarm and wake-up
|
||||
Reserved49_IRQHandler, // 49 : Reserved interrupt
|
||||
Reserved50_IRQHandler, // 50 : Reserved interrupt
|
||||
PIN_INT4_IRQHandler, // 51 : Pin interrupt 4 or pattern match engine slice 4
|
||||
PIN_INT5_IRQHandler, // 52 : Pin interrupt 5 or pattern match engine slice 5
|
||||
PIN_INT6_IRQHandler, // 53 : Pin interrupt 6 or pattern match engine slice 6
|
||||
PIN_INT7_IRQHandler, // 54 : Pin interrupt 7 or pattern match engine slice 7
|
||||
CTIMER2_IRQHandler, // 55 : Standard counter/timer CTIMER2
|
||||
CTIMER4_IRQHandler, // 56 : Standard counter/timer CTIMER4
|
||||
OS_EVENT_TIMER_IRQHandler, // 57 : OS event timer 0
|
||||
FLEXSPI_IRQHandler, // 58 : FLEXSPI interface
|
||||
Reserved59_IRQHandler, // 59 : Reserved interrupt
|
||||
Reserved60_IRQHandler, // 60 : Reserved interrupt
|
||||
Reserved61_IRQHandler, // 61 : Reserved interrupt
|
||||
SDIO_IRQHandler, // 62 : The secure digital interface
|
||||
SGPIO_INTA_IRQHandler, // 63 : Secure GPIO interrupt A
|
||||
SGPIO_INTB_IRQHandler, // 64 : Secure GPIO interrupt B
|
||||
Reserved65_IRQHandler, // 65 : Reserved interrupt
|
||||
USB_IRQHandler, // 66 : High-speed USB device/host
|
||||
Reserved67_IRQHandler, // 67 : Reserved interrupt
|
||||
Reserved68_IRQHandler, // 68 : Reserved interrupt
|
||||
Reserved69_IRQHandler, // 69 : Reserved interrupt
|
||||
DMA1_IRQHandler, // 70 : DMA controller 1 (non-secure or HiFi 4 DMA)
|
||||
PUF_IRQHandler, // 71 : Physical Unclonable Function
|
||||
POWERQUAD_IRQHandler, // 72 : PowerQuad math coprocessor
|
||||
Reserved73_IRQHandler, // 73 : Reserved interrupt
|
||||
Reserved74_IRQHandler, // 74 : Reserved interrupt
|
||||
Reserved75_IRQHandler, // 75 : Reserved interrupt
|
||||
Reserved76_IRQHandler, // 76 : Reserved interrupt
|
||||
LCD_IRQHandler, // 77 : LCDIC
|
||||
CAPTIMER_IRQHandler, // 78 : Capture timer
|
||||
Reserved79_IRQHandler, // 79 : Reserved interrupt
|
||||
W2MWKUP_DONE0_IRQHandler, // 80 : Wi-Fi to MCU, wakeup done 0
|
||||
W2MWKUP_DONE1_IRQHandler, // 81 : Wi-Fi to MCU, wakeup done 1
|
||||
W2MWKUP_DONE2_IRQHandler, // 82 : Wi-Fi to MCU, wakeup done 2
|
||||
W2MWKUP_DONE3_IRQHandler, // 83 : Wi-Fi to MCU, wakeup done 3
|
||||
W2MWKUP_DONE4_IRQHandler, // 84 : Wi-Fi to MCU, wakeup done 4
|
||||
W2MWKUP_DONE5_IRQHandler, // 85 : Wi-Fi to MCU, wakeup done 5
|
||||
W2MWKUP_DONE6_IRQHandler, // 86 : Wi-Fi to MCU, wakeup done 6
|
||||
W2MWKUP_DONE7_IRQHandler, // 87 : Wi-Fi to MCU, wakeup done 7
|
||||
W2MWKUP0_IRQHandler, // 88 : Wi-Fi to MCU, wakeup signal 0
|
||||
W2MWKUP1_IRQHandler, // 89 : Wi-Fi to MCU, wakueup signal 1
|
||||
WL_MCI_INT0_IRQHandler, // 90 : Wi-Fi to MCU interrupt 0
|
||||
WL_MCI_INT1_IRQHandler, // 91 : Reserved for Wi-Fi to MCU
|
||||
WL_MCI_INT2_IRQHandler, // 92 : Reserved for Wi-Fi to MCU
|
||||
WL_MCI_INT3_IRQHandler, // 93 : Reserved for Wi-Fi to MCU
|
||||
WL_MCI_INT4_IRQHandler, // 94 : Reserved for Wi-Fi to MCU
|
||||
WL_MCI_INT5_IRQHandler, // 95 : Reserved for Wi-Fi to MCU
|
||||
WL_MCI_INT6_IRQHandler, // 96 : Reserved for Wi-Fi to MCU
|
||||
WL_MCI_INT7_IRQHandler, // 97 : Reserved for Wi-Fi to MCU
|
||||
B2MWKUP_DONE0_IRQHandler, // 98 : Bluetooth LE/802.15.4 radio to MCU, wakeup done 0
|
||||
B2MWKUP_DONE1_IRQHandler, // 99 : Bluetooth LE/802.15.4 radio to MCU, wakeup done 1
|
||||
B2MWKUP_DONE2_IRQHandler, // 100: Bluetooth LE/802.15.4 radio to MCU, wakeup done 2
|
||||
B2MWKUP_DONE3_IRQHandler, // 101: Bluetooth LE/802.15.4 radio to MCU, wakeup done 3
|
||||
B2MWKUP_DONE4_IRQHandler, // 102: Bluetooth LE/802.15.4 radio to MCU, wakeup done 4
|
||||
B2MWKUP_DONE5_IRQHandler, // 103: Bluetooth LE/802.15.4 radio to MCU, wakeup done 5
|
||||
B2MWKUP_DONE6_IRQHandler, // 104: Bluetooth LE/802.15.4 radio to MCU, wakeup done 6
|
||||
B2MWKUP_DONE7_IRQHandler, // 105: Bluetooth LE/802.15.4 radio to MCU, wakeup done 7
|
||||
B2MWKUP0_IRQHandler, // 106: Bluetooth LE/802.15.4 radio to MCU, wakeup signal 0
|
||||
B2MWKUP1_IRQHandler, // 107: Bluetooth LE/802.15.4 radio to MCU, wakeup signal 1
|
||||
BLE_MCI_INT0_IRQHandler, // 108: Bluetooth LE/802.15.4 radio to MCU interrupt 0
|
||||
BLE_MCI_INT1_IRQHandler, // 109: Reserved for Bluetooth LE/802.15.4 radio to MCU
|
||||
BLE_MCI_INT2_IRQHandler, // 110: Reserved for Bluetooth LE/802.15.4 radio to MCU
|
||||
BLE_MCI_INT3_IRQHandler, // 111: Reserved for Bluetooth LE/802.15.4 radio to MCU
|
||||
BLE_MCI_INT4_IRQHandler, // 112: Reserved for Bluetooth LE/802.15.4 radio to MCU
|
||||
BLE_MCI_INT5_IRQHandler, // 113: Reserved for Bluetooth LE/802.15.4 radio to MCU
|
||||
BLE_MCI_INT6_IRQHandler, // 114: Reserved for Bluetooth LE/802.15.4 radio to MCU
|
||||
BLE_MCI_INT7_IRQHandler, // 115: Reserved for Bluetooth LE/802.15.4 radio to MCU
|
||||
PIN0_INT_IRQHandler, // 116: From AON GPIO
|
||||
PIN1_INT_IRQHandler, // 117: From AON GPIO
|
||||
ELS_IRQHandler, // 118: EdgeLock subsystem (ELS)
|
||||
ELS_GDET_IRQHandler, // 119: ELS IRQ line for GDET error
|
||||
ELS_GDET_UM_IRQHandler, // 120: ELS un-gated latched error
|
||||
PKC_INT_IRQHandler, // 121: Public key crypto-processor (PKC) interrupt
|
||||
PKC_ERR_IRQHandler, // 122: PKC error
|
||||
CDOG_INT_IRQHandler, // 123: Code watch dog timmer interrupt
|
||||
GAU_DAC_IRQHandler, // 124: General analog unit (GAU) digital to analog converter (DAC)
|
||||
GAU_ACOMP_WKUP_IRQHandler, // 125: GAU analog comparator (ACOMP) wake-up
|
||||
GAU_ACOMP_IRQHandler, // 126: GAU analog comparator
|
||||
GAU_ADC1_IRQHandler, // 127: GAU analog to digital converter 1 (ADC1)
|
||||
GAU_ADC0_IRQHandler, // 128: GAU analog to digital converter 0 (ADC0)
|
||||
USIM_IRQHandler, // 129: Universal subscriber identity module (USIM) interface
|
||||
OTP_IRQHandler, // 130: One time programmable (OTP) memory interrupt
|
||||
ENET_IRQHandler, // 131: Etheret interrupt
|
||||
ENET_TIMER_IRQHandler, // 132: Ethernet timer interrupt
|
||||
PMIP_IRQHandler, // 133: Power management IP (PMIP)
|
||||
PMIP_CHANGE_IRQHandler, // 134: PMIP change from 1 to 0
|
||||
ITRC_IRQHandler, // 135: Intrusion and tamper response controller (ITRC) interrupt request
|
||||
Reserved136_IRQHandler, // 136: Reserved interrupt
|
||||
Reserved137_IRQHandler, // 137: Reserved interrupt
|
||||
Reserved138_IRQHandler, // 138: Reserved interrupt
|
||||
TRNG_IRQHandler, // 139: TRNG interrupt request
|
||||
ACC_C_INT_IRQHandler, // 140: AHB memory access checker - Cortex-M33 code bus
|
||||
ACC_S_INT_IRQHandler, // 141: AHB memory access checker - Cortex-M33 sys bus
|
||||
WACC_IRQHandler, // 142: Wi-Fi accessed during power off
|
||||
BACC_IRQHandler, // 143: Bluetooth LE/802.15.4 radio accessed during power off
|
||||
GDMA_IRQHandler, // 144: General purpose direct memory access (GDMA) interrupt
|
||||
};
|
||||
|
||||
extern unsigned char _end[]; // End of data section, start of heap. See link.ld
|
||||
__attribute__((naked, noreturn)) void Reset_Handler(void) {
|
||||
__asm("cpsid i"); // Disable interrupts
|
||||
// Config VTOR & MSPLIM register
|
||||
__asm("LDR R0, =0xE000ED08 \n"
|
||||
"STR %0, [R0] \n"
|
||||
"LDR R1, [%0] \n"
|
||||
"MSR MSP, R1 \n"
|
||||
"MSR MSPLIM, %1 \n"
|
||||
:
|
||||
: "r"(tab), "r"(_end)
|
||||
: "r0", "r1");
|
||||
extern long _sbss, _ebss, _sdata, _edata, _sidata, _siram, _siiram, _eiram;
|
||||
for (long *dst = &_sbss; dst < &_ebss; dst++) *dst = 0;
|
||||
for (long *dst = &_sdata, *src = &_sidata; dst < &_edata;) *dst++ = *src++;
|
||||
for (long *dst = &_siram, *src = &_siiram; dst < &_eiram;) *dst++ = *src++;
|
||||
SystemInit();
|
||||
__asm("cpsie i"); // Reenable interrupts
|
||||
// Call main()
|
||||
extern void main(void);
|
||||
main();
|
||||
for (;;) (void) 0; // Infinite loop
|
||||
}
|
||||
|
||||
void SystemCoreClockUpdate (void) {
|
||||
|
||||
}
|
||||
|
||||
void Default_Handler(void) {
|
||||
for (;;) (void) 0;
|
||||
}
|
||||
Reference in new issue
Block a user