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Reorganized NXP examples
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robert committed
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../../../../mongoose.c
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../../../../mongoose.h
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#pragma once
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#define MG_ARCH MG_ARCH_ARMGCC // Use ARM toolchain
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#define MG_ENABLE_TCPIP 1 // Enable built-in network stack
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#define MG_ENABLE_DRIVER_IMXRT10 1
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#define MG_ENABLE_TCPIP_DRIVER_INIT 0
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#define MG_ENABLE_CUSTOM_MILLIS 1 // Let user implement mg_millis()
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#define MG_ENABLE_POSIX_FS 0 // Disable POSIX filesystem
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#define MG_OTA MG_OTA_RT1060 // Enable OTA
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#define MG_TLS MG_TLS_BUILTIN // Enable built-in TLS
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// Match Teensy's linker script - required for OTA to work
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#define MG_IRAM __attribute__((noinline, section(".fastrun")))
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// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
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// By default, those are set to zero, meaning that DHCP is used
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//
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// #define MG_TCPIP_IP MG_IPV4(192, 168, 0, 10)
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// #define MG_TCPIP_GW MG_IPV4(192, 168, 0, 1)
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// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0)
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// Set custom MAC address. By default, it is randomly generated
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// Using a build-time constant:
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// #define MG_SET_MAC_ADDRESS(mac) do { mac[0] = 2; mac[1] = 3; mac[2] = 4; mac[3] = 5; mac[4] = 6; mac[5] = 7; } while (0)
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//
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// Using custom function:
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// extern void my_function(unsigned char *mac);
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// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)
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// Construct MAC address from the MCU unique ID
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#define MG_OCOTP_FUSES ((volatile uint32_t *) 0x401f4410)
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#define MG_SET_MAC_ADDRESS(mac) \
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do { \
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mac[0] = 2; \
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mac[1] = (MG_OCOTP_FUSES[0] >> 0) & 255; \
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mac[2] = (MG_OCOTP_FUSES[0] >> 10) & 255; \
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mac[3] = ((MG_OCOTP_FUSES[0] >> 19) ^ (MG_OCOTP_FUSES[4] >> 19)) & 255; \
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mac[4] = (MG_OCOTP_FUSES[4] >> 10) & 255; \
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mac[5] = (MG_OCOTP_FUSES[4] >> 0) & 255; \
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} while (0)
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#include "mongoose.h"
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void ethernet_init(void);
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struct mg_mgr mgr;
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struct mg_tcpip_driver_imxrt_data data = {.mdc_cr = 24, .phy_addr = 0};
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struct mg_tcpip_if mif = {
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// Construct MAC address from the unique chip ID
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.mac = {2, (uint8_t) (HW_OCOTP_CFG0 & 255),
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(uint8_t) ((HW_OCOTP_CFG0 >> 10) & 255),
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(uint8_t) (((HW_OCOTP_CFG0 >> 19) ^ (HW_OCOTP_CFG1 >> 19)) & 255),
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(uint8_t) ((HW_OCOTP_CFG1 >> 10) & 255),
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(uint8_t) (HW_OCOTP_CFG1 & 255)},
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// The default is DHCP. Uncomment 3 lines below for static IP config:
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// .ip = mg_htonl(MG_U32(192, 168, 0, 223)),
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// .mask = mg_htonl(MG_U32(255, 255, 255, 0)),
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// .gw = mg_htonl(MG_U32(192, 168, 0, 1)),
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.driver = &mg_tcpip_driver_imxrt,
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.driver_data = &data};
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uint64_t mg_millis(void) { // Let Mongoose use our uptime function
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return millis();
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}
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static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) {
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if (ev == MG_EV_HTTP_MSG) { // New HTTP request received
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struct mg_http_message *hm = (struct mg_http_message *) ev_data;
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if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) {
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mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), mg_millis());
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} else {
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mg_http_reply(c, 200, "", "Hi from Mongoose, tick %llu\n",
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mg_millis());
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}
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}
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}
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void setup() {
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pinMode(LED_BUILTIN, OUTPUT);
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Serial.begin(115200);
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while (!Serial) delay(50);
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mg_mgr_init(&mgr); // Initialise Mongoose event manager
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mg_log_set(MG_LL_DEBUG); // Set log level and log function
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mg_log_set_fn([](char ch, void *) { Serial.print(ch); }, NULL);
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MG_INFO(("CPU %g MHz. Starting TCP/IP stack", (double) F_CPU / 1000000));
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ethernet_init();
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mg_tcpip_init(&mgr, &mif); // Initialise built-in TCP/IP stack
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MG_INFO(("Waiting for IP..."));
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while (mif.state != MG_TCPIP_STATE_READY) mg_mgr_poll(&mgr, 1);
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mg_http_listen(&mgr, "http://0.0.0.0:8000", http_ev_handler, NULL);
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}
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void loop() {
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static uint64_t timer;
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if (mg_timer_expired(&timer, 500, mg_millis())) { // Every 500ms
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digitalWrite(LED_BUILTIN, !digitalRead(LED_BUILTIN)); // blink an LED
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}
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mg_mgr_poll(&mgr, 1); // Process network events
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}
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extern "C" void ENET_IRQHandler(void);
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#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
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#define RMII_PAD_INPUT_PULLDOWN 0x30E9
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#define RMII_PAD_INPUT_PULLUP 0xB0E9
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#define RMII_PAD_CLOCK 0x0031
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// initialize the ethernet hardware
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void ethernet_init(void) {
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CCM_CCGR1 |= CCM_CCGR1_ENET(CCM_CCGR_ON);
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// configure PLL6 for 50 MHz, pg 1173
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CCM_ANALOG_PLL_ENET_CLR =
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CCM_ANALOG_PLL_ENET_POWERDOWN | CCM_ANALOG_PLL_ENET_BYPASS | 0x0F;
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CCM_ANALOG_PLL_ENET_SET = CCM_ANALOG_PLL_ENET_ENABLE |
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CCM_ANALOG_PLL_ENET_BYPASS
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/*| CCM_ANALOG_PLL_ENET_ENET2_REF_EN*/
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| CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN
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/*| CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(1)*/
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| CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
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while (!(CCM_ANALOG_PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK))
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; // wait for PLL lock
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CCM_ANALOG_PLL_ENET_CLR = CCM_ANALOG_PLL_ENET_BYPASS;
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// configure REFCLK to be driven as output by PLL6, pg 326
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CLRSET(IOMUXC_GPR_GPR1,
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IOMUXC_GPR_GPR1_ENET1_CLK_SEL | IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN,
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IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR);
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// Configure pins
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 5; // Reset B0_14 Alt5 GPIO7.15
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 5; // Power B0_15 Alt5 GPIO7.14
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GPIO7_GDIR |= (1 << 14) | (1 << 15);
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GPIO7_DR_SET = (1 << 15); // Power on
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GPIO7_DR_CLEAR = (1 << 14); // Reset PHY chip
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IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = RMII_PAD_INPUT_PULLDOWN; // PhyAdd[0] = 0
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IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = RMII_PAD_INPUT_PULLDOWN; // PhyAdd[1] = 1
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IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = RMII_PAD_INPUT_PULLUP; // Slave mode
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IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = RMII_PAD_INPUT_PULLDOWN; // Auto MDIX
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IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = RMII_PAD_INPUT_PULLUP;
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IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = RMII_PAD_INPUT_PULLUP;
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IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = RMII_PAD_INPUT_PULLUP;
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IOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = RMII_PAD_CLOCK;
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 3; // RXD1 B1_05 Alt3, pg 525
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 3; // RXD0 B1_04 Alt3, pg 524
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 6 | 0x10; // REFCLK B1_10 Alt6, pg 530
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 3; // RXER B1_11 Alt3, pg 531
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 3; // RXEN B1_06 Alt3, pg 526
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 3; // TXEN B1_09 Alt3, pg 529
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 3; // TXD0 B1_07 Alt3, pg 527
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 3; // TXD1 B1_08 Alt3, pg 528
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 0; // MDIO B1_15 Alt0, pg 535
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IOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 0; // MDC B1_14 Alt0, pg 534
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IOMUXC_ENET_MDIO_SELECT_INPUT = 2; // GPIO_B1_15_ALT0, pg 792
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IOMUXC_ENET0_RXDATA_SELECT_INPUT = 1; // GPIO_B1_04_ALT3, pg 792
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IOMUXC_ENET1_RXDATA_SELECT_INPUT = 1; // GPIO_B1_05_ALT3, pg 793
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IOMUXC_ENET_RXEN_SELECT_INPUT = 1; // GPIO_B1_06_ALT3, pg 794
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IOMUXC_ENET_RXERR_SELECT_INPUT = 1; // GPIO_B1_11_ALT3, pg 795
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IOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 1; // GPIO_B1_10_ALT6, pg 791
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delay(1);
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GPIO7_DR_SET = (1 << 14); // Start PHY chip
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// ENET_MSCR = ENET_MSCR_MII_SPEED(9);
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delay(1);
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// Setup IRQ handler
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attachInterruptVector(IRQ_ENET, ENET_IRQHandler);
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NVIC_ENABLE_IRQ(IRQ_ENET);
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}
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