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Create MG_ARCH_FREERTOS, MG_ENABLE_LWIP, MG_ENABLE_FREERTOS_TCP. Remove MG_ARCH_FREERTOS_TCP, MG_ARCH_RTX_LWIP

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cpq committed 2022-11-07 23:58:58 +00:00
1 parent 095cdcd69e
commit 2192914cbb
20 files changed
+348 -417
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examples/stm32/nucleo-f429zi-baremetal/mcu.h
+11 -9
View File
@@ -22,7 +22,7 @@ enum { APB1_PRE = 5 /* AHB clock / 4 */, APB2_PRE = 4 /* AHB clock / 2 */ };
enum { PLL_HSI = 16, PLL_M = 8, PLL_N = 180, PLL_P = 2 }; // Run at 180 Mhz
//#define PLL_FREQ PLL_HSI
#define PLL_FREQ (PLL_HSI * PLL_N / PLL_M / PLL_P)
#define FLASH_LATENCY 5
#define FLASH_LATENCY 5
#define FREQ (PLL_FREQ * 1000000)
static inline void spin(volatile uint32_t count) {
@@ -175,9 +175,10 @@ static inline void uart_init(struct uart *uart, unsigned long baud) {
gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
uart->CR1 = 0; // Disable this UART
uart->BRR = FREQ / 4 / baud; // Baud rate x16 (with 4dp), "4" is APBx prescaler, different from APBx_PRE
// TODO(): make this configurable ?
uart->CR1 = 0; // Disable this UART
uart->BRR = FREQ / APB2_PRE / baud; // Baud rate x16 (with 4dp), "4" is APBx
// prescaler, different from APBx_PRE
// TODO(): make this configurable ?
uart->CR1 |= BIT(13) | BIT(2) | BIT(3); // Set UE, RE, TE
}
static inline void uart_write_byte(struct uart *uart, uint8_t byte) {
@@ -194,12 +195,13 @@ static inline uint8_t uart_read_byte(struct uart *uart) {
return (uint8_t) (uart->DR & 255);
}
static inline void clock_init(void) { // Set clock frequency
static inline void clock_init(void) { // Set clock frequency
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
asm ("DSB");
asm ("ISB");
FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch, Icache, Dcache
RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers
asm("DSB");
asm("ISB");
FLASH->ACR |= FLASH_LATENCY | BIT(8) |
BIT(9); // Flash latency, prefetch, Icache, Dcache
RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers
RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P
RCC->PLLCFGR |= PLL_M | (PLL_N << 6); // Set PLL_M and PLL_N
RCC->CR |= BIT(24); // Enable PLL
examples/stm32/stm32-freertos-tcp/Makefile
+1 -1
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@@ -6,7 +6,7 @@ DOCKER ?= docker run --rm -v $(PROJECT_ROOT_PATH):$(PROJECT_ROOT_PATH) -w $(CURD
FREERTOS_KERNEL_PATH ?= $(PROJECT_ROOT_PATH)/test/freertos-kernel
FREERTOS_PLUS_TCP_PATH ?= $(PROJECT_ROOT_PATH)/test/freertos-tcp
MONGOOSE_FLAGS = -DMG_ARCH=MG_ARCH_FREERTOS_TCP
MONGOOSE_FLAGS = -DMG_ARCH=MG_ARCH_FREERTOS -DMG_ENABLE_FREERTOS_TCP -DMG_ENABLE_FILE=0
MCU_FLAGS = -mcpu=cortex-m7 -mthumb -mfloat-abi=softfp -mfpu=vfpv4
#-mcpu=cortex-m7 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard