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stm32 examples revamp
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@@ -0,0 +1,29 @@
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# STM32H573I-DK Mongoose Integration
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This guide explains how to bring up a production-grade Web UI dashboard on the
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STM32H573I-DK development board.
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A pre-configured, ready-to-run project zip is available for download at
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https://mongoose.ws.
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To integrate the Web UI dashboard into an existing CubeMX project, or to create a
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new project from scratch:
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1. Configure the peripherals (described below).
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2. Regenerate your project code and integrate Mongoose core by following
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https://mongoose.ws/docs/guides/stm32-tcpip-stack/.
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3. Add the Web UI dashboard by following
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https://mongoose.ws/docs/guides/web-dashboard-guide/.
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## Configure peripherals
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An `.ioc` file is included in this directory for your reference. It was created
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using the following steps:
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- Open CubeMX. If you are starting a new project, select the STM32H573I
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microcontroller and create a new project.
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- In Clock Configuration, set the maximum clock frequency to 250 MHz.
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- In Pinout & Configuration / Connectivity, enable USART1 in asynchronous mode.
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Configure pins PA9 and PA10 for USART.
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- In Pinout & Configuration / Connectivity, enable ETH in RMII mode and set pins
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PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG12, and PG13 for Ethernet.
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@@ -0,0 +1,237 @@
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#MicroXplorer Configuration settings - do not modify
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CAD.formats=
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CAD.pinconfig=
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CAD.provider=
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CORTEX_M33_NS.userName=CORTEX_M33
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ETH.IPParameters=MediaInterface
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ETH.MediaInterface=HAL_ETH_RMII_MODE
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File.Version=6
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GPIO.groupedBy=
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KeepUserPlacement=false
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MMTAppRegionsCount=0
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MMTConfigApplied=false
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MMTSectionSuffix=
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Mcu.CPN=STM32H573IIK3Q
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Mcu.ContextProject=TrustZoneDisabled
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Mcu.Family=STM32H5
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Mcu.IP0=BOOTPATH
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Mcu.IP1=CORTEX_M33_NS
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Mcu.IP2=ETH
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Mcu.IP3=MEMORYMAP
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Mcu.IP4=NVIC
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Mcu.IP5=PWR
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Mcu.IP6=RCC
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Mcu.IP7=RNG
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Mcu.IP8=SYS
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Mcu.IP9=USART1
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Mcu.IPNb=10
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Mcu.Name=STM32H573IIKxQ
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Mcu.Package=UFBGA176
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Mcu.Pin0=PG12
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Mcu.Pin1=PG13
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Mcu.Pin10=PA7
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Mcu.Pin11=VP_CORTEX_M33_NS_VS_Hclk
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Mcu.Pin12=VP_PWR_VS_SECSignals
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Mcu.Pin13=VP_PWR_VS_LPOM
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Mcu.Pin14=VP_RNG_VS_RNG
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Mcu.Pin15=VP_SYS_VS_Systick
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Mcu.Pin16=VP_BOOTPATH_VS_BOOTPATH
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Mcu.Pin17=VP_MEMORYMAP_VS_MEMORYMAP
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Mcu.Pin2=PG11
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Mcu.Pin3=PA10
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Mcu.Pin4=PA9
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Mcu.Pin5=PC1
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Mcu.Pin6=PA1
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Mcu.Pin7=PA2
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Mcu.Pin8=PC4
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Mcu.Pin9=PC5
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Mcu.PinsNb=18
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Mcu.ThirdPartyNb=0
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Mcu.UserConstants=
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Mcu.UserName=STM32H573IIKxQ
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MxCube.Version=6.17.0
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MxDb.Version=DB.6.0.170
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NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.ETH_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
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NVIC.ForceEnableDMAVector=true
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NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
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NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
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NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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PA1.Mode=RMII
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PA1.Signal=ETH_REF_CLK
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PA10.Locked=true
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PA10.Mode=Asynchronous
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PA10.Signal=USART1_RX
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PA2.Mode=RMII
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PA2.Signal=ETH_MDIO
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PA7.Mode=RMII
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PA7.Signal=ETH_CRS_DV
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PA9.Locked=true
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PA9.Mode=Asynchronous
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PA9.Signal=USART1_TX
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PC1.Mode=RMII
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PC1.Signal=ETH_MDC
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PC4.Mode=RMII
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PC4.Signal=ETH_RXD0
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PC5.Mode=RMII
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PC5.Signal=ETH_RXD1
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PCC.Checker=false
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PCC.Display=Plot\: All Steps
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PCC.Line=STM32H563/H573
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PCC.MCU=STM32H573IIKxQ
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PCC.PartNumber=STM32H573IIKxQ
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PCC.Series=STM32H5
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PCC.Temperature=25
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PCC.Vdd=3.0
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PG11.Mode=RMII
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PG11.Signal=ETH_TX_EN
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PG12.Locked=true
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PG12.Mode=RMII
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PG12.Signal=ETH_TXD1
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PG13.Mode=RMII
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PG13.Signal=ETH_TXD0
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PinOutPanel.CurrentBGAView=Top
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PinOutPanel.RotationAngle=0
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ProjectManager.AskForMigrate=true
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ProjectManager.BackupPrevious=false
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ProjectManager.CompilerLinker=GCC
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ProjectManager.CompilerOptimize=6
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ProjectManager.ComputerToolchain=false
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ProjectManager.CoupleFile=false
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ProjectManager.CustomerFirmwarePackage=
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ProjectManager.DefaultFWLocation=true
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ProjectManager.DeletePrevious=true
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ProjectManager.DeviceId=STM32H573IIKxQ
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ProjectManager.FirmwarePackage=STM32Cube FW_H5 V1.6.0
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ProjectManager.FreePins=false
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ProjectManager.FreePinsContext=
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ProjectManager.HalAssertFull=false
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ProjectManager.HeapSize=0x10000
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ProjectManager.KeepUserCode=true
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ProjectManager.LastFirmware=true
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ProjectManager.LibraryCopy=1
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ProjectManager.MainLocation=Core/Src
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ProjectManager.NoMain=false
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ProjectManager.PreviousToolchain=STM32CubeIDE
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ProjectManager.ProjectBuild=false
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ProjectManager.ProjectFileName=h573.ioc
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ProjectManager.ProjectName=h573
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ProjectManager.ProjectStructure=
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ProjectManager.RegisterCallBack=
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ProjectManager.StackSize=0x2000
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ProjectManager.TargetToolchain=CMake
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ProjectManager.ToolChainLocation=
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ProjectManager.UAScriptAfterPath=
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ProjectManager.UAScriptBeforePath=
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ProjectManager.UnderRoot=false
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ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ETH_Init-ETH-false-HAL-true,4-MX_RNG_Init-RNG-false-HAL-true,5-MX_USART1_UART_Init-USART1-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true
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RCC.ADCFreq_Value=250000000
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RCC.AHBFreq_Value=250000000
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RCC.APB1Freq_Value=250000000
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RCC.APB1TimFreq_Value=250000000
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RCC.APB2Freq_Value=250000000
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RCC.APB2TimFreq_Value=250000000
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RCC.APB3Freq_Value=250000000
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RCC.CECFreq_Value=32000
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RCC.CKPERFreq_Value=32000000
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RCC.CRSFreq_Value=48000000
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RCC.CSI_VALUE=4000000
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RCC.CortexFreq_Value=250000000
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RCC.DACFreq_Value=32768
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RCC.EPOD_VALUE=4000000
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RCC.ETHFreq_Value=250000000
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RCC.FCLKCortexFreq_Value=250000000
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RCC.FDCANFreq_Value=25000000
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RCC.FamilyName=M
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RCC.HCLKFreq_Value=250000000
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RCC.HSE_VALUE=25000000
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RCC.HSI48_VALUE=48000000
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RCC.HSI_VALUE=64000000
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RCC.I2C1Freq_Value=250000000
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RCC.I2C2Freq_Value=250000000
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RCC.I2C3Freq_Value=250000000
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RCC.I2C4Freq_Value=250000000
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RCC.I3C1Freq_Value=250000000
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RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CECFreq_Value,CKPERFreq_Value,CRSFreq_Value,CSI_VALUE,CortexFreq_Value,DACFreq_Value,EPOD_VALUE,ETHFreq_Value,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I3C1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPTIM4Freq_Value,LPTIM5Freq_Value,LPTIM6Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSIRC_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,OCTOSPIMFreq_Value,PLL2FRACN,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3FRACN,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLFRACN,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1Freq_Value,SDMMC2Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SPI5Freq_Value,SPI6Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART12Freq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,UART9Freq_Value,UCPD1outputFreq_Value,USART10Freq_Value,USART11Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value
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RCC.LPTIM1Freq_Value=250000000
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RCC.LPTIM2Freq_Value=250000000
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RCC.LPTIM3Freq_Value=250000000
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RCC.LPTIM4Freq_Value=250000000
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RCC.LPTIM5Freq_Value=250000000
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RCC.LPTIM6Freq_Value=250000000
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RCC.LPUART1Freq_Value=250000000
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RCC.LSCOPinFreq_Value=32000
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RCC.LSE_VALUE=32768
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RCC.LSIRC_VALUE=32000
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RCC.MCO1PinFreq_Value=32000000
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RCC.MCO2PinFreq_Value=250000000
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RCC.OCTOSPIMFreq_Value=250000000
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RCC.PLL2FRACN=0
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RCC.PLL2PoutputFreq_Value=258000000
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RCC.PLL2QoutputFreq_Value=258000000
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RCC.PLL2RoutputFreq_Value=258000000
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RCC.PLL3FRACN=0
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RCC.PLL3PoutputFreq_Value=258000000
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RCC.PLL3QoutputFreq_Value=258000000
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RCC.PLL3RoutputFreq_Value=258000000
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RCC.PLLFRACN=0
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RCC.PLLN=125
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RCC.PLLPoutputFreq_Value=250000000
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RCC.PLLQoutputFreq_Value=250000000
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RCC.PWRFreq_Value=250000000
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RCC.RNGFreq_Value=48000000
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RCC.SAI1Freq_Value=258000000
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RCC.SAI2Freq_Value=258000000
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RCC.SDMMC1Freq_Value=250000000
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RCC.SDMMC2Freq_Value=250000000
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RCC.SPI1Freq_Value=250000000
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RCC.SPI2Freq_Value=250000000
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RCC.SPI3Freq_Value=250000000
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RCC.SPI4Freq_Value=250000000
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RCC.SPI5Freq_Value=250000000
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RCC.SPI6Freq_Value=250000000
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RCC.SYSCLKFreq_VALUE=250000000
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RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
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RCC.UART12Freq_Value=250000000
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RCC.UART4Freq_Value=250000000
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RCC.UART5Freq_Value=250000000
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RCC.UART7Freq_Value=250000000
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RCC.UART8Freq_Value=250000000
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RCC.UART9Freq_Value=250000000
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RCC.UCPD1outputFreq_Value=8000000
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RCC.USART10Freq_Value=250000000
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RCC.USART11Freq_Value=250000000
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RCC.USART1Freq_Value=250000000
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RCC.USART2Freq_Value=250000000
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RCC.USART3Freq_Value=250000000
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RCC.USART6Freq_Value=250000000
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RCC.USBFreq_Value=48000000
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RCC.VCOInput2Freq_Value=4000000
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RCC.VCOInput3Freq_Value=4000000
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RCC.VCOInputFreq_Value=4000000
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RCC.VCOOutputFreq_Value=500000000
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RCC.VCOPLL2OutputFreq_Value=516000000
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RCC.VCOPLL3OutputFreq_Value=516000000
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USART1.IPParameters=VirtualMode-Asynchronous
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USART1.VirtualMode-Asynchronous=VM_ASYNC
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VP_BOOTPATH_VS_BOOTPATH.Mode=BP_Activate
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||||
VP_BOOTPATH_VS_BOOTPATH.Signal=BOOTPATH_VS_BOOTPATH
|
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VP_CORTEX_M33_NS_VS_Hclk.Mode=Hclk_Mode
|
||||
VP_CORTEX_M33_NS_VS_Hclk.Signal=CORTEX_M33_NS_VS_Hclk
|
||||
VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg
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VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP
|
||||
VP_PWR_VS_LPOM.Mode=PowerOptimisation
|
||||
VP_PWR_VS_LPOM.Signal=PWR_VS_LPOM
|
||||
VP_PWR_VS_SECSignals.Mode=Security/Privilege
|
||||
VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals
|
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VP_RNG_VS_RNG.Mode=RNG_Activate
|
||||
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
|
||||
VP_SYS_VS_Systick.Mode=SysTick
|
||||
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
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board=custom
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@@ -0,0 +1,39 @@
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||||
# Copyright (c) 2026 Cesanta Software Limited
|
||||
# Environment setup: https://mongoose.ws/docs/getting-started/build-environment/
|
||||
|
||||
CFLAGS = -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion
|
||||
CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
|
||||
CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
|
||||
CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_h5/Include -Imongoose
|
||||
CFLAGS += -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard $(CFLAGS_EXTRA)
|
||||
LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nosys.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
|
||||
|
||||
SOURCES = main.c hal.c
|
||||
SOURCES += cmsis_h5/Source/Templates/gcc/startup_stm32h573xx.s
|
||||
SOURCES += mongoose/mongoose.c
|
||||
|
||||
|
||||
all build example: firmware.bin
|
||||
|
||||
mongoose/mongoose.c mongoose/mongoose.h:
|
||||
cp ../../../../mongoose.[ch] mongoose/
|
||||
|
||||
firmware.elf: cmsis_core cmsis_h5 hal.h link.ld Makefile $(SOURCES) mongoose/mongoose.h
|
||||
arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(CFLAGS_EXTRA) $(LDFLAGS) -o $@
|
||||
|
||||
firmware.bin: firmware.elf
|
||||
arm-none-eabi-objcopy -O binary $< $@
|
||||
@echo
|
||||
@echo "To flash, run 'make flash', or use STM32CubeProgrammer"
|
||||
|
||||
flash: firmware.bin
|
||||
STM32_Programmer_CLI -c port=swd -e all -w firmware.elf -hardRst
|
||||
|
||||
cmsis_core:
|
||||
git clone -q -c advice.detachedHead=false --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
|
||||
|
||||
cmsis_h5:
|
||||
git clone -q -c advice.detachedHead=false --depth 1 -b v1.2.0 https://github.com/STMicroelectronics/cmsis_device_h5 $@
|
||||
|
||||
clean:
|
||||
rm -rf firmware.* cmsis_* mongoose/mongoose.*
|
||||
@@ -0,0 +1,125 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now) {
|
||||
uint64_t diff = now - *t; // Wrap-safe elapsed time since last expiry
|
||||
if (period == 0) return false; // Avoid division by zero
|
||||
if (diff < period) return false; // Period has not elapsed yet
|
||||
*t += (diff / period) * period; // Preserve cadence, skip missed periods
|
||||
return true;
|
||||
}
|
||||
|
||||
static volatile uint64_t s_ticks; // Milliseconds since boot
|
||||
void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
|
||||
s_ticks++;
|
||||
}
|
||||
|
||||
uint64_t hal_get_tick(void) {
|
||||
return s_ticks;
|
||||
};
|
||||
|
||||
uint32_t SystemCoreClock = SYS_FREQUENCY;
|
||||
void SystemInit(void) { // Called automatically by startup code
|
||||
hal_system_init(); // Enable FPU
|
||||
hal_clock_init();
|
||||
SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
|
||||
}
|
||||
|
||||
void ExitRun0Mode(void) {
|
||||
}
|
||||
|
||||
struct stat;
|
||||
__attribute__((weak)) int _fstat(int fd, struct stat *st) {
|
||||
(void) fd, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
extern unsigned char _end[]; // End of data section, start of heap. See link.ld
|
||||
static unsigned char *s_current_heap_end = _end;
|
||||
|
||||
size_t hal_ram_used(void) {
|
||||
return (size_t) (s_current_heap_end - _end);
|
||||
}
|
||||
|
||||
size_t hal_ram_free(void) {
|
||||
unsigned char endofstack;
|
||||
return (size_t) (&endofstack - s_current_heap_end);
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
unsigned char *prev_heap;
|
||||
unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
|
||||
prev_heap = s_current_heap_end;
|
||||
// Check how much space we got from the heap end to the stack end
|
||||
if (s_current_heap_end + incr > heap_end) return (void *) -1;
|
||||
s_current_heap_end += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int mkdir(const char *path, int mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _init(void) {
|
||||
}
|
||||
@@ -0,0 +1,203 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// https://www.st.com/resource/en/reference_manual/dm00031020-stm32f405-415-stm32f407-417-stm32f427-437-and-stm32f429-439-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
|
||||
// https://www.st.com/resource/en/datasheet/stm32f429zi.pdf
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stm32h573xx.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
|
||||
extern bool hal_timer_expired(volatile uint64_t *t, uint64_t prd, uint64_t now);
|
||||
extern uint64_t hal_get_tick(void);
|
||||
extern size_t hal_ram_free(void);
|
||||
extern size_t hal_ram_used(void);
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
#define HAL_ETH_PINS \
|
||||
PIN('A', 1), /* ETH_REF_CLK */ \
|
||||
PIN('A', 2), /* ETH_MDIO */ \
|
||||
PIN('A', 7), /* ETH_CRS_DV */ \
|
||||
PIN('C', 1), /* ETH_MDC */ \
|
||||
PIN('C', 4), /* ETH_RXD0 */ \
|
||||
PIN('C', 5), /* ETH_RXD1 */ \
|
||||
PIN('G', 11), /* ETH_TX_EN */ \
|
||||
PIN('G', 12), /* ETH_TXD1 */ \
|
||||
PIN('G', 13) /* ETH_TXD0 */
|
||||
|
||||
#define BIT(x) (1UL << (x))
|
||||
#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
|
||||
#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
|
||||
#define PINNO(pin) (pin & 255)
|
||||
#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
void hal_init(void);
|
||||
size_t hal_ram_free(void);
|
||||
size_t hal_ram_used(void);
|
||||
|
||||
// System clock (11.4, Figure 48; 11.4.5, Figure 51; 11.4.8
|
||||
// SYS_FREQUENCY <= 250 MHz; (SYS_FREQUENCY / HPRE) ; hclk = SYS_FREQUENCY
|
||||
// APB clocks <= 250 MHz. Configure flash latency (WS) in accordance to hclk
|
||||
// freq (7.3.4, Table 37)
|
||||
enum {
|
||||
HAL_HPRE = 7, // register value, divisor value = BIT(value - 7) = / 1
|
||||
HAL_PPRE1 = 4, // register values, divisor value = BIT(value - 3) = / 2
|
||||
HAL_PPRE2 = 4,
|
||||
HAL_PPRE3 = 4,
|
||||
};
|
||||
// Make sure your chip package uses the internal LDO, otherwise set PLL1_N = 200
|
||||
enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 250, PLL1_P = 2 };
|
||||
#define SYS_FREQUENCY \
|
||||
((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / (BIT(HAL_HPRE - 7))) * 1000000)
|
||||
#define AHB_FREQUENCY SYS_FREQUENCY
|
||||
#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(HAL_PPRE2 - 3)))
|
||||
#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(HAL_PPRE1 - 3)))
|
||||
|
||||
static inline void spin(volatile uint32_t n) {
|
||||
while (n--) (void) 0;
|
||||
}
|
||||
|
||||
enum { HAL_GPIO_MODE_INPUT, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_MODE_AF, HAL_GPIO_MODE_ANALOG };
|
||||
enum { HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_OTYPE_OPEN_DRAIN };
|
||||
enum { HAL_GPIO_SPEED_LOW, HAL_GPIO_SPEED_MEDIUM, HAL_GPIO_SPEED_HIGH, HAL_GPIO_SPEED_INSANE };
|
||||
enum { HAL_GPIO_PULL_NONE, HAL_GPIO_PULL_UP, HAL_GPIO_PULL_DOWN };
|
||||
|
||||
#define HAL_GPIO(N) ((GPIO_TypeDef *) ((GPIOA_BASE_NS) + 0x400 * (N)))
|
||||
|
||||
static GPIO_TypeDef *hal_gpio_bank(uint16_t pin) {
|
||||
return HAL_GPIO(PINBANK(pin));
|
||||
}
|
||||
static inline void hal_gpio_toggle(uint16_t pin) {
|
||||
GPIO_TypeDef *gpio = hal_gpio_bank(pin);
|
||||
uint32_t mask = BIT(PINNO(pin));
|
||||
gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
|
||||
}
|
||||
static inline int hal_gpio_read(uint16_t pin) {
|
||||
return hal_gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
|
||||
}
|
||||
static inline void hal_gpio_write(uint16_t pin, bool val) {
|
||||
GPIO_TypeDef *gpio = hal_gpio_bank(pin);
|
||||
gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
|
||||
}
|
||||
static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
uint8_t speed, uint8_t pull, uint8_t af) {
|
||||
GPIO_TypeDef *gpio = hal_gpio_bank(pin);
|
||||
uint8_t n = (uint8_t) (PINNO(pin));
|
||||
RCC->AHB2ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
|
||||
CLRSET(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
|
||||
CLRSET(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
|
||||
CLRSET(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
|
||||
CLRSET(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
|
||||
((uint32_t) af) << ((n & 7) * 4));
|
||||
CLRSET(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
|
||||
}
|
||||
static inline void hal_gpio_input(uint16_t pin) {
|
||||
hal_gpio_init(pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH,
|
||||
HAL_GPIO_PULL_NONE, 0);
|
||||
}
|
||||
static inline void hal_gpio_output(uint16_t pin) {
|
||||
hal_gpio_init(pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH,
|
||||
HAL_GPIO_PULL_NONE, 0);
|
||||
}
|
||||
|
||||
static inline bool hal_uart_init(USART_TypeDef *uart, uint16_t tx,
|
||||
uint16_t rx, unsigned long baud) {
|
||||
uint8_t af = 7; // Alternate function
|
||||
uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
|
||||
|
||||
if (uart == USART1) {
|
||||
freq = APB2_FREQUENCY, RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
|
||||
} else if (uart == USART2) {
|
||||
freq = APB1_FREQUENCY, RCC->APB1LENR |= RCC_APB1LENR_USART2EN;
|
||||
} else if (uart == USART3) {
|
||||
freq = APB1_FREQUENCY, RCC->APB1LENR |= RCC_APB1LENR_USART3EN;
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
hal_gpio_init(tx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af);
|
||||
hal_gpio_init(rx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af);
|
||||
uart->CR1 = 0; // Disable UART
|
||||
uart->BRR = freq / baud; // Set baud rate
|
||||
uart->CR1 = USART_CR1_RE | USART_CR1_TE; // Set mode to TX & RX
|
||||
uart->CR1 |= USART_CR1_UE; // Enable UART
|
||||
return true;
|
||||
}
|
||||
static inline void hal_uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
|
||||
uart->TDR = byte;
|
||||
while ((uart->ISR & BIT(7)) == 0) spin(1);
|
||||
}
|
||||
static inline void hal_uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) hal_uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int hal_uart_read_ready(USART_TypeDef *uart) {
|
||||
return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
|
||||
}
|
||||
static inline uint8_t hal_uart_read_byte(USART_TypeDef *uart) {
|
||||
return (uint8_t) (uart->RDR & 255);
|
||||
}
|
||||
|
||||
static inline void hal_rng_init(void) {
|
||||
RCC->CCIPR5 |= RCC_CCIPR5_RNGSEL_0; // RNG clock source pll1_q_ck
|
||||
RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; // Enable RNG clock
|
||||
RNG->CR |= RNG_CR_RNGEN; // Enable RNG
|
||||
}
|
||||
static inline uint32_t hal_rng_read(void) {
|
||||
while ((RNG->SR & RNG_SR_DRDY) == 0) spin(1);
|
||||
return RNG->DR;
|
||||
}
|
||||
|
||||
static inline bool hal_ldo_is_on(void) {
|
||||
return (PWR->SCCR & PWR_SCCR_LDOEN) == PWR_SCCR_LDOEN;
|
||||
}
|
||||
|
||||
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
|
||||
static inline void hal_ethernet_init(void) {
|
||||
// Initialise Ethernet. Enable MAC GPIO pins, see UM3115 section 10.7
|
||||
uint16_t pins[] = {HAL_ETH_PINS};
|
||||
for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
|
||||
hal_gpio_init(pins[i], HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_INSANE,
|
||||
HAL_GPIO_PULL_NONE, 11); // 11 is the Ethernet function
|
||||
}
|
||||
NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
|
||||
RCC->APB3ENR |= RCC_APB3ENR_SBSEN; // Enable SBS clock
|
||||
CLRSET(SBS->PMCR, SBS_PMCR_ETH_SEL_PHY, SBS_PMCR_ETH_SEL_PHY_2); // RMII
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_ETHEN | RCC_AHB1ENR_ETHRXEN | RCC_AHB1ENR_ETHTXEN;
|
||||
}
|
||||
|
||||
static inline void hal_system_init(void) {
|
||||
SCB->CPACR |= ((3UL << 20U) | (3UL << 22U)); // Enable FPU
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
static inline void hal_clock_init(void) {
|
||||
// Set flash latency. RM0481, section 7.11.1, section 7.3.4 table 37
|
||||
CLRSET(FLASH->ACR, (FLASH_ACR_WRHIGHFREQ_Msk | FLASH_ACR_LATENCY_Msk),
|
||||
FLASH_ACR_LATENCY_5WS | FLASH_ACR_WRHIGHFREQ_1);
|
||||
|
||||
if (hal_ldo_is_on()) {
|
||||
PWR->VOSCR = PWR_VOSCR_VOS_0 | PWR_VOSCR_VOS_1; // Select VOS0
|
||||
} else {
|
||||
PWR->VOSCR = PWR_VOSCR_VOS_1; // Select VOS1
|
||||
}
|
||||
uint32_t f = PWR->VOSCR; // fake read to wait for bus clocking
|
||||
while ((PWR->VOSSR & PWR_VOSSR_ACTVOSRDY) == 0) spin(1);
|
||||
(void) f;
|
||||
RCC->CR = RCC_CR_HSION; // Clear HSI clock divisor
|
||||
while ((RCC->CR & RCC_CR_HSIRDY) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR2 = (HAL_PPRE3 << 12) | (HAL_PPRE2 << 8) | (HAL_PPRE1 << 4) | (HAL_HPRE << 0);
|
||||
RCC->PLL1DIVR =
|
||||
((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0); // Set PLL1_P PLL1_N
|
||||
// Enable P and Q divider outputs; set PLL1_M, select HSI as source,
|
||||
// !PLL1VCOSEL, PLL1RGE=0
|
||||
RCC->PLL1CFGR =
|
||||
RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1PEN | (PLL1_M << 8) | (1 << 0);
|
||||
RCC->CR |= RCC_CR_PLL1ON; // Enable PLL1
|
||||
while ((RCC->CR & RCC_CR_PLL1RDY) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR1 |= (3 << 0); // Set clock source to PLL1
|
||||
while ((RCC->CFGR1 & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
|
||||
}
|
||||
@@ -0,0 +1,30 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k
|
||||
sram(rwx) : ORIGIN = 0x20000000, LENGTH = 640k
|
||||
}
|
||||
_estack = ORIGIN(sram) + LENGTH(sram); /* End of RAM. stack points here */
|
||||
|
||||
SECTIONS {
|
||||
.vectors : { KEEP(*(.isr_vector)) } > flash
|
||||
.text : { *(.text* .text.*) } > flash
|
||||
.rodata : { *(.rodata*) } > flash
|
||||
|
||||
.data : {
|
||||
_sdata = .;
|
||||
*(.first_data)
|
||||
*(.ram)
|
||||
*(.data SORT(.data.*))
|
||||
_edata = .;
|
||||
} > sram AT > flash
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : {
|
||||
_sbss = .;
|
||||
*(.bss SORT(.bss.*) COMMON)
|
||||
_ebss = .;
|
||||
} > sram
|
||||
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
}
|
||||
@@ -0,0 +1,78 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "mongoose.h"
|
||||
#include "hal.h"
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG USART1
|
||||
#define UART_DEBUG_TX_PIN PIN('A', 9)
|
||||
#define UART_DEBUG_RX_PIN PIN('A', 10)
|
||||
#else
|
||||
#define UART_DEBUG_TX_PIN PIN('A', 9)
|
||||
#define UART_DEBUG_RX_PIN PIN('A', 10)
|
||||
#endif
|
||||
|
||||
#define LED1 PIN('I', 9) // On-board LED pin (green)
|
||||
#define LED2 PIN('I', 8) // On-board LED pin (orange)
|
||||
#define LED3 PIN('F', 1) // On-board LED pin (red)
|
||||
|
||||
// Redirect stdout debug output to UART
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
if (fd == 1 || fd == 2) hal_uart_write_buf(UART_DEBUG, ptr, (size_t) len);
|
||||
return len;
|
||||
}
|
||||
|
||||
static void blink_task(void) {
|
||||
static uint64_t blink_timer = 0;
|
||||
if (hal_timer_expired(&blink_timer, 500, hal_get_tick())) {
|
||||
hal_gpio_toggle(LED1);
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t mg_millis(void) {
|
||||
return hal_get_tick();
|
||||
}
|
||||
|
||||
bool mg_random(void *buf, size_t len) {
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = hal_rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) {
|
||||
if (ev == MG_EV_HTTP_MSG) { // New HTTP request received
|
||||
struct mg_http_message *hm = (struct mg_http_message *) ev_data;
|
||||
if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) {
|
||||
mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), hal_get_tick());
|
||||
} else {
|
||||
mg_http_reply(c, 200, "", "Hi from Mongoose, tick %llu\n",
|
||||
hal_get_tick());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
hal_clock_init();
|
||||
hal_rng_init();
|
||||
hal_gpio_output(LED1);
|
||||
hal_gpio_output(LED2);
|
||||
hal_gpio_output(LED3);
|
||||
hal_uart_init(UART_DEBUG, UART_DEBUG_TX_PIN, UART_DEBUG_RX_PIN, 115200);
|
||||
|
||||
hal_ethernet_init();
|
||||
|
||||
// Start a minimal web server
|
||||
struct mg_mgr mgr;
|
||||
mg_mgr_init(&mgr);
|
||||
mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL);
|
||||
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
blink_task();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,23 @@
|
||||
#pragma once
|
||||
|
||||
#define MG_ARCH MG_ARCH_ARMGCC
|
||||
#define MG_TLS MG_TLS_BUILTIN
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_DRIVER_STM32H 1
|
||||
#define MG_OTA MG_OTA_STM32H5
|
||||
|
||||
// Construct MAC address from the MCU unique ID. It is defined in the
|
||||
// ST CMSIS header as UID_BASE
|
||||
#define MGUID ((uint32_t *) 0x1FFF7A10) // Unique 96-bit chip ID
|
||||
#define MG_SET_MAC_ADDRESS(mac) \
|
||||
do { \
|
||||
mac[0] = 2; \
|
||||
mac[1] = MGUID[0] & 255; \
|
||||
mac[2] = (MGUID[0] >> 10) & 255; \
|
||||
mac[3] = (MGUID[0] >> 19) & 255; \
|
||||
mac[4] = MGUID[1] & 255; \
|
||||
mac[5] = MGUID[2] & 255; \
|
||||
} while (0)
|
||||
Reference in new issue
Block a user