From 42c1bee8eaf1f0d492241183efc27577485c68b0 Mon Sep 17 00:00:00 2001 From: "Sergio R. Caprile" Date: Mon, 29 Aug 2022 15:15:48 -0300 Subject: [PATCH] Add baremetal example on Nucleo-F429ZI --- .../stm32/nucleo-f429zi-baremetal/Makefile | 42 ++++ .../stm32/nucleo-f429zi-baremetal/README.md | 36 +++ examples/stm32/nucleo-f429zi-baremetal/boot.c | 162 +++++++++++++ .../stm32/nucleo-f429zi-baremetal/link.ld | 29 +++ examples/stm32/nucleo-f429zi-baremetal/main.c | 82 +++++++ examples/stm32/nucleo-f429zi-baremetal/mcu.h | 217 ++++++++++++++++++ .../stm32/nucleo-f429zi-baremetal/syscalls.c | 83 +++++++ 7 files changed, 651 insertions(+) create mode 100644 examples/stm32/nucleo-f429zi-baremetal/Makefile create mode 100644 examples/stm32/nucleo-f429zi-baremetal/README.md create mode 100644 examples/stm32/nucleo-f429zi-baremetal/boot.c create mode 100644 examples/stm32/nucleo-f429zi-baremetal/link.ld create mode 100644 examples/stm32/nucleo-f429zi-baremetal/main.c create mode 100644 examples/stm32/nucleo-f429zi-baremetal/mcu.h create mode 100644 examples/stm32/nucleo-f429zi-baremetal/syscalls.c diff --git a/examples/stm32/nucleo-f429zi-baremetal/Makefile b/examples/stm32/nucleo-f429zi-baremetal/Makefile new file mode 100644 index 00000000..4f68bddc --- /dev/null +++ b/examples/stm32/nucleo-f429zi-baremetal/Makefile @@ -0,0 +1,42 @@ +TARGET = firmware +ROOT ?= $(realpath $(CURDIR)/../../..) +D ?= docker +DOCKER ?= $(D) run --rm -v $(ROOT):$(ROOT) -w $(CURDIR) mdashnet/armgcc +CROSS ?= arm-none-eabi +CFLAGS ?= -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion \ + -Wformat-truncation -fno-common -Wconversion \ + -g3 -Os -ffunction-sections -fdata-sections -I. -I$(ROOT) \ + -DMG_ARCH=MG_ARCH_NEWLIB -DMIP_DEBUG=1 -DMG_ENABLE_PACKED_FS=1 \ + -DMG_ENABLE_CUSTOM_MILLIS=1 -DxMG_ENABLE_LINES=1 -DMG_ENABLE_MIP=1 \ + -mcpu=cortex-m4 -mthumb -mfloat-abi=soft $(EXTRA_CFLAGS) +LDFLAGS ?= -Tlink.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map +SOURCES = boot.c main.c syscalls.c \ + $(ROOT)/mongoose.c \ + $(ROOT)/examples/device-dashboard/packed_fs.c \ + $(ROOT)/examples/device-dashboard/net.c + +all build example: $(TARGET).bin + +$(TARGET).bin: $(TARGET).elf + $(DOCKER) $(CROSS)-objcopy -O binary $< $@ + +$(TARGET).elf: $(SOURCES) mcu.h + $(DOCKER) $(CROSS)-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@ + +# Build on Windows. Download Win32 Zip from ARM GCC downloads, unzip to c:\armgcc +ARMGCC ?= c:/armgcc +windows: $(TARGET).bin +windows: CROSS = $(ARMGCC)/bin/arm-none-eabi +windows: DOCKER = + +# Show top 10 stack-hungry functions +su: CFLAGS += -fstack-usage +su: $(TARGET).elf + cat *.su | sort -rnk2 | head -10 + +# Note: on "unknown chip id" flash error, wire BOOT0 to VDD and st-flash erase +flash: $(TARGET).bin + st-flash --reset write $(TARGET).bin 0x8000000 + +clean: + @rm -rf $(TARGET).* *.su diff --git a/examples/stm32/nucleo-f429zi-baremetal/README.md b/examples/stm32/nucleo-f429zi-baremetal/README.md new file mode 100644 index 00000000..50808066 --- /dev/null +++ b/examples/stm32/nucleo-f429zi-baremetal/README.md @@ -0,0 +1,36 @@ +# Baremetal webserver on NUCLEO-F429ZG + +This firmware uses experimental TCP/IP stack of the Mongoose Network Library, +which implements the following: + +- Implements HTTP server and SNTP time synchronisation +- No dependencies: no HAL, no CMSIS, no RTOS +- Hand-written [mcu.h](mcu.h) header based on a [datasheet](https://www.st.com/resource/en/reference_manual/rm0090-stm32f405415-stm32f407417-stm32f427437-and-stm32f429439-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) +- Interrupt-driven [mip_driver_stm32.h](../../../drivers/mip_driver_stm32.h) ethernet driver +- Blue LED blinky, based on SysTick interrupt +- User button handler, turns off/on green LED, based on EXTI, interrupt-driven +- HardFault handler that blinks red LED +- Debug log on UART3 (st-link) + +## Requirements + +- GNU make +- [ARM GCC](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm) toolchain for build +- [st-link](https://github.com/stlink-org/stlink) for flashing + +## Usage + +Plugin your Nucleo board into USB, and attach an Ethernet cable. +To build and flash: + +```sh +$ make clean flash +``` + +To see debug log, use any serial monitor program like `picocom` at 115200 bps and configure it to insert carriage returns after line feeds: + +```sh +$ picocom /dev/ttyACM0 -i -b 115200 --imap=lfcrlf +``` + +For more details and benchmark data on MIP, check the [F746ZG example](../nucleo-f746zg-baremetal/) diff --git a/examples/stm32/nucleo-f429zi-baremetal/boot.c b/examples/stm32/nucleo-f429zi-baremetal/boot.c new file mode 100644 index 00000000..91c69a66 --- /dev/null +++ b/examples/stm32/nucleo-f429zi-baremetal/boot.c @@ -0,0 +1,162 @@ +// Copyright (c) 2022 Cesanta Software Limited +// All rights reserved + +// Startup code +__attribute__((naked, noreturn)) void _reset(void) { + // Init stack + asm("ldr sp, = _estack"); + + // Initialise memory + extern long _sbss, _ebss, _sdata, _edata, _sidata; + for (long *src = &_sbss; src < &_ebss; src++) *src = 0; + for (long *src = &_sdata, *dst = &_sidata; src < &_edata;) *src++ = *dst++; + + // Call main() + extern void main(void); + main(); + for (;;) (void) 0; +} + +void __attribute__((weak)) DefaultIRQHandler(void) { + for (;;) (void) 0; +} + +#define WEAK_ALIAS __attribute__((weak, alias("DefaultIRQHandler"))) + +WEAK_ALIAS void NMI_Handler(void); +WEAK_ALIAS void HardFault_Handler(void); +WEAK_ALIAS void MemManage_Handler(void); +WEAK_ALIAS void BusFault_Handler(void); +WEAK_ALIAS void UsageFault_Handler(void); +WEAK_ALIAS void SVC_Handler(void); +WEAK_ALIAS void DebugMon_Handler(void); +WEAK_ALIAS void PendSV_Handler(void); +WEAK_ALIAS void SysTick_Handler(void); + +WEAK_ALIAS void WWDG_IRQHandler(void); +WEAK_ALIAS void PVD_IRQHandler(void); +WEAK_ALIAS void TAMP_STAMP_IRQHandler(void); +WEAK_ALIAS void RTC_WKUP_IRQHandler(void); +WEAK_ALIAS void FLASH_IRQHandler(void); +WEAK_ALIAS void RCC_IRQHandler(void); +WEAK_ALIAS void EXTI0_IRQHandler(void); +WEAK_ALIAS void EXTI1_IRQHandler(void); +WEAK_ALIAS void EXTI2_IRQHandler(void); +WEAK_ALIAS void EXTI3_IRQHandler(void); +WEAK_ALIAS void EXTI4_IRQHandler(void); +WEAK_ALIAS void EXTI9_5_IRQHandler(void); +WEAK_ALIAS void EXTI15_10_IRQHandler(void); +WEAK_ALIAS void DMA1_Stream0_IRQHandler(void); +WEAK_ALIAS void DMA1_Stream1_IRQHandler(void); +WEAK_ALIAS void DMA1_Stream2_IRQHandler(void); +WEAK_ALIAS void DMA1_Stream3_IRQHandler(void); +WEAK_ALIAS void DMA1_Stream4_IRQHandler(void); +WEAK_ALIAS void DMA1_Stream5_IRQHandler(void); +WEAK_ALIAS void DMA1_Stream6_IRQHandler(void); +WEAK_ALIAS void ADC_IRQHandler(void); +WEAK_ALIAS void CAN1_TX_IRQHandler(void); +WEAK_ALIAS void CAN1_RX0_IRQHandler(void); +WEAK_ALIAS void CAN1_RX1_IRQHandler(void); +WEAK_ALIAS void CAN1_SCE_IRQHandler(void); +WEAK_ALIAS void TIM1_BRK_TIM9_IRQHandler(void); +WEAK_ALIAS void TIM1_UP_TIM10_IRQHandler(void); +WEAK_ALIAS void TIM1_TRG_COM_TIM11_IRQHandler(void); +WEAK_ALIAS void TIM1_CC_IRQHandler(void); +WEAK_ALIAS void TIM2_IRQHandler(void); +WEAK_ALIAS void TIM3_IRQHandler(void); +WEAK_ALIAS void TIM4_IRQHandler(void); +WEAK_ALIAS void I2C1_EV_IRQHandler(void); +WEAK_ALIAS void I2C1_ER_IRQHandler(void); +WEAK_ALIAS void I2C2_EV_IRQHandler(void); +WEAK_ALIAS void I2C2_ER_IRQHandler(void); +WEAK_ALIAS void SPI1_IRQHandler(void); +WEAK_ALIAS void SPI2_IRQHandler(void); +WEAK_ALIAS void USART1_IRQHandler(void); +WEAK_ALIAS void USART2_IRQHandler(void); +WEAK_ALIAS void USART3_IRQHandler(void); +WEAK_ALIAS void RTC_Alarm_IRQHandler(void); +WEAK_ALIAS void OTG_FS_WKUP_IRQHandler(void); +WEAK_ALIAS void TIM8_BRK_TIM12_IRQHandler(void); +WEAK_ALIAS void TIM8_UP_TIM13_IRQHandler(void); +WEAK_ALIAS void TIM8_TRG_COM_TIM14_IRQHandler(void); +WEAK_ALIAS void TIM8_CC_IRQHandler(void); +WEAK_ALIAS void DMA1_Stream7_IRQHandler(void); +WEAK_ALIAS void FMC_IRQHandler(void); +WEAK_ALIAS void SDMMC1_IRQHandler(void); +WEAK_ALIAS void TIM5_IRQHandler(void); +WEAK_ALIAS void SPI3_IRQHandler(void); +WEAK_ALIAS void UART4_IRQHandler(void); +WEAK_ALIAS void UART5_IRQHandler(void); +WEAK_ALIAS void TIM6_DAC_IRQHandler(void); +WEAK_ALIAS void TIM7_IRQHandler(void); +WEAK_ALIAS void DMA2_Stream0_IRQHandler(void); +WEAK_ALIAS void DMA2_Stream1_IRQHandler(void); +WEAK_ALIAS void DMA2_Stream2_IRQHandler(void); +WEAK_ALIAS void DMA2_Stream3_IRQHandler(void); +WEAK_ALIAS void DMA2_Stream4_IRQHandler(void); +WEAK_ALIAS void ETH_IRQHandler(void); +WEAK_ALIAS void ETH_WKUP_IRQHandler(void); +WEAK_ALIAS void CAN2_TX_IRQHandler(void); +WEAK_ALIAS void CAN2_RX0_IRQHandler(void); +WEAK_ALIAS void CAN2_RX1_IRQHandler(void); +WEAK_ALIAS void CAN2_SCE_IRQHandler(void); +WEAK_ALIAS void OTG_FS_IRQHandler(void); +WEAK_ALIAS void DMA2_Stream5_IRQHandler(void); +WEAK_ALIAS void DMA2_Stream6_IRQHandler(void); +WEAK_ALIAS void DMA2_Stream7_IRQHandler(void); +WEAK_ALIAS void USART6_IRQHandler(void); +WEAK_ALIAS void I2C3_EV_IRQHandler(void); +WEAK_ALIAS void I2C3_ER_IRQHandler(void); +WEAK_ALIAS void OTG_HS_EP1_OUT_IRQHandler(void); +WEAK_ALIAS void OTG_HS_EP1_IN_IRQHandler(void); +WEAK_ALIAS void OTG_HS_WKUP_IRQHandler(void); +WEAK_ALIAS void OTG_HS_IRQHandler(void); +WEAK_ALIAS void DCMI_IRQHandler(void); +WEAK_ALIAS void RNG_IRQHandler(void); +WEAK_ALIAS void FPU_IRQHandler(void); +WEAK_ALIAS void UART7_IRQHandler(void); +WEAK_ALIAS void UART8_IRQHandler(void); +WEAK_ALIAS void SPI4_IRQHandler(void); +WEAK_ALIAS void SPI5_IRQHandler(void); +WEAK_ALIAS void SPI6_IRQHandler(void); +WEAK_ALIAS void SAI1_IRQHandler(void); +WEAK_ALIAS void LTDC_IRQHandler(void); +WEAK_ALIAS void LTDC_ER_IRQHandler(void); +WEAK_ALIAS void DMA2D_IRQHandler(void); + +// IRQ table +__attribute__((section(".vectors"))) void (*tab[16 + 91])(void) = { + // Cortex interrupts + 0, _reset, NMI_Handler, HardFault_Handler, MemManage_Handler, + BusFault_Handler, UsageFault_Handler, 0, 0, 0, 0, SVC_Handler, + DebugMon_Handler, 0, PendSV_Handler, SysTick_Handler, + + // Interrupts from peripherals + WWDG_IRQHandler, PVD_IRQHandler, TAMP_STAMP_IRQHandler, RTC_WKUP_IRQHandler, + FLASH_IRQHandler, RCC_IRQHandler, EXTI0_IRQHandler, EXTI1_IRQHandler, + EXTI2_IRQHandler, EXTI3_IRQHandler, EXTI4_IRQHandler, + DMA1_Stream0_IRQHandler, DMA1_Stream1_IRQHandler, DMA1_Stream2_IRQHandler, + DMA1_Stream3_IRQHandler, DMA1_Stream4_IRQHandler, DMA1_Stream5_IRQHandler, + DMA1_Stream6_IRQHandler, ADC_IRQHandler, CAN1_TX_IRQHandler, + CAN1_RX0_IRQHandler, CAN1_RX1_IRQHandler, CAN1_SCE_IRQHandler, + EXTI9_5_IRQHandler, TIM1_BRK_TIM9_IRQHandler, TIM1_UP_TIM10_IRQHandler, + TIM1_TRG_COM_TIM11_IRQHandler, TIM1_CC_IRQHandler, TIM2_IRQHandler, + TIM3_IRQHandler, TIM4_IRQHandler, I2C1_EV_IRQHandler, I2C1_ER_IRQHandler, + I2C2_EV_IRQHandler, I2C2_ER_IRQHandler, SPI1_IRQHandler, SPI2_IRQHandler, + USART1_IRQHandler, USART2_IRQHandler, USART3_IRQHandler, + EXTI15_10_IRQHandler, RTC_Alarm_IRQHandler, OTG_FS_WKUP_IRQHandler, + TIM8_BRK_TIM12_IRQHandler, TIM8_UP_TIM13_IRQHandler, + TIM8_TRG_COM_TIM14_IRQHandler, TIM8_CC_IRQHandler, DMA1_Stream7_IRQHandler, + FMC_IRQHandler, SDMMC1_IRQHandler, TIM5_IRQHandler, SPI3_IRQHandler, + UART4_IRQHandler, UART5_IRQHandler, TIM6_DAC_IRQHandler, TIM7_IRQHandler, + DMA2_Stream0_IRQHandler, DMA2_Stream1_IRQHandler, DMA2_Stream2_IRQHandler, + DMA2_Stream3_IRQHandler, DMA2_Stream4_IRQHandler, ETH_IRQHandler, + ETH_WKUP_IRQHandler, CAN2_TX_IRQHandler, CAN2_RX0_IRQHandler, + CAN2_RX1_IRQHandler, CAN2_SCE_IRQHandler, OTG_FS_IRQHandler, + DMA2_Stream5_IRQHandler, DMA2_Stream6_IRQHandler, DMA2_Stream7_IRQHandler, + USART6_IRQHandler, I2C3_EV_IRQHandler, I2C3_ER_IRQHandler, + OTG_HS_EP1_OUT_IRQHandler, OTG_HS_EP1_IN_IRQHandler, OTG_HS_WKUP_IRQHandler, + OTG_HS_IRQHandler, DCMI_IRQHandler, 0, RNG_IRQHandler, FPU_IRQHandler, + UART7_IRQHandler, UART8_IRQHandler, SPI4_IRQHandler, SPI5_IRQHandler, + SPI6_IRQHandler, SAI1_IRQHandler, LTDC_IRQHandler, LTDC_ER_IRQHandler, + DMA2D_IRQHandler}; diff --git a/examples/stm32/nucleo-f429zi-baremetal/link.ld b/examples/stm32/nucleo-f429zi-baremetal/link.ld new file mode 100644 index 00000000..b262649d --- /dev/null +++ b/examples/stm32/nucleo-f429zi-baremetal/link.ld @@ -0,0 +1,29 @@ +ENTRY(_reset); +MEMORY { + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k + sram(rwx) : ORIGIN = 0x20000000, LENGTH = 192k /* remaining 64k in a separate address space */ +} +_estack = ORIGIN(sram) + LENGTH(sram); /* stack points to end of SRAM */ + +SECTIONS { + .vectors : { KEEP(*(.vectors)) } > flash + .text : { *(.text*) } > flash + .rodata : { *(.rodata*) } > flash + + .data : { + _sdata = .; /* for init_ram() */ + *(.first_data) + *(.data SORT(.data.*)) + _edata = .; /* for init_ram() */ + } > sram AT > flash + _sidata = LOADADDR(.data); + + .bss : { + _sbss = .; /* for init_ram() */ + *(.bss SORT(.bss.*) COMMON) + _ebss = .; /* for init_ram() */ + } > sram + + . = ALIGN(8); + _end = .; /* for cmsis_gcc.h and init_ram() */ +} diff --git a/examples/stm32/nucleo-f429zi-baremetal/main.c b/examples/stm32/nucleo-f429zi-baremetal/main.c new file mode 100644 index 00000000..fbc5d9ea --- /dev/null +++ b/examples/stm32/nucleo-f429zi-baremetal/main.c @@ -0,0 +1,82 @@ +// Copyright (c) 2022 Cesanta Software Limited +// All rights reserved + +#include "mcu.h" +#include "mongoose.h" + +#define LED1 PIN('B', 0) // On-board LED pin (green) +#define LED2 PIN('B', 7) // On-board LED pin (blue) +#define LED3 PIN('B', 14) // On-board LED pin (red) +#define BTN1 PIN('C', 13) // On-board user button + +static uint64_t s_ticks, s_exti; // Counters, increased by IRQ handlers + +static void blink_cb(void *arg) { // Blink periodically + // MG_INFO(("ticks: %u", (unsigned) s_ticks)); + gpio_toggle(LED2); + (void) arg; +} + +uint64_t mg_millis(void) { // Declare our own uptime function + return s_ticks; // Return number of milliseconds since boot +} + +void HardFault_Handler(void) { // Escalated fault handler + gpio_output(LED3); // Setup red LED + for (;;) spin(2999999), gpio_toggle(LED3); // Blink LED infinitely +} + +void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms + s_ticks++; +} + +void EXTI15_10_IRQHandler(void) { // External interrupt handler + s_exti++; + if (EXTI->PR & BIT(PINNO(BTN1))) EXTI->PR = BIT(PINNO(BTN1)); + gpio_write(LED1, gpio_read(BTN1)); // No debounce. Turn LED if button pressed +} + +int main(void) { + static struct uart *uart = UART3; // Use UART3 - its attached to debug + clock_init(); // Set clock to 180MHz + systick_init(FREQ / 1000); // Increment s_ticks every ms + gpio_output(LED1); // Setup green LED + gpio_output(LED2); // Setup blue LED + gpio_input(BTN1); // Set button to input + irq_exti_attach(BTN1); // Attach BTN1 to exti + uart_init(uart, 115200); // It is wired to the debug port + + // Initialise Ethernet. Enable MAC GPIO pins, see + // https://www.farnell.com/datasheets/2014265.pdf section 6.10 + uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7), + PIN('B', 13), PIN('C', 1), PIN('C', 4), + PIN('C', 5), PIN('G', 11), PIN('G', 13)}; + for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) { + gpio_init(pins[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE, + GPIO_PULL_NONE, 11); + } + nvic_enable_irq(61); // Setup Ethernet IRQ handler + RCC->APB2ENR |= BIT(14); // Enable SYSCFG + SYSCFG->PMC |= BIT(23); // Use RMII. Goes first! + RCC->AHB1ENR |= BIT(25) | BIT(26) | BIT(27); // Enable Ethernet clocks + RCC->AHB1RSTR |= BIT(25); // ETHMAC force reset + RCC->AHB1RSTR &= ~BIT(25); // ETHMAC release reset + + struct mg_mgr mgr; // Initialise Mongoose event manager + mg_mgr_init(&mgr); // and attach it to the MIP interface + mg_log_set(MG_LL_DEBUG); // Set log level + mg_timer_add(&mgr, 500, MG_TIMER_REPEAT, blink_cb, &mgr); + + // Initialise Mongoose network stack + // Specify MAC address, and use 0 for IP, mask, GW - i.e. use DHCP + // For static configuration, specify IP/mask/GW in network byte order + struct mip_ipcfg c = {.mac = {0, 0, 1, 2, 3, 4}, .ip = 0, .mask = 0, .gw = 0}; + mip_init(&mgr, &c, &mip_driver_stm32, NULL); + MG_INFO(("Init done, starting main loop")); + + extern void device_dashboard_fn(struct mg_connection *, int, void *, void *); + mg_http_listen(&mgr, "http://0.0.0.0", device_dashboard_fn, &mgr); + for (;;) mg_mgr_poll(&mgr, 0); // Infinite event loop + + return 0; +} diff --git a/examples/stm32/nucleo-f429zi-baremetal/mcu.h b/examples/stm32/nucleo-f429zi-baremetal/mcu.h new file mode 100644 index 00000000..28af5ecd --- /dev/null +++ b/examples/stm32/nucleo-f429zi-baremetal/mcu.h @@ -0,0 +1,217 @@ +// Copyright (c) 2022 Cesanta Software Limited +// All rights reserved +// https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf + +#pragma once + +#include +#include +#include +#include + +#define BIT(x) (1UL << (x)) +#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK) +#define PIN(bank, num) ((((bank) - 'A') << 8) | (num)) +#define PINNO(pin) (pin & 255) +#define PINBANK(pin) (pin >> 8) + +/* System clock +6.3.3: APB1 clock <= 45MHz; APB2 clock <= 90MHz +3.5.1, Table 11: configure flash latency (WS) in accordance to clock freq +33.4: The AHB clock frequency must be at least 25 MHz when the Ethernet controller is used */ +enum { APB1_PRE = 5 /* AHB clock / 4 */, APB2_PRE = 4 /* AHB clock / 2 */ }; +enum { PLL_HSI = 16, PLL_M = 8, PLL_N = 180, PLL_P = 2 }; // Run at 180 Mhz +//#define PLL_FREQ PLL_HSI +#define PLL_FREQ (PLL_HSI * PLL_N / PLL_M / PLL_P) +#define FLASH_LATENCY 5 +#define FREQ (PLL_FREQ * 1000000) + +static inline void spin(volatile uint32_t count) { + while (count--) asm("nop"); +} + +struct rcc { + volatile uint32_t CR, PLLCFGR, CFGR, CIR, AHB1RSTR, AHB2RSTR, AHB3RSTR, + RESERVED0, APB1RSTR, APB2RSTR, RESERVED1[2], AHB1ENR, AHB2ENR, AHB3ENR, + RESERVED2, APB1ENR, APB2ENR, RESERVED3[2], AHB1LPENR, AHB2LPENR, + AHB3LPENR, RESERVED4, APB1LPENR, APB2LPENR, RESERVED5[2], BDCR, CSR, + RESERVED6[2], SSCGR, PLLI2SCFGR; +}; +#define RCC ((struct rcc *) 0x40023800) + +struct pwr { + volatile uint32_t CR, CSR; +}; +#define PWR ((struct pwr *) 0x40007000) + +struct nvic { + volatile uint32_t ISER[8], RESERVED0[24], ICER[8], RSERVED1[24], ISPR[8], + RESERVED2[24], ICPR[8], RESERVED3[24], IABR[8], RESERVED4[56], IP[240], + RESERVED5[644], STIR; +}; +#define NVIC ((struct nvic *) 0xe000e100) +static inline void nvic_set_prio(int irq, uint32_t prio) { + NVIC->IP[irq] = prio << 4; +} +static inline void nvic_enable_irq(int irq) { + NVIC->ISER[irq >> 5] = (uint32_t) (1 << (irq & 31)); +} + +struct systick { + volatile uint32_t CTRL, LOAD, VAL, CALIB; +}; +#define SYSTICK ((struct systick *) 0xe000e010) // 2.2.2 +static inline void systick_init(uint32_t ticks) { + if ((ticks - 1) > 0xffffff) return; // Systick timer is 24 bit + SYSTICK->LOAD = ticks - 1; + SYSTICK->VAL = 0; + SYSTICK->CTRL = BIT(0) | BIT(1) | BIT(2); // Enable systick + RCC->APB2ENR |= BIT(14); // Enable SYSCFG +} + +struct flash { + volatile uint32_t ACR, KEYR, OPTKEYR, SR, CR, AR, RESERVED, OBR, WRPR; +}; +#define FLASH ((struct flash *) 0x40023c00) + +struct scb { + volatile uint32_t CPUID, ICSR, VTOR, AIRCR, SCR, CCR, SHPR[3], SHCSR, CFSR, + HFSR, DFSR, MMFAR, BFAR, AFSR, ID_PFR[2], ID_DFR, ID_AFR, ID_MFR[4], + ID_ISAR[5], RESERVED0[1], CLIDR, CTR, CCSIDR, CSSELR, CPACR, + RESERVED3[93], STIR, RESERVED4[15], MVFR0, MVFR1, MVFR2, RESERVED5[1], + ICIALLU, RESERVED6[1], ICIMVAU, DCIMVAC, DCISW, DCCMVAU, DCCMVAC, DCCSW, + DCCIMVAC, DCCISW, RESERVED7[6], ITCMCR, DTCMCR, AHBPCR, CACR, AHBSCR, + RESERVED8[1], ABFSR; +}; +#define SCB ((struct scb *) 0xe000e000) + +enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG }; +enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN }; +enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE }; +enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +struct gpio { + volatile uint32_t MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR, BSRR, LCKR, AFR[2]; +}; +#define GPIO(N) ((struct gpio *) (0x40020000 + 0x400 * (N))) + +static struct gpio *gpio_bank(uint16_t pin) { + return GPIO(PINBANK(pin)); +} +static inline void gpio_toggle(uint16_t pin) { + struct gpio *gpio = gpio_bank(pin); + uint32_t mask = BIT(PINNO(pin)); + gpio->BSRR |= mask << (gpio->ODR & mask ? 16 : 0); +} +static inline int gpio_read(uint16_t pin) { + return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0; +} +static inline void gpio_write(uint16_t pin, bool val) { + struct gpio *gpio = gpio_bank(pin); + gpio->BSRR |= BIT(PINNO(pin)) << (val ? 0 : 16); +} +static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type, + uint8_t speed, uint8_t pull, uint8_t af) { + struct gpio *gpio = gpio_bank(pin); + uint8_t n = (uint8_t) (PINNO(pin)); + RCC->AHB1ENR |= BIT(PINBANK(pin)); // Enable GPIO clock + SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n); + SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2)); + SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2)); + SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4), + ((uint32_t) af) << ((n & 7) * 4)); + SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2)); +} +static inline void gpio_input(uint16_t pin) { + gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, + GPIO_PULL_NONE, 0); +} +static inline void gpio_output(uint16_t pin) { + gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, + GPIO_PULL_NONE, 0); +} + +struct syscfg { + volatile uint32_t MEMRMP, PMC, EXTICR[4], RESERVED[2], CMPCR; +}; +#define SYSCFG ((struct syscfg *) 0x40013800) + +struct exti { + volatile uint32_t IMR, EMR, RTSR, FTSR, SWIER, PR; +}; +#define EXTI ((struct exti *) 0x40013c00) + +static inline void irq_exti_attach(uint16_t pin) { + uint8_t bank = (uint8_t) (PINBANK(pin)), n = (uint8_t) (PINNO(pin)); + RCC->APB2ENR |= BIT(14); // Enable SYSCFG + SYSCFG->EXTICR[n / 4] &= ~(15UL << ((n % 4) * 4)); + SYSCFG->EXTICR[n / 4] |= (uint32_t) (bank << ((n % 4) * 4)); + EXTI->IMR |= BIT(n); + EXTI->RTSR |= BIT(n); + EXTI->FTSR |= BIT(n); + int irqvec = n < 5 ? 6 + n : n < 10 ? 23 : 40; // IRQ vector index, 10.1.2 + nvic_set_prio(irqvec, 3); + nvic_enable_irq(irqvec); +} + +struct uart { + volatile uint32_t SR, DR, BRR, CR1, CR2, CR3, GTPR; +}; +#define UART1 ((struct uart *) 0x40011000) +#define UART2 ((struct uart *) 0x40004400) +#define UART3 ((struct uart *) 0x40004800) + +static inline void uart_init(struct uart *uart, unsigned long baud) { + // https://www.st.com/resource/en/datasheet/stm32f429zi.pdf + uint8_t af = 0; // Alternate function + uint16_t rx = 0, tx = 0; // pins + + if (uart == UART1) RCC->APB2ENR |= BIT(4); + if (uart == UART2) RCC->APB1ENR |= BIT(17); + if (uart == UART3) RCC->APB1ENR |= BIT(18); + + if (uart == UART1) af = 4, tx = PIN('A', 9), rx = PIN('A', 10); + if (uart == UART2) af = 4, tx = PIN('A', 2), rx = PIN('A', 3); + if (uart == UART3) af = 7, tx = PIN('D', 8), rx = PIN('D', 9); + + gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af); + gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af); + uart->CR1 = 0; // Disable this UART + uart->BRR = FREQ / 4 / baud; // Baud rate x16 (with 4dp), "4" is APBx prescaler, different from APBx_PRE + // TODO(): make this configurable ? + uart->CR1 |= BIT(13) | BIT(2) | BIT(3); // Set UE, RE, TE +} +static inline void uart_write_byte(struct uart *uart, uint8_t byte) { + uart->DR = byte; + while ((uart->SR & BIT(7)) == 0) spin(1); +} +static inline void uart_write_buf(struct uart *uart, char *buf, size_t len) { + while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++); +} +static inline int uart_read_ready(struct uart *uart) { + return uart->SR & BIT(5); // If RXNE bit is set, data is ready +} +static inline uint8_t uart_read_byte(struct uart *uart) { + return (uint8_t) (uart->DR & 255); +} + +static inline void clock_init(void) { // Set clock frequency +#if 0 + RCC->APB1ENR |= BIT(28); // Power enable + PWR->CR |= 3UL << 14; // Voltage regulator scale 3 + PWR->CR |= BIT(16); // Enable overdrive + while ((PWR->CSR & BIT(16)) == 0) spin(1); // Wait until done + PWR->CR |= BIT(17); // Enable overdrive switching + while ((PWR->CSR & BIT(17)) == 0) spin(1); // Wait until done + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU +#endif + FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch, Icache, Dcache + RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers + RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P + RCC->PLLCFGR |= PLL_M | (PLL_N << 6); // Set PLL_M and PLL_N + RCC->CR |= BIT(24); // Enable PLL + while ((RCC->CR & BIT(25)) == 0) spin(1); // Wait until done + RCC->CFGR = (APB1_PRE << 10) | (APB2_PRE << 13); // Set prescalers + RCC->CFGR |= 2; // Set clock source to PLL + while ((RCC->CFGR & 12) == 0) spin(1); // Wait until done +} diff --git a/examples/stm32/nucleo-f429zi-baremetal/syscalls.c b/examples/stm32/nucleo-f429zi-baremetal/syscalls.c new file mode 100644 index 00000000..3b16ca78 --- /dev/null +++ b/examples/stm32/nucleo-f429zi-baremetal/syscalls.c @@ -0,0 +1,83 @@ +#include + +#include "mcu.h" + +int _fstat(int fd, struct stat *st) { + if (fd < 0) return -1; + st->st_mode = S_IFCHR; + return 0; +} + +void *_sbrk(int incr) { + extern char _end; + static unsigned char *heap = NULL; + unsigned char *prev_heap; + if (heap == NULL) heap = (unsigned char *) &_end; + prev_heap = heap; + heap += incr; + return prev_heap; +} + +int _open(const char *path) { + (void) path; + return -1; +} + +int _close(int fd) { + (void) fd; + return -1; +} + +int _isatty(int fd) { + (void) fd; + return 1; +} + +int _lseek(int fd, int ptr, int dir) { + (void) fd, (void) ptr, (void) dir; + return 0; +} + +void _exit(int status) { + (void) status; + for (;;) asm volatile("BKPT #0"); +} + +void _kill(int pid, int sig) { + (void) pid, (void) sig; +} + +int _getpid(void) { + return -1; +} + +int _write(int fd, char *ptr, int len) { + (void) fd, (void) ptr, (void) len; + if (fd == 1) uart_write_buf(UART3, ptr, (size_t) len); + return -1; +} + +int _read(int fd, char *ptr, int len) { + (void) fd, (void) ptr, (void) len; + return -1; +} + +int _link(const char *a, const char *b) { + (void) a, (void) b; + return -1; +} + +int _unlink(const char *a) { + (void) a; + return -1; +} + +int _stat(const char *path, struct stat *st) { + (void) path, (void) st; + return -1; +} + +int mkdir(const char *path, mode_t mode) { + (void) path, (void) mode; + return -1; +}