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Remove IMX, imx prefix for NXP

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cpq committed 2023-10-24 17:30:22 +01:00
1 parent 2903937cba
commit 2caff93f83
5 files changed
+30 -30
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mongoose.c
+13 -13
View File
@@ -8438,9 +8438,9 @@ size_t mg_ws_wrap(struct mg_connection *c, size_t len, int op) {
#endif #endif
#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT1020) && \ #if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_RT1020) && \
MG_ENABLE_DRIVER_IMXRT1020 MG_ENABLE_DRIVER_RT1020
struct imx_rt1020_enet { struct rt1020_enet {
volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3], volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3],
ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR, ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR,
RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2, RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2,
@@ -8465,7 +8465,7 @@ struct imx_rt1020_enet {
}; };
#undef ENET #undef ENET
#define ENET ((struct imx_rt1020_enet *) (uintptr_t) 0x402D8000u) #define ENET ((struct rt1020_enet *) (uintptr_t) 0x402D8000u)
#undef BIT #undef BIT
#define BIT(x) ((uint32_t) 1 << (x)) #define BIT(x) ((uint32_t) 1 << (x))
@@ -8509,9 +8509,9 @@ static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
// MDC clock is generated from IPS Bus clock (ipg_clk); as per 802.3, // MDC clock is generated from IPS Bus clock (ipg_clk); as per 802.3,
// it must not exceed 2.5MHz // it must not exceed 2.5MHz
// The PHY receives the PLL6-generated 50MHz clock // The PHY receives the PLL6-generated 50MHz clock
static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) { static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) {
struct mg_tcpip_driver_imxrt1020_data *d = struct mg_tcpip_driver_rt1020_data *d =
(struct mg_tcpip_driver_imxrt1020_data *) ifp->driver_data; (struct mg_tcpip_driver_rt1020_data *) ifp->driver_data;
s_ifp = ifp; s_ifp = ifp;
// Init RX descriptors // Init RX descriptors
@@ -8561,8 +8561,8 @@ static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) {
// Transmit frame // Transmit frame
static uint32_t s_txno; static uint32_t s_txno;
static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len, static size_t mg_tcpip_driver_rt1020_tx(const void *buf, size_t len,
struct mg_tcpip_if *ifp) { struct mg_tcpip_if *ifp) {
if (len > sizeof(s_txbuf[ETH_DESC_CNT])) { if (len > sizeof(s_txbuf[ETH_DESC_CNT])) {
MG_ERROR(("Frame too big, %ld", (long) len)); MG_ERROR(("Frame too big, %ld", (long) len));
len = 0; // fail len = 0; // fail
@@ -8582,7 +8582,7 @@ static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len,
return len; return len;
} }
static bool mg_tcpip_driver_imxrt1020_up(struct mg_tcpip_if *ifp) { static bool mg_tcpip_driver_rt1020_up(struct mg_tcpip_if *ifp) {
uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR); uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR);
bool up = bsr & BIT(2) ? 1 : 0; bool up = bsr & BIT(2) ? 1 : 0;
if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up
@@ -8620,9 +8620,9 @@ void ENET_IRQHandler(void) {
// If b24 == 0, descriptors were exhausted and probably frames were dropped // If b24 == 0, descriptors were exhausted and probably frames were dropped
} }
struct mg_tcpip_driver mg_tcpip_driver_imxrt1020 = { struct mg_tcpip_driver mg_tcpip_driver_rt1020 = {
mg_tcpip_driver_imxrt1020_init, mg_tcpip_driver_imxrt1020_tx, NULL, mg_tcpip_driver_rt1020_init, mg_tcpip_driver_rt1020_tx, NULL,
mg_tcpip_driver_imxrt1020_up}; mg_tcpip_driver_rt1020_up};
#endif #endif
mongoose.h
+2 -2
View File
@@ -1789,7 +1789,7 @@ extern struct mg_tcpip_driver mg_tcpip_driver_stm32;
extern struct mg_tcpip_driver mg_tcpip_driver_w5500; extern struct mg_tcpip_driver mg_tcpip_driver_w5500;
extern struct mg_tcpip_driver mg_tcpip_driver_tm4c; extern struct mg_tcpip_driver mg_tcpip_driver_tm4c;
extern struct mg_tcpip_driver mg_tcpip_driver_stm32h; extern struct mg_tcpip_driver mg_tcpip_driver_stm32h;
extern struct mg_tcpip_driver mg_tcpip_driver_imxrt1020; extern struct mg_tcpip_driver mg_tcpip_driver_rt1020;
extern struct mg_tcpip_driver mg_tcpip_driver_same54; extern struct mg_tcpip_driver mg_tcpip_driver_same54;
// Drivers that require SPI, can use this SPI abstraction // Drivers that require SPI, can use this SPI abstraction
@@ -1802,7 +1802,7 @@ struct mg_tcpip_spi {
#endif #endif
struct mg_tcpip_driver_imxrt1020_data { struct mg_tcpip_driver_rt1020_data {
// MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk), // MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk),
// must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz // must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz
// 37.5.1.8.2, Table 37-46 : f = ipg_clk / (2(mdc_cr + 1)) // 37.5.1.8.2, Table 37-46 : f = ipg_clk / (2(mdc_cr + 1))
src/drivers/rt1020.c
+13 -13
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@@ -1,8 +1,8 @@
#include "tcpip.h" #include "tcpip.h"
#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT1020) && \ #if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_RT1020) && \
MG_ENABLE_DRIVER_IMXRT1020 MG_ENABLE_DRIVER_RT1020
struct imx_rt1020_enet { struct rt1020_enet {
volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3], volatile uint32_t RESERVED0, EIR, EIMR, RESERVED1, RDAR, TDAR, RESERVED2[3],
ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR, ECR, RESERVED3[6], MMFR, MSCR, RESERVED4[7], MIBC, RESERVED5[7], RCR,
RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2, RESERVED6[15], TCR, RESERVED7[7], PALR, PAUR, OPD, TXIC0, TXIC1, TXIC2,
@@ -27,7 +27,7 @@ struct imx_rt1020_enet {
}; };
#undef ENET #undef ENET
#define ENET ((struct imx_rt1020_enet *) (uintptr_t) 0x402D8000u) #define ENET ((struct rt1020_enet *) (uintptr_t) 0x402D8000u)
#undef BIT #undef BIT
#define BIT(x) ((uint32_t) 1 << (x)) #define BIT(x) ((uint32_t) 1 << (x))
@@ -71,9 +71,9 @@ static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
// MDC clock is generated from IPS Bus clock (ipg_clk); as per 802.3, // MDC clock is generated from IPS Bus clock (ipg_clk); as per 802.3,
// it must not exceed 2.5MHz // it must not exceed 2.5MHz
// The PHY receives the PLL6-generated 50MHz clock // The PHY receives the PLL6-generated 50MHz clock
static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) { static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) {
struct mg_tcpip_driver_imxrt1020_data *d = struct mg_tcpip_driver_rt1020_data *d =
(struct mg_tcpip_driver_imxrt1020_data *) ifp->driver_data; (struct mg_tcpip_driver_rt1020_data *) ifp->driver_data;
s_ifp = ifp; s_ifp = ifp;
// Init RX descriptors // Init RX descriptors
@@ -123,8 +123,8 @@ static bool mg_tcpip_driver_imxrt1020_init(struct mg_tcpip_if *ifp) {
// Transmit frame // Transmit frame
static uint32_t s_txno; static uint32_t s_txno;
static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len, static size_t mg_tcpip_driver_rt1020_tx(const void *buf, size_t len,
struct mg_tcpip_if *ifp) { struct mg_tcpip_if *ifp) {
if (len > sizeof(s_txbuf[ETH_DESC_CNT])) { if (len > sizeof(s_txbuf[ETH_DESC_CNT])) {
MG_ERROR(("Frame too big, %ld", (long) len)); MG_ERROR(("Frame too big, %ld", (long) len));
len = 0; // fail len = 0; // fail
@@ -144,7 +144,7 @@ static size_t mg_tcpip_driver_imxrt1020_tx(const void *buf, size_t len,
return len; return len;
} }
static bool mg_tcpip_driver_imxrt1020_up(struct mg_tcpip_if *ifp) { static bool mg_tcpip_driver_rt1020_up(struct mg_tcpip_if *ifp) {
uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR); uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR);
bool up = bsr & BIT(2) ? 1 : 0; bool up = bsr & BIT(2) ? 1 : 0;
if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up
@@ -182,8 +182,8 @@ void ENET_IRQHandler(void) {
// If b24 == 0, descriptors were exhausted and probably frames were dropped // If b24 == 0, descriptors were exhausted and probably frames were dropped
} }
struct mg_tcpip_driver mg_tcpip_driver_imxrt1020 = { struct mg_tcpip_driver mg_tcpip_driver_rt1020 = {
mg_tcpip_driver_imxrt1020_init, mg_tcpip_driver_imxrt1020_tx, NULL, mg_tcpip_driver_rt1020_init, mg_tcpip_driver_rt1020_tx, NULL,
mg_tcpip_driver_imxrt1020_up}; mg_tcpip_driver_rt1020_up};
#endif #endif
src/drivers/rt1020.h
+1 -1
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@@ -1,6 +1,6 @@
#pragma once #pragma once
struct mg_tcpip_driver_imxrt1020_data { struct mg_tcpip_driver_rt1020_data {
// MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk), // MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk),
// must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz // must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz
// 37.5.1.8.2, Table 37-46 : f = ipg_clk / (2(mdc_cr + 1)) // 37.5.1.8.2, Table 37-46 : f = ipg_clk / (2(mdc_cr + 1))
src/net_builtin.h
+1 -1
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@@ -55,7 +55,7 @@ extern struct mg_tcpip_driver mg_tcpip_driver_stm32;
extern struct mg_tcpip_driver mg_tcpip_driver_w5500; extern struct mg_tcpip_driver mg_tcpip_driver_w5500;
extern struct mg_tcpip_driver mg_tcpip_driver_tm4c; extern struct mg_tcpip_driver mg_tcpip_driver_tm4c;
extern struct mg_tcpip_driver mg_tcpip_driver_stm32h; extern struct mg_tcpip_driver mg_tcpip_driver_stm32h;
extern struct mg_tcpip_driver mg_tcpip_driver_imxrt1020; extern struct mg_tcpip_driver mg_tcpip_driver_rt1020;
extern struct mg_tcpip_driver mg_tcpip_driver_same54; extern struct mg_tcpip_driver mg_tcpip_driver_same54;
// Drivers that require SPI, can use this SPI abstraction // Drivers that require SPI, can use this SPI abstraction