From 2dffbc32bae2540f41d19af5ee52cc734ba4f684 Mon Sep 17 00:00:00 2001 From: "Sergio R. Caprile" Date: Mon, 12 Jun 2023 10:58:24 -0300 Subject: [PATCH] Squashed commit of the following: update for tag movement updated to new release update pack in examples new release number rename to extra Cleanup Added ready-made examples to ST pack Add Keil examples Fix CRLF, start adding examples descriptions Remove examples STM32Cube Expansion Pack with no examples Add STM32Cube Expansion Pack skeleton Added examples for discussion Add support for Cube Working on examples pack skeleton ready --- .../EventRecorderStub.scvd | 9 + .../nucleo-f746zg-keil-baremetal/README.md | 7 + .../STM32F746ZGTx/FrameworkCubeMX.gpdsc | 62 + .../RTE/Device/STM32F746ZGTx/MX_Device.h | 212 + .../STM32F746ZGTx/STCubeGenerated/.mxproject | 12 + .../STM32F746ZGTx/STCubeGenerated/Inc/main.h | 69 + .../STCubeGenerated/Inc/stm32f7xx_hal_conf.h | 484 + .../STCubeGenerated/Inc/stm32f7xx_it.h | 66 + .../STCubeGenerated/STCubeGenerated.ioc | 178 + .../STM32F746ZGTx/STCubeGenerated/Src/main.c | 330 + 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100644 extra/stm_exp_pack/Makefile diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-baremetal/EventRecorderStub.scvd b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-baremetal/EventRecorderStub.scvd new file mode 100644 index 00000000..0fb3ee58 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-baremetal/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-baremetal/README.md b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-baremetal/README.md new file mode 100644 index 00000000..4d765bae --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-baremetal/README.md @@ -0,0 +1,7 @@ +# Baremetal web device dashboard on NUCLEO-F746ZG, built on Keil MDK + +- Open this example with Keil uVision +- Build it +- Run/Debug it + +Mongoose configuration is in mongoose_custom.h, inside Network_Library diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-baremetal/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-baremetal/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc new file mode 100644 index 00000000..60e1807b --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-baremetal/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc @@ -0,0 +1,62 @@ + + + + + Keil + FrameworkCubeMX + STM32CubeMX generated pack description + project-path + + + - Generated: 14/03/2023 13:27:52 + + + + + STM32CubeMX Environment + + $SMDK/CubeMX/STM32CubeMXLauncher + $PRTE/Device/STM32F746ZGTx + + + + + + + + + + STM32Cube Framework + + + + Condition to include CMSIS core and Device Startup components + + + + + + + + + + + + + + Configuration via STM32CubeMX + + #define RTE_DEVICE_FRAMEWORK_CUBE_MX + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/MX_Device.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/MX_Device.h new file mode 100644 index 00000000..00adb2ad --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/MX_Device.h @@ -0,0 +1,212 @@ +/****************************************************************************** + * File Name : MX_Device.h + * Date : 14/03/2023 13:35:04 + * Description : STM32Cube MX parameter definitions + * Note : This file is generated by STM32CubeMX (DO NOT EDIT!) + ******************************************************************************/ + +#ifndef __MX_DEVICE_H +#define __MX_DEVICE_H + +/*---------------------------- Clock Configuration ---------------------------*/ + +#define MX_LSI_VALUE 32000 +#define MX_LSE_VALUE 32768 +#define MX_HSI_VALUE 16000000 +#define MX_HSE_VALUE 25000000 +#define MX_EXTERNAL_CLOCK_VALUE 12288000 +#define MX_SYSCLKFreq_VALUE 216000000 +#define MX_HCLKFreq_Value 216000000 +#define MX_FCLKCortexFreq_Value 216000000 +#define MX_CortexFreq_Value 216000000 +#define MX_AHBFreq_Value 216000000 +#define MX_APB1Freq_Value 54000000 +#define MX_APB2Freq_Value 108000000 +#define MX_APB1TimFreq_Value 108000000 +#define MX_APB2TimFreq_Value 216000000 +#define MX_EthernetFreq_Value 216000000 +#define MX_CECFreq_Value 32786 +#define MX_LCDTFToutputFreq_Value 96000000 +#define MX_I2C1Freq_Value 54000000 +#define MX_I2C2Freq_Value 54000000 +#define MX_I2C3Freq_Value 54000000 +#define MX_I2C4Freq_Value 54000000 +#define MX_I2SFreq_Value 192000000 +#define MX_SAI1Freq_Value 192000000 +#define MX_SAI2Freq_Value 192000000 +#define MX_SDMMCFreq_Value 216000000 +#define MX_RTCFreq_Value 32000 +#define MX_USART1Freq_Value 108000000 +#define MX_USART2Freq_Value 54000000 +#define MX_USART3Freq_Value 54000000 +#define MX_UART4Freq_Value 54000000 +#define MX_UART5Freq_Value 54000000 +#define MX_UART8Freq_Value 54000000 +#define MX_UART7Freq_Value 54000000 +#define MX_USART6Freq_Value 108000000 +#define MX_USBFreq_Value 48000000 +#define MX_WatchDogFreq_Value 32000 +#define MX_LPTIM1Freq_Value 54000000 +#define MX_SPDIFRXFreq_Value 192000000 +#define MX_MCO1PinFreq_Value 16000000 +#define MX_MCO2PinFreq_Value 216000000 + +/*-------------------------------- CORTEX_M7 --------------------------------*/ + +#define MX_CORTEX_M7 1 + +/* GPIO Configuration */ + +/*-------------------------------- ETH --------------------------------*/ + +#define MX_ETH 1 + +/* GPIO Configuration */ + +/* Pin PA1 */ +#define MX_ETH_REF_CLK_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_REF_CLK_Pin PA1 +#define MX_ETH_REF_CLK_GPIOx GPIOA +#define MX_ETH_REF_CLK_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_REF_CLK_GPIO_Pin GPIO_PIN_1 +#define MX_ETH_REF_CLK_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_REF_CLK_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PA7 */ +#define MX_ETH_CRS_DV_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_CRS_DV_Pin PA7 +#define MX_ETH_CRS_DV_GPIOx GPIOA +#define MX_ETH_CRS_DV_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_CRS_DV_GPIO_Pin GPIO_PIN_7 +#define MX_ETH_CRS_DV_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_CRS_DV_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC4 */ +#define MX_ETH_RXD0_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_RXD0_Pin PC4 +#define MX_ETH_RXD0_GPIOx GPIOC +#define MX_ETH_RXD0_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_RXD0_GPIO_Pin GPIO_PIN_4 +#define MX_ETH_RXD0_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_RXD0_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC5 */ +#define MX_ETH_RXD1_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_RXD1_Pin PC5 +#define MX_ETH_RXD1_GPIOx GPIOC +#define MX_ETH_RXD1_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_RXD1_GPIO_Pin GPIO_PIN_5 +#define MX_ETH_RXD1_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_RXD1_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PG11 */ +#define MX_ETH_TX_EN_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TX_EN_Pin PG11 +#define MX_ETH_TX_EN_GPIOx GPIOG +#define MX_ETH_TX_EN_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TX_EN_GPIO_Pin GPIO_PIN_11 +#define MX_ETH_TX_EN_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TX_EN_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PA2 */ +#define MX_ETH_MDIO_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_MDIO_Pin PA2 +#define MX_ETH_MDIO_GPIOx GPIOA +#define MX_ETH_MDIO_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_MDIO_GPIO_Pin GPIO_PIN_2 +#define MX_ETH_MDIO_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_MDIO_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PB13 */ +#define MX_ETH_TXD1_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TXD1_Pin PB13 +#define MX_ETH_TXD1_GPIOx GPIOB +#define MX_ETH_TXD1_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TXD1_GPIO_Pin GPIO_PIN_13 +#define MX_ETH_TXD1_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TXD1_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PG13 */ +#define MX_ETH_TXD0_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TXD0_Pin PG13 +#define MX_ETH_TXD0_GPIOx GPIOG +#define MX_ETH_TXD0_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TXD0_GPIO_Pin GPIO_PIN_13 +#define MX_ETH_TXD0_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TXD0_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC1 */ +#define MX_ETH_MDC_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_MDC_Pin PC1 +#define MX_ETH_MDC_GPIOx GPIOC +#define MX_ETH_MDC_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_MDC_GPIO_Pin GPIO_PIN_1 +#define MX_ETH_MDC_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_MDC_GPIO_Mode GPIO_MODE_AF_PP + +/* NVIC Configuration */ + +/* NVIC ETH_IRQn */ +#define MX_ETH_IRQn_interruptPremptionPriority 0 +#define MX_ETH_IRQn_PriorityGroup NVIC_PRIORITYGROUP_4 +#define MX_ETH_IRQn_Subriority 0 + +/*-------------------------------- RNG --------------------------------*/ + +#define MX_RNG 1 + +/* GPIO Configuration */ + +/*-------------------------------- SYS --------------------------------*/ + +#define MX_SYS 1 + +/* GPIO Configuration */ + +/*-------------------------------- USART3 --------------------------------*/ + +#define MX_USART3 1 + +#define MX_USART3_VM VM_ASYNC + +/* GPIO Configuration */ + +/* Pin PD8 */ +#define MX_USART3_TX_GPIO_ModeDefaultPP GPIO_MODE_AF_PP +#define MX_USART3_TX_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_USART3_TX_Pin PD8 +#define MX_USART3_TX_GPIOx GPIOD +#define MX_USART3_TX_GPIO_PuPd GPIO_NOPULL +#define MX_USART3_TX_GPIO_Pin GPIO_PIN_8 +#define MX_USART3_TX_GPIO_AF GPIO_AF7_USART3 + +/* Pin PD9 */ +#define MX_USART3_RX_GPIO_ModeDefaultPP GPIO_MODE_AF_PP +#define MX_USART3_RX_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_USART3_RX_Pin PD9 +#define MX_USART3_RX_GPIOx GPIOD +#define MX_USART3_RX_GPIO_PuPd GPIO_NOPULL +#define MX_USART3_RX_GPIO_Pin GPIO_PIN_9 +#define MX_USART3_RX_GPIO_AF GPIO_AF7_USART3 + +/*-------------------------------- NVIC --------------------------------*/ + +#define MX_NVIC 1 + +/*-------------------------------- GPIO --------------------------------*/ + +#define MX_GPIO 1 + +/* GPIO Configuration */ + +/* Pin PB7 */ +#define MX_PB7_GPIO_Speed GPIO_SPEED_FREQ_LOW +#define MX_PB7_Pin PB7 +#define MX_PB7_GPIOx GPIOB +#define MX_PB7_PinState GPIO_PIN_RESET +#define MX_PB7_GPIO_PuPd GPIO_NOPULL +#define MX_PB7_GPIO_Pin GPIO_PIN_7 +#define MX_PB7_GPIO_ModeDefaultOutputPP GPIO_MODE_OUTPUT_PP + +#endif /* __MX_DEVICE_H */ + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject new file mode 100644 index 00000000..9a8f5fd7 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject @@ -0,0 +1,12 @@ +[PreviousLibFiles] +LibFiles=Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rng.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f746xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\system_stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c; + +[] +SourceFiles=;; + +[PreviousGenFiles] +HeaderPath=..\Inc +HeaderFiles=stm32f7xx_it.h;stm32f7xx_hal_conf.h;main.h; +SourcePath=..\Src +SourceFiles=stm32f7xx_it.c;stm32f7xx_hal_msp.c;main.c; + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h new file mode 100644 index 00000000..280da443 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h new file mode 100644 index 00000000..21c37deb --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h @@ -0,0 +1,484 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f7xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)15U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define ART_ACCELERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE 1524 /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32f7xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h new file mode 100644 index 00000000..8ee5240e --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h @@ -0,0 +1,63 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_IT_H +#define __STM32F7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void DebugMon_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_IT_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc new file mode 100644 index 00000000..780345ba --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc @@ -0,0 +1,178 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +ETH.IPParameters=MediaInterface +ETH.MediaInterface=HAL_ETH_RMII_MODE +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.CPN=STM32F746ZGT6 +Mcu.Family=STM32F7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=ETH +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=RNG +Mcu.IP5=SYS +Mcu.IP6=USART3 +Mcu.IPNb=7 +Mcu.Name=STM32F746ZGTx +Mcu.Package=LQFP144 +Mcu.Pin0=PC1 +Mcu.Pin1=PA1 +Mcu.Pin10=PG13 +Mcu.Pin11=PB7 +Mcu.Pin12=VP_RNG_VS_RNG +Mcu.Pin13=VP_SYS_VS_Systick +Mcu.Pin2=PA2 +Mcu.Pin3=PA7 +Mcu.Pin4=PC4 +Mcu.Pin5=PC5 +Mcu.Pin6=PB13 +Mcu.Pin7=PD8 +Mcu.Pin8=PD9 +Mcu.Pin9=PG11 +Mcu.PinsNb=14 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F746ZGTx +MxCube.Version=6.8.0 +MxDb.Version=DB.6.0.80 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ETH_IRQn=true\:0\:0\:false\:false\:false\:true\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:false\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA1.Mode=RMII +PA1.Signal=ETH_REF_CLK +PA2.Mode=RMII +PA2.Signal=ETH_MDIO +PA7.Mode=RMII +PA7.Signal=ETH_CRS_DV +PB13.Mode=RMII +PB13.Signal=ETH_TXD1 +PB7.Locked=true +PB7.Signal=GPIO_Output +PC1.Mode=RMII +PC1.Signal=ETH_MDC +PC4.Mode=RMII +PC4.Signal=ETH_RXD0 +PC5.Mode=RMII +PC5.Signal=ETH_RXD1 +PD8.Locked=true +PD8.Mode=Asynchronous +PD8.Signal=USART3_TX +PD9.Locked=true +PD9.Mode=Asynchronous +PD9.Signal=USART3_RX +PG11.Locked=true +PG11.Mode=RMII +PG11.Signal=ETH_TX_EN +PG13.Locked=true +PG13.Mode=RMII +PG13.Signal=ETH_TXD0 +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F746ZGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.17.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=2 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=true +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=STCubeGenerated.ioc +ProjectManager.ProjectName=STCubeGenerated +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_RNG_Init-RNG-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.AHBFreq_Value=216000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=54000000 +RCC.APB1TimFreq_Value=108000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=108000000 +RCC.APB2TimFreq_Value=216000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=216000000 +RCC.EthernetFreq_Value=216000000 +RCC.FCLKCortexFreq_Value=216000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=216000000 +RCC.HSE_VALUE=25000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=54000000 +RCC.I2C2Freq_Value=54000000 +RCC.I2C3Freq_Value=54000000 +RCC.I2C4Freq_Value=54000000 +RCC.I2SFreq_Value=192000000 +RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value +RCC.LCDTFToutputFreq_Value=96000000 +RCC.LPTIM1Freq_Value=54000000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=216000000 +RCC.PLLCLKFreq_Value=216000000 +RCC.PLLI2SPCLKFreq_Value=192000000 +RCC.PLLI2SQCLKFreq_Value=192000000 +RCC.PLLI2SRCLKFreq_Value=192000000 +RCC.PLLI2SRoutputFreq_Value=192000000 +RCC.PLLM=8 +RCC.PLLN=216 +RCC.PLLQ=9 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLQoutputFreq_Value=48000000 +RCC.PLLSAIPCLKFreq_Value=192000000 +RCC.PLLSAIQCLKFreq_Value=192000000 +RCC.PLLSAIRCLKFreq_Value=192000000 +RCC.PLLSAIoutputFreq_Value=192000000 +RCC.RNGFreq_Value=48000000 +RCC.SAI1Freq_Value=192000000 +RCC.SAI2Freq_Value=192000000 +RCC.SDMMCFreq_Value=216000000 +RCC.SPDIFRXFreq_Value=192000000 +RCC.SYSCLKFreq_VALUE=216000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=54000000 +RCC.UART5Freq_Value=54000000 +RCC.UART7Freq_Value=54000000 +RCC.UART8Freq_Value=54000000 +RCC.USART1Freq_Value=108000000 +RCC.USART2Freq_Value=54000000 +RCC.USART3Freq_Value=54000000 +RCC.USART6Freq_Value=108000000 +RCC.USBFreq_Value=48000000 +RCC.VCOI2SOutputFreq_Value=384000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutputFreq_Value=432000000 +RCC.VCOSAIOutputFreq_Value=384000000 +USART3.IPParameters=VirtualMode-Asynchronous +USART3.VirtualMode-Asynchronous=VM_ASYNC +VP_RNG_VS_RNG.Mode=RNG_Activate +VP_RNG_VS_RNG.Signal=RNG_VS_RNG +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c new file mode 100644 index 00000000..a8611c5c --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c @@ -0,0 +1,329 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "string.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma location=0x2004c000 +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +#pragma location=0x2004c0a0 +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __CC_ARM ) /* MDK ARM Compiler */ + +__attribute__((at(0x2004c000))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +__attribute__((at(0x2004c0a0))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __GNUC__ ) /* GNU Compiler */ +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */ +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection"))); /* Ethernet Tx DMA Descriptors */ + +#endif + +ETH_TxPacketConfig TxConfig; + +ETH_HandleTypeDef heth; + +RNG_HandleTypeDef hrng; + +UART_HandleTypeDef huart3; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART3_UART_Init(void); +static void MX_ETH_Init(void); +static void MX_RNG_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +void mx_init(void) { + SystemClock_Config(); + MX_GPIO_Init(); + MX_USART3_UART_Init(); + MX_RNG_Init(); + MX_ETH_Init(); +} + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 216; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ETH Initialization Function + * @param None + * @retval None + */ +static void MX_ETH_Init(void) +{ + + /* USER CODE BEGIN ETH_Init 0 */ + + /* USER CODE END ETH_Init 0 */ + + static uint8_t MACAddr[6]; + + /* USER CODE BEGIN ETH_Init 1 */ + + /* USER CODE END ETH_Init 1 */ + heth.Instance = ETH; + MACAddr[0] = 0x00; + MACAddr[1] = 0x80; + MACAddr[2] = 0xE1; + MACAddr[3] = 0x00; + MACAddr[4] = 0x00; + MACAddr[5] = 0x00; + heth.Init.MACAddr = &MACAddr[0]; + heth.Init.MediaInterface = HAL_ETH_RMII_MODE; + heth.Init.TxDesc = DMATxDscrTab; + heth.Init.RxDesc = DMARxDscrTab; + heth.Init.RxBuffLen = 1524; + + /* USER CODE BEGIN MACADDRESS */ + + /* USER CODE END MACADDRESS */ + + if (HAL_ETH_Init(&heth) != HAL_OK) + { + Error_Handler(); + } + + memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig)); + TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; + TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; + TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; + /* USER CODE BEGIN ETH_Init 2 */ + + /* USER CODE END ETH_Init 2 */ + +} + +/** + * @brief RNG Initialization Function + * @param None + * @retval None + */ +static void MX_RNG_Init(void) +{ + + /* USER CODE BEGIN RNG_Init 0 */ + + /* USER CODE END RNG_Init 0 */ + + /* USER CODE BEGIN RNG_Init 1 */ + + /* USER CODE END RNG_Init 1 */ + hrng.Instance = RNG; + if (HAL_RNG_Init(&hrng) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RNG_Init 2 */ + + /* USER CODE END RNG_Init 2 */ + +} + +/** + * @brief USART3 Initialization Function + * @param None + * @retval None + */ +static void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET); + + /*Configure GPIO pin : PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c new file mode 100644 index 00000000..cff0eb5b --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c @@ -0,0 +1,326 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ETH MSP Initialization +* This function configures the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspInit 0 */ + + /* USER CODE END ETH_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ETH_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* ETH interrupt Init */ + HAL_NVIC_SetPriority(ETH_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspInit 1 */ + + /* USER CODE END ETH_MspInit 1 */ + } + +} + +/** +* @brief ETH MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspDeInit 0 */ + + /* USER CODE END ETH_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11|GPIO_PIN_13); + + /* ETH interrupt DeInit */ + HAL_NVIC_DisableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspDeInit 1 */ + + /* USER CODE END ETH_MspDeInit 1 */ + } + +} + +/** +* @brief RNG MSP Initialization +* This function configures the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspInit 0 */ + + /* USER CODE END RNG_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_RNG_CLK_ENABLE(); + /* USER CODE BEGIN RNG_MspInit 1 */ + + /* USER CODE END RNG_MspInit 1 */ + } + +} + +/** +* @brief RNG MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspDeInit 0 */ + + /* USER CODE END RNG_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RNG_CLK_DISABLE(); + /* USER CODE BEGIN RNG_MspDeInit 1 */ + + /* USER CODE END RNG_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; + PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9); + + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c new file mode 100644 index 00000000..e7760fd5 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c @@ -0,0 +1,163 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M7 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f7xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s new file mode 100644 index 00000000..9286c004 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s @@ -0,0 +1,468 @@ +;******************************************************************************* +;* File Name : startup_stm32f746xx.s +;* Author : MCD Application Team +;* Description : STM32F746xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2016 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000800 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000800 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c new file mode 100644 index 00000000..32e7fa5f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c @@ -0,0 +1,259 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS RAMDTCM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/project.script b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/project.script new file mode 100644 index 00000000..0f10b399 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Device/project.script @@ -0,0 +1,7 @@ +load STM32F746ZGTx +project name STCubeGenerated +project toolchain "MDK-ARM V5" +project path "C:\Users\scaprile\Documents\Keil\nucleo-f746zg-keil-baremetal\RTE\Device\STM32F746ZGTx\" +set tpl_path "C:\Users\scaprile\AppData\Local\Arm\Packs\Keil\STM32F7xx_DFP\2.15.1\MDK\CubeMX" +set dest_path "STM32F746ZGTx" +SetCopyLibrary "copy as reference" diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Network/ethif_config.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Network/ethif_config.h new file mode 100644 index 00000000..5f7ba64f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Network/ethif_config.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ETHIF_CONFIG_H +#define ETHIF_CONFIG_H + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Connect to hardware via Driver_ETH# <0-255> +// Select driver control block for MAC and PHY interface +#define ETH_DRV_NUM 0 + +// Ethernet MAC Address +// MAC Address byte 1 <0x00-0xff> +#define MAC_ADDR0 0x02 + +// MAC Address byte 2 <0x00-0xff> +#define MAC_ADDR1 0x00 + +// MAC Address byte 3 <0x00-0xff> +#define MAC_ADDR2 0x00 + +// MAC Address byte 4 <0x00-0xff> +#define MAC_ADDR3 0x00 + +// MAC Address byte 4 <0x00-0xff> +#define MAC_ADDR4 0x00 + +// MAC Address byte 4 <0x00-0xff> +#define MAC_ADDR5 0x00 +// + +//------------- <<< end of configuration section >>> --------------------------- + +#endif diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Network/lwipopts.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Network/lwipopts.h new file mode 100644 index 00000000..98aa9d38 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Network/lwipopts.h @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef LWIP_LWIPOPTS_H +#define LWIP_LWIPOPTS_H + +/* Options managed by RTE */ +#include "lwipopts_rte.h" + +/* See "lwip/opt.h" for all available configuration options */ + +/* + ------------------------------------ + -------------- NO SYS -------------- + ------------------------------------ +#define NO_SYS managed by RTE +#define LWIP_TIMERS managed by RTE +#define SYS_LIGHTWEIGHT_PROT managed by RTE +*/ + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +#define MEM_LIBC_MALLOC 0 +#define MEMP_MEM_MALLOC 1 +#define MEMP_MEM_INIT 0 +#define MEM_ALIGNMENT 4 +#define MEM_SIZE (10*1024) +#define MEMP_OVERFLOW_CHECK 0 +#define MEMP_SANITY_CHECK 0 +#define MEM_OVERFLOW_CHECK 0 +#define MEM_SANITY_CHECK 0 + +/* ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ + */ +#define MEMP_NUM_PBUF 10 +#define MEMP_NUM_RAW_PCB 4 +#define MEMP_NUM_UDP_PCB 6 +#define MEMP_NUM_TCP_PCB 10 +#define MEMP_NUM_TCP_PCB_LISTEN 6 +#define MEMP_NUM_TCP_SEG 12 +#define MEMP_NUM_REASSDATA 16 +#define MEMP_NUM_FRAG_PBUF 15 +#define MEMP_NUM_ARP_QUEUE 10 +#define MEMP_NUM_IGMP_GROUP 8 +#define MEMP_NUM_NETBUF 2 +#define MEMP_NUM_NETCONN 10 +#define MEMP_NUM_SELECT_CB 4 +#define MEMP_NUM_TCPIP_MSG_API 8 +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#define MEMP_NUM_NETDB 1 +#define MEMP_NUM_LOCALHOSTLIST 1 +#define PBUF_POOL_SIZE 16 + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +#define LWIP_ETHERNET managed by RTE +*/ +#define LWIP_ARP 1 +#define ARP_TABLE_SIZE 10 +#define ETHARP_SUPPORT_VLAN 0 +#define ETH_PAD_SIZE 2 +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +#define LWIP_IPV4 managed by RTE +*/ +#define IP_FORWARD 0 +#define IP_REASSEMBLY 1 +#define IP_FRAG 1 +#define IP_OPTIONS_ALLOWED 1 +#define IP_REASS_MAX_PBUFS 10 +#define IP_DEFAULT_TTL 128 +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +#define LWIP_ICMP 1 + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +#define LWIP_RAW 1 + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +#define LWIP_DHCP 1 +#define LWIP_DHCP_CHECK_LINK_UP 0 +#define LWIP_DHCP_BOOTP_FILE 0 +#define LWIP_DHCP_GET_NTP_SRV 0 +#define LWIP_DHCP_MAX_NTP_SERVERS 1 + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +#define LWIP_AUTOIP 0 +#define LWIP_DHCP_AUTOIP_COOP 0 +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +#define LWIP_IGMP 0 + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +#define LWIP_DNS 0 +#define DNS_TABLE_SIZE 4 +#define DNS_MAX_NAME_LENGTH 256 + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +#define LWIP_UDP 1 +#define LWIP_UDPLITE 0 + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +#define LWIP_TCP 1 +#define TCP_QUEUE_OOSEQ 0 +#define LWIP_TCP_SACK_OUT 0 +#define LWIP_TCP_MAX_SACK_NUM 4 +#define TCP_MSS 1460 +#define TCP_OOSEQ_MAX_BYTES 0 +#define TCP_OOSEQ_MAX_PBUFS 0 +#define TCP_LISTEN_BACKLOG 1 +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#define LWIP_WND_SCALE 0 +#define TCP_RCV_SCALE 0 +#define LWIP_TCP_PCB_NUM_EXT_ARGS 0 +#define LWIP_ALTCP 0 +#define LWIP_ALTCP_TLS 0 + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +#define PBUF_LINK_ENCAPSULATION_HLEN 0 + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +#define LWIP_SINGLE_NETIF 0 +#define LWIP_NETIF_HOSTNAME 0 +#define LWIP_NETIF_API 0 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_EXT_STATUS_CALLBACK 0 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define LWIP_NETIF_REMOVE_CALLBACK 0 +#define LWIP_NETIF_HWADDRHINT 1 + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +#define LWIP_HAVE_LOOPIF 0 +#define LWIP_LOOPIF_MULTICAST 0 +#define LWIP_NETIF_LOOPBACK 0 +#define LWIP_LOOPBACK_MAX_PBUFS 0 + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +#define TCPIP_THREAD_NAME "tcpip_thread" +#define TCPIP_THREAD_STACKSIZE 1024 +#define TCPIP_THREAD_PRIO (configMAX_PRIORITIES - 1) +#define TCPIP_MBOX_SIZE 6 +#define SLIPIF_THREAD_NAME "slipif_loop" +#define SLIPIF_THREAD_STACKSIZE 0 +#define SLIPIF_THREAD_PRIO 1 +#define DEFAULT_THREAD_NAME "lwIP" +#define DEFAULT_THREAD_STACKSIZE 1024 +#define DEFAULT_THREAD_PRIO (configMAX_PRIORITIES - 1) +#define DEFAULT_RAW_RECVMBOX_SIZE 6 +#define DEFAULT_UDP_RECVMBOX_SIZE 6 +#define DEFAULT_TCP_RECVMBOX_SIZE 6 +#define DEFAULT_ACCEPTMBOX_SIZE 6 + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +#define LWIP_NETCONN 0 +#define LWIP_TCPIP_TIMEOUT 1 +#define LWIP_NETCONN_SEM_PER_THREAD 0 +#define LWIP_NETCONN_FULLDUPLEX 0 + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +#define LWIP_SOCKET 1 +#define LWIP_COMPAT_SOCKETS 1 +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#define LWIP_TCP_KEEPALIVE 1 +#define LWIP_SO_SNDTIMEO 0 +#define LWIP_SO_RCVTIMEO 0 +#define LWIP_SO_SNDRCVTIMEO_NONSTANDARD 0 +#define LWIP_SO_RCVBUF 0 +#define LWIP_SO_LINGER 0 +#define SO_REUSE 0 +#define SO_REUSE_RXTOALL 0 +#define LWIP_SOCKET_SELECT 1 +#define LWIP_SOCKET_POLL 1 + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +#define LWIP_STATS 0 + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +#define LWIP_CHECKSUM_CTRL_PER_NETIF 0 + +/* + --------------------------------------- + ---------- IPv6 options --------------- + --------------------------------------- +#define LWIP_IPV6 managed by RTE +*/ +#define LWIP_IPV6_FORWARD 0 +#define LWIP_IPV6_FRAG 1 +#define LWIP_IPV6_REASS 1 +#define LWIP_IPV6_AUTOCONFIG 1 +#define LWIP_ICMP6 1 +#define LWIP_IPV6_MLD 0 +#define MEMP_NUM_MLD6_GROUP 4 +#define LWIP_ND6_NUM_NEIGHBORS 10 +#define LWIP_ND6_NUM_DESTINATIONS 10 +#define LWIP_ND6_NUM_PREFIXES 5 +#define LWIP_ND6_NUM_ROUTERS 3 +#define LWIP_ND6_ALLOW_RA_UPDATES 1 +#define LWIP_ND6_TCP_REACHABILITY_HINTS 1 +#define LWIP_IPV6_DHCP6 0 +#define LWIP_IPV6_DHCP6_STATEFUL 0 +#define LWIP_IPV6_DHCP6_STATELESS 1 +#define LWIP_DHCP6_GET_NTP_SRV 0 +#define LWIP_DHCP6_MAX_NTP_SERVERS 1 + +#endif /* LWIP_LWIPOPTS_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Network_Library/mongoose_custom.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Network_Library/mongoose_custom.h new file mode 100644 index 00000000..8e245b97 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/Network_Library/mongoose_custom.h @@ -0,0 +1,77 @@ + +// <<< Use Configuration Wizard in Context Menu >>> + +// System Architecture +// <0=> Bare metal +// <1=> FreeRTOS +// <2=> CMSIS-RTOS v1 +// <3=> CMSIS-RTOS v2 +// Select either bare metal operation or a supported RTOS +// "FreeRTOS" uses direct FreeRTOS calls +// "CMSIS-RTOS v1" supports only Keil RTX through API v1 +// "CMSIS-RTOS v2" supports Keil RTX5 and FreeRTOS through API v2 + +#define MG_CMSISPACK_ARCH 1 + + +// Networking support +// Networking stack +// <0=> Built-in +// <1=> lwIP +// <2=> FreeRTOS-Plus-TCP +// <3=> MDK (RL) +// Select the networking stack to use with Mongoose Library +// The built-in stack can run on bare metal or over any RTOS +// "lwIP" requires using an RTOS and BSD socket mode +// "MDK" requires using CMSIS-RTOS1 (RTX + RL) or CMSIS-RTOS2 (MDK Plus or Pro), and BSD socket mode +#define MG_CMSISPACK_NET 1 + +// Use Mbed-TLS +// Mongoose will use Mbed-TLS calls for TLS-related functionality +#define MG_ENABLE_MBEDTLS 0 +// + + +// Enable custom mg_millis() +// Use a user-provided function to get uptime in milliseconds, otherwise Mongoose will default to using time(). Except for bare metal, Mongoose will use the time base for the configured architecture +//#define MG_ENABLE_CUSTOM_MILLIS 1 +// + + +// Enable custom mg_rand() +// Use a user-provided function to generate random numbers, otherwise Mongoose will default to using rand() +#define MG_ENABLE_CUSTOM_RANDOM 1 +// + + +// Filesystem support +// Enable packed (embedded) filesystem +#define MG_ENABLE_PACKED_FS 1 +// + + +// <<< end of configuration section >>> + +// Translate to Mongoose macros +#if MG_CMSISPACK_ARCH == 1 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_FREERTOS +#elif MG_CMSISPACK_ARCH == 2 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_CMSIS_RTOS1 +#elif MG_CMSISPACK_ARCH == 3 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_CMSIS_RTOS2 +#endif +#if MG_CMSISPACK_NET == 0 +#define MG_ENABLE_TCPIP 1 +#elif MG_CMSISPACK_NET == 1 +#define MG_ENABLE_LWIP 1 +#elif MG_CMSISPACK_NET == 2 +#define MG_ENABLE_FREERTOS_TCP 1 +#elif MG_CMSISPACK_NET == 3 +#define MG_ENABLE_RL 1 +#endif + + +// Add your customization below this comment diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/RTOS/FreeRTOSConfig.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/RTOS/FreeRTOSConfig.h new file mode 100644 index 00000000..d4b0187d --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/RTOS/FreeRTOSConfig.h @@ -0,0 +1,166 @@ +/* + * FreeRTOS Kernel V10.4.0 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +#if (defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)) +#include + +extern uint32_t SystemCoreClock; +#endif + +/* Constants that describe the hardware and memory usage. */ +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configTOTAL_HEAP_SIZE ((size_t)1024 * 128) +#define configMINIMAL_STACK_SIZE ((uint16_t)256) +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configSUPPORT_STATIC_ALLOCATION 0 + +/* Constants related to the behaviour or the scheduler. */ +#define configMAX_PRIORITIES 5 +#define configUSE_PREEMPTION 1 +#define configUSE_TIME_SLICING 1 +#define configIDLE_SHOULD_YIELD 1 +#define configMAX_TASK_NAME_LEN (10) +#define configUSE_16_BIT_TICKS 0 + +/* Software timer definitions. */ +#define configUSE_TIMERS 0 +#define configTIMER_TASK_PRIORITY 2 +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Constants that build features in or out. */ +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_TICKLESS_IDLE 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configUSE_CO_ROUTINES 0 + +/* Constants provided for debugging and optimisation assistance. */ +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configQUEUE_REGISTRY_SIZE 0 +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Constants that define which hook (callback) functions should be used. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 + +/* Port specific configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_MVE 0 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ((uint32_t)1024) +#define configRUN_FREERTOS_SECURE_ONLY 0 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __NVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + // CMSIS headers are not being pulled with this file + #define configPRIO_BITS 4 +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 + +/* The highest interrupt priority that can be used by any interrupt service + * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT + * CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A + * HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic + * to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! + * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is + * only necessary if the linker does not automatically remove functions that are + * not referenced anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_xTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xQueueGetMutexHolder 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_uxTaskGetStackHighWaterMark2 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 + +/* Map the FreeRTOS port interrupt handlers to their CMSIS standard names. */ +#define xPortPendSVHandler PendSV_Handler +#define vPortSVCHandler SVC_Handler +// We'll handle SysTick_Handler and call xPortSysTickHandler ourselves, like CMSIS-RTOS2 + +// Make lwIP happy +#define configUSE_POSIX_ERRNO 1 +#define configPRINTF printf // -Wno-format-security + +#if (defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)) +/* Include debug event definitions */ +#include "freertos_evr.h" +#endif + +#endif /* FREERTOS_CONFIG_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/_Target_1/Pre_Include_Global.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/_Target_1/Pre_Include_Global.h new file mode 100644 index 00000000..8aabd0e0 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/_Target_1/Pre_Include_Global.h @@ -0,0 +1,17 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'device-dashboard' + * Target: 'Target 1' + */ + +#ifndef PRE_INCLUDE_GLOBAL_H +#define PRE_INCLUDE_GLOBAL_H + +/* Keil::Device:STM32Cube HAL:Common:1.3.0 */ +#define USE_HAL_DRIVER + + +#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/_Target_1/RTE_Components.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/_Target_1/RTE_Components.h new file mode 100644 index 00000000..72a1a25d --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/RTE/_Target_1/RTE_Components.h @@ -0,0 +1,68 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'device-dashboard' + * Target: 'Target 1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f7xx.h" + +/* ARM.FreeRTOS::RTOS:Config:FreeRTOS:10.5.1 */ +#define RTE_RTOS_FreeRTOS_CONFIG /* RTOS FreeRTOS Config for FreeRTOS API */ +/* ARM.FreeRTOS::RTOS:Core:Cortex-M:10.5.1 */ +#define RTE_RTOS_FreeRTOS_CORE /* RTOS FreeRTOS Core */ +/* ARM.FreeRTOS::RTOS:Heap:Heap_4:10.5.1 */ +#define RTE_RTOS_FreeRTOS_HEAP_4 /* RTOS FreeRTOS Heap 4 */ +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:User:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ +/* Keil::CMSIS Driver:Ethernet MAC:1.12.0 */ +#define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */ +/* Keil::CMSIS Driver:Ethernet PHY:LAN8742A:1.3.0 */ +#define RTE_Drivers_PHY_LAN8742A /* Driver PHY LAN8742A */ +/* Keil::Device:STM32Cube Framework:STM32CubeMX:1.1.0 */ +#define RTE_DEVICE_FRAMEWORK_CUBE_MX +/* Keil::Device:STM32Cube HAL:Common:1.3.0 */ +#define RTE_DEVICE_HAL_COMMON +/* Keil::Device:STM32Cube HAL:Cortex:1.3.0 */ +#define RTE_DEVICE_HAL_CORTEX +/* Keil::Device:STM32Cube HAL:DMA:1.3.0 */ +#define RTE_DEVICE_HAL_DMA +/* Keil::Device:STM32Cube HAL:ETH:1.3.0 */ +#define RTE_DEVICE_HAL_ETH +/* Keil::Device:STM32Cube HAL:GPIO:1.3.0 */ +#define RTE_DEVICE_HAL_GPIO +/* Keil::Device:STM32Cube HAL:PWR:1.3.0 */ +#define RTE_DEVICE_HAL_PWR +/* Keil::Device:STM32Cube HAL:RCC:1.3.0 */ +#define RTE_DEVICE_HAL_RCC +/* Keil::Device:STM32Cube HAL:RNG:1.3.0 */ +#define RTE_DEVICE_HAL_RNG +/* Keil::Device:STM32Cube HAL:UART:1.3.0 */ +#define RTE_DEVICE_HAL_UART +/* Keil::Device:Startup:1.2.5 */ +#define RTE_DEVICE_STARTUP_STM32F7XX /* Device Startup for STM32F7 */ +/* lwIP.lwIP::Network:API:2.2.0 */ +#define RTE_Network_API /* Network API */ +/* lwIP.lwIP::Network:CORE:IPv4:2.2.0 */ +#define RTE_Network_Core /* Network Core */ + #define RTE_Network_IPv4 /* Network IPv4 Stack */ +/* lwIP.lwIP::Network:Driver:Ethernet:CMSIS Driver:2.2.0 */ +#define RTE_Network_Driver_Ethernet /* Network Driver Ethernet */ +/* lwIP.lwIP::Network:Interface:Ethernet:2.2.0 */ +#define RTE_Network_Interface_Ethernet /* Network Interface Ethernet */ +/* lwIP.lwIP::Network:RTOS:FreeRTOS:2.2.0 */ +#define RTE_Network_RTOS /* Network RTOS */ + #define RTE_Network_FreeRTOS /* Network FreeRTOS */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/device-dashboard.uvguix b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/device-dashboard.uvguix new file mode 100644 index 00000000..d300e350 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/device-dashboard.uvguix @@ -0,0 +1,3711 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/device-dashboard.uvoptx @@ -0,0 +1,407 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 16000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ST-LINKIII-KEIL_SWO + -U066BFF514982494867132513 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(5BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FF1STM32F7xTCM_1024.FLM -FS1200000 -FL1100000 -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + + + + + + 0 + 1 + s_netif + + + 1 + 1 + eth0_status + + + + + 1 + 0 + 0x20010850 + 0 + + + + C:\Users\scaprile\AppData\Local\Arm\Packs\ARM\CMSIS-FreeRTOS\10.5.1\CMSIS\RTOS2\FreeRTOS\FreeRTOS.scvd + ARM.CMSIS-FreeRTOS.10.5.1 + 1 + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + OS Support\Event Viewer + 35904 + + + OS Support\System and Thread Viewer + 35905 + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 1 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + .\hal.h + hal.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + .\net.c + net.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + .\packed_fs.c + packed_fs.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + .\syscalls.c + syscalls.c + 0 + 0 + + + + + :STM32CubeMX:Common Sources + 0 + 0 + 0 + 0 + + 2 + 6 + 1 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + main.c + 0 + 0 + + + 2 + 7 + 5 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Inc\stm32f7xx_it.h + stm32f7xx_it.h + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + stm32f7xx_it.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::CMSIS Driver + 0 + 0 + 0 + 1 + + + + ::Compiler + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + + ::Network + 1 + 0 + 0 + 1 + + + + ::Network Library + 1 + 0 + 0 + 1 + + + + ::RTOS + 1 + 0 + 0 + 1 + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/device-dashboard.uvprojx b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/device-dashboard.uvprojx new file mode 100644 index 00000000..a2c3349f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/device-dashboard.uvprojx @@ -0,0 +1,678 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + STM32F746ZGTx + STMicroelectronics + Keil.STM32F7xx_DFP.2.15.1 + https://www.keil.com/pack/ + IRAM(0x20010000,0x40000) IRAM2(0x20000000,0x10000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + 0 + $$Device:STM32F746ZGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h + + + + + + + + + + $$Device:STM32F746ZGTx$CMSIS\SVD\STM32F746.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + device-dashboard + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x200000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 6 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + + -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion -Wno-unused-parameter -Wconversion -Wno-sign-conversion -Wno-implicit-int-conversion -Wno-format-security -fno-common -fdata-sections + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20010000 + + + + + --diag_suppress 6918 + + + + + + + + Source Group 1 + + + hal.h + 5 + .\hal.h + + + main.c + 1 + .\main.c + + + net.c + 1 + .\net.c + + + packed_fs.c + 1 + .\packed_fs.c + + + syscalls.c + 1 + .\syscalls.c + + + + + :STM32CubeMX:Common Sources + + + main.c + 1 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + + + stm32f7xx_it.h + 5 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Inc\stm32f7xx_it.h + + + stm32f7xx_it.c + 1 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + + + + + ::CMSIS + + + ::CMSIS Driver + + + ::Compiler + + + ::Device + + + ::Network + + + ::Network Library + + + ::RTOS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\STM32F746ZGTx\startup_stm32f746xx.s + + + + + + + + RTE\Device\STM32F746ZGTx\system_stm32f7xx.c + + + + + + + + RTE\Network\ethif_config.h + + + + + + + + RTE\Network\lwipopts.h + + + + + + + + RTE\Network_Library\mongoose_custom.h + + + + + + + + RTE\RTOS\FreeRTOSConfig.h + + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/hal.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/hal.h new file mode 100644 index 00000000..0516da74 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/hal.h @@ -0,0 +1,11 @@ +// Copyright (c) 2022-23 Cesanta Software Limited +// All rights reserved +// https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf + +#pragma once + +#include + +#ifndef UART_DEBUG +#define UART_DEBUG USART3 +#endif diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/main.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/main.c new file mode 100644 index 00000000..ddf32126 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/main.c @@ -0,0 +1,101 @@ +// Copyright (c) 2023 Cesanta Software Limited +// All rights reserved + +#include "hal.h" +#include "mongoose.h" +#include "main.h" +#include "ethernetif.h" +#include "lwip/dhcp.h" +#include "lwip/netif.h" +#include "lwip/tcpip.h" + +#define BLINK_PERIOD_MS 1000 // LED blinking period in millis + + +extern void xPortSysTickHandler(void); +void SysTick_Handler (void) { + HAL_IncTick(); + // xPortSysTickHandler() must be called after vTaskStartScheduler() and mx_init() takes longer than 1ms + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) + xPortSysTickHandler(); +} + +void mg_random(void *buf, size_t len) { // Use on-board RNG + extern RNG_HandleTypeDef hrng; + for (size_t n = 0; n < len; n += sizeof(uint32_t)) { + uint32_t r; + HAL_RNG_GenerateRandomNumber(&hrng, &r); + memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r)); + } +} + +static void server(void *args) { + struct mg_mgr mgr; // Initialise Mongoose event manager + mg_mgr_init(&mgr); // and attach it to the interface + mg_log_set(MG_LL_DEBUG); // Set log level + + MG_INFO(("Initialising application...")); + extern void device_dashboard_fn(struct mg_connection *, int, void *, void *); + mg_http_listen(&mgr, "http://0.0.0.0", device_dashboard_fn, NULL); + + MG_INFO(("Starting event loop")); + for (;;) mg_mgr_poll(&mgr, 1000); // Infinite event loop + (void) args; +} + +static void blinker(void *args) { + for (;;) { + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_7); // Blink On-board blue LED + vTaskDelay(pdMS_TO_TICKS(BLINK_PERIOD_MS)); + } + (void) args; +} + + +static void netw(void *args) { + struct netif *netif = (struct netif *) args; + for (;;) { + ethernetif_check_link(netif); + ethernetif_poll(netif); + } +} + +static void netw_init (struct netif *netif) { + ip4_addr_t ipaddr, netmask, gw; + tcpip_init(NULL, NULL); + ipaddr.addr = IPADDR_ANY; // otherwise, set your static configuration + netmask.addr = IPADDR_ANY; + gw.addr = IPADDR_ANY; + netif_add(netif, &ipaddr, &netmask, &gw, NULL, ðernetif_init, &tcpip_input); + netif_set_default(netif); + netif_set_up(netif); + dhcp_start(netif); // remove for static configuration +} + +static struct netif s_netif; + +static void app_main (void *args) { + netw_init(&s_netif); + xTaskCreate(netw, "netw", 128, &s_netif, configMAX_PRIORITIES - 1, NULL); // Create the Ethernet link/rx thread + MG_INFO(("Waiting for IP...")); + while(ip4_addr_isany_val(*netif_ip4_addr(&s_netif))) + vTaskDelay(pdMS_TO_TICKS(200)); + MG_INFO(("READY, IP: %s", ip4addr_ntoa(netif_ip4_addr(&s_netif)))); + + xTaskCreate(server, "server", 2048, 0, configMAX_PRIORITIES - 1, NULL); + vTaskDelete(NULL); + (void)args; +} + +extern void mx_init(void); + +int main(void) { + mx_init(); // Setup clock and all peripherals configured in CubeMX + // Initialise random number generator + // Initialise ethernet pins + // Start tasks. NOTE: stack sizes are in 32-bit words + xTaskCreate(blinker, "blinker", 128, ":)", configMAX_PRIORITIES - 1, NULL); + xTaskCreate(app_main, "app_main", 128, 0, configMAX_PRIORITIES - 1, NULL); + vTaskStartScheduler(); // This blocks + return 0; +} diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/syscalls.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/syscalls.c new file mode 100644 index 00000000..79113968 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-lwip/syscalls.c @@ -0,0 +1,10 @@ +#include +#include + +#include "main.h" + +int stdout_putchar (int ch) { + extern UART_HandleTypeDef huart3; + HAL_UART_Transmit(&huart3, (const uint8_t *)&ch, 1, 100); + return ch; +} diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-tcp/EventRecorderStub.scvd b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-tcp/EventRecorderStub.scvd new file mode 100644 index 00000000..0fb3ee58 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-tcp/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-tcp/FreeRTOSIPConfig.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-tcp/FreeRTOSIPConfig.h new file mode 100644 index 00000000..cb19ae8f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-tcp/FreeRTOSIPConfig.h @@ -0,0 +1,336 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + + +/***************************************************************************** + * + * See the following URL for configuration information. + * https://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_TCP/TCP_IP_Configuration.html + * + *****************************************************************************/ + +#ifndef FREERTOS_IP_CONFIG_H +#define FREERTOS_IP_CONFIG_H + +/* Prototype for the function used to print out. In this case it prints to the +console before the network is connected then a UDP port after the network has +connected. */ +extern void vLoggingPrintf( const char *pcFormatString, ... ); + + +/* Set to 1 to print out debug messages. If ipconfigHAS_DEBUG_PRINTF is set to +1 then FreeRTOS_debug_printf should be defined to the function used to print +out the debugging messages. */ +#define ipconfigHAS_DEBUG_PRINTF 0 + +#ifdef HEAP3 + #define xPortGetMinimumEverFreeHeapSize(x) 0 + #define xPortGetFreeHeapSize() 0 +#endif + +#if( ipconfigHAS_DEBUG_PRINTF == 1 ) +#include + #define FreeRTOS_debug_printf(X) \ + printf("%p->%s %d: ", \ + xTaskGetCurrentTaskHandle(), \ + __FUNCTION__, \ + __LINE__); \ + vLoggingPrintf X +#endif + +/* Set to 1 to print out non debugging messages, for example the output of the +FreeRTOS_netstat() command, and ping replies. If ipconfigHAS_PRINTF is set to 1 +then FreeRTOS_printf should be set to the function used to print out the +messages. */ +#define ipconfigHAS_PRINTF 0 +#if( ipconfigHAS_PRINTF == 1 ) +#include + #define FreeRTOS_printf(X) \ + printf("%p->%s %d: ", \ + xTaskGetCurrentTaskHandle(), \ + __FUNCTION__, \ + __LINE__); \ + vLoggingPrintf X +#endif + +/* Define the byte order of the target MCU (the MCU FreeRTOS+TCP is executing +on). Valid options are pdFREERTOS_BIG_ENDIAN and pdFREERTOS_LITTLE_ENDIAN. */ +#define ipconfigBYTE_ORDER pdFREERTOS_LITTLE_ENDIAN + +/* If the network card/driver includes checksum offloading (IP/TCP/UDP checksums) +then set ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM to 1 to prevent the software +stack repeating the checksum calculations. */ +#define ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM 1 + +/* Several API's will block until the result is known, or the action has been +performed, for example FreeRTOS_send() and FreeRTOS_recv(). The timeouts can be +set per socket, using setsockopt(). If not set, the times below will be +used as defaults. */ +#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME ( 5000 ) +#define ipconfigSOCK_DEFAULT_SEND_BLOCK_TIME ( 5000 ) + +/* Include support for LLMNR: Link-local Multicast Name Resolution +(non-Microsoft) */ +#define ipconfigUSE_LLMNR ( 0 ) + +/* Include support for NBNS: NetBIOS Name Service (Microsoft) */ +#define ipconfigUSE_NBNS ( 0 ) + +/* Include support for DNS caching. For TCP, having a small DNS cache is very +useful. When a cache is present, ipconfigDNS_REQUEST_ATTEMPTS can be kept low +and also DNS may use small timeouts. If a DNS reply comes in after the DNS +socket has been destroyed, the result will be stored into the cache. The next +call to FreeRTOS_gethostbyname() will return immediately, without even creating +a socket. */ +#define ipconfigUSE_DNS_CACHE ( 0 ) +#define ipconfigDNS_CACHE_NAME_LENGTH ( 16 ) +#define ipconfigDNS_CACHE_ENTRIES ( 4 ) +#define ipconfigDNS_REQUEST_ATTEMPTS ( 2 ) + +/* The IP stack executes it its own task (although any application task can make +use of its services through the published sockets API). ipconfigUDP_TASK_PRIORITY +sets the priority of the task that executes the IP stack. The priority is a +standard FreeRTOS task priority so can take any value from 0 (the lowest +priority) to (configMAX_PRIORITIES - 1) (the highest priority). +configMAX_PRIORITIES is a standard FreeRTOS configuration parameter defined in +FreeRTOSConfig.h, not FreeRTOSIPConfig.h. Consideration needs to be given as to +the priority assigned to the task executing the IP stack relative to the +priority assigned to tasks that use the IP stack. */ +#define ipconfigIP_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* The size, in words (not bytes), of the stack allocated to the FreeRTOS+TCP +task. This setting is less important when the FreeRTOS Win32 simulator is used +as the Win32 simulator only stores a fixed amount of information on the task +stack. FreeRTOS includes optional stack overflow detection, see: +http://www.freertos.org/Stacks-and-stack-overflow-checking.html */ +#define ipconfigIP_TASK_STACK_SIZE_WORDS ( configMINIMAL_STACK_SIZE * 5 ) + +/* ipconfigRAND32() is called by the IP stack to generate random numbers for +things such as a DHCP transaction number or initial sequence number. Random +number generation is performed via this macro to allow applications to use their +own random number generation method. For example, it might be possible to +generate a random number by sampling noise on an analogue input. */ +extern UBaseType_t uxRand(); +#define ipconfigRAND32() uxRand() + +/* If ipconfigUSE_NETWORK_EVENT_HOOK is set to 1 then FreeRTOS+TCP will call the +network event hook at the appropriate times. If ipconfigUSE_NETWORK_EVENT_HOOK +is not set to 1 then the network event hook will never be called. See +http://www.FreeRTOS.org/FreeRTOS-Plus/FreeRTOS_Plus_UDP/API/vApplicationIPNetworkEventHook.shtml +*/ +#define ipconfigUSE_NETWORK_EVENT_HOOK 1 + +/* Sockets have a send block time attribute. If FreeRTOS_sendto() is called but +a network buffer cannot be obtained then the calling task is held in the Blocked +state (so other tasks can continue to executed) until either a network buffer +becomes available or the send block time expires. If the send block time expires +then the send operation is aborted. The maximum allowable send block time is +capped to the value set by ipconfigMAX_SEND_BLOCK_TIME_TICKS. Capping the +maximum allowable send block time prevents prevents a deadlock occurring when +all the network buffers are in use and the tasks that process (and subsequently +free) the network buffers are themselves blocked waiting for a network buffer. +ipconfigMAX_SEND_BLOCK_TIME_TICKS is specified in RTOS ticks. A time in +milliseconds can be converted to a time in ticks by dividing the time in +milliseconds by portTICK_PERIOD_MS. */ +#define ipconfigUDP_MAX_SEND_BLOCK_TIME_TICKS ( 5000U / portTICK_PERIOD_MS ) + +/* If ipconfigUSE_DHCP is 1 then FreeRTOS+TCP will attempt to retrieve an IP +address, netmask, DNS server address and gateway address from a DHCP server. If +ipconfigUSE_DHCP is 0 then FreeRTOS+TCP will use a static IP address. The +stack will revert to using the static IP address even when ipconfigUSE_DHCP is +set to 1 if a valid configuration cannot be obtained from a DHCP server for any +reason. The static configuration used is that passed into the stack by the +FreeRTOS_IPInit() function call. */ +#define ipconfigUSE_DHCP 1 + +/* When ipconfigUSE_DHCP is set to 1, DHCP requests will be sent out at +increasing time intervals until either a reply is received from a DHCP server +and accepted, or the interval between transmissions reaches +ipconfigMAXIMUM_DISCOVER_TX_PERIOD. The IP stack will revert to using the +static IP address passed as a parameter to FreeRTOS_IPInit() if the +re-transmission time interval reaches ipconfigMAXIMUM_DISCOVER_TX_PERIOD without +a DHCP reply being received. */ +#define ipconfigMAXIMUM_DISCOVER_TX_PERIOD ( 120000U / portTICK_PERIOD_MS ) + +/* The ARP cache is a table that maps IP addresses to MAC addresses. The IP +stack can only send a UDP message to a remove IP address if it knowns the MAC +address associated with the IP address, or the MAC address of the router used to +contact the remote IP address. When a UDP message is received from a remote IP +address the MAC address and IP address are added to the ARP cache. When a UDP +message is sent to a remote IP address that does not already appear in the ARP +cache then the UDP message is replaced by a ARP message that solicits the +required MAC address information. ipconfigARP_CACHE_ENTRIES defines the maximum +number of entries that can exist in the ARP table at any one time. */ +#define ipconfigARP_CACHE_ENTRIES 6 + +/* ARP requests that do not result in an ARP response will be re-transmitted a +maximum of ipconfigMAX_ARP_RETRANSMISSIONS times before the ARP request is +aborted. */ +#define ipconfigMAX_ARP_RETRANSMISSIONS ( 5 ) + +/* ipconfigMAX_ARP_AGE defines the maximum time between an entry in the ARP +table being created or refreshed and the entry being removed because it is stale. +New ARP requests are sent for ARP cache entries that are nearing their maximum +age. ipconfigMAX_ARP_AGE is specified in tens of seconds, so a value of 150 is +equal to 1500 seconds (or 25 minutes). */ +#define ipconfigMAX_ARP_AGE 150 + +/* Implementing FreeRTOS_inet_addr() necessitates the use of string handling +routines, which are relatively large. To save code space the full +FreeRTOS_inet_addr() implementation is made optional, and a smaller and faster +alternative called FreeRTOS_inet_addr_quick() is provided. FreeRTOS_inet_addr() +takes an IP in decimal dot format (for example, "192.168.0.1") as its parameter. +FreeRTOS_inet_addr_quick() takes an IP address as four separate numerical octets +(for example, 192, 168, 0, 1) as its parameters. If +ipconfigINCLUDE_FULL_INET_ADDR is set to 1 then both FreeRTOS_inet_addr() and +FreeRTOS_indet_addr_quick() are available. If ipconfigINCLUDE_FULL_INET_ADDR is +not set to 1 then only FreeRTOS_indet_addr_quick() is available. */ +#define ipconfigINCLUDE_FULL_INET_ADDR 0 + +/* ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS defines the total number of network buffer that +are available to the IP stack. The total number of network buffers is limited +to ensure the total amount of RAM that can be consumed by the IP stack is capped +to a pre-determinable value. */ +#define ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS 60 + +/* A FreeRTOS queue is used to send events from application tasks to the IP +stack. ipconfigEVENT_QUEUE_LENGTH sets the maximum number of events that can +be queued for processing at any one time. The event queue must be a minimum of +5 greater than the total number of network buffers. */ +#define ipconfigEVENT_QUEUE_LENGTH ( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS + 5 ) + +/* The address of a socket is the combination of its IP address and its port +number. FreeRTOS_bind() is used to manually allocate a port number to a socket +(to 'bind' the socket to a port), but manual binding is not normally necessary +for client sockets (those sockets that initiate outgoing connections rather than +wait for incoming connections on a known port number). If +ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 1 then calling +FreeRTOS_sendto() on a socket that has not yet been bound will result in the IP +stack automatically binding the socket to a port number from the range +socketAUTO_PORT_ALLOCATION_START_NUMBER to 0xffff. If +ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND is set to 0 then calling FreeRTOS_sendto() +on a socket that has not yet been bound will result in the send operation being +aborted. */ +#define ipconfigALLOW_SOCKET_SEND_WITHOUT_BIND 1 + +/* Defines the Time To Live (TTL) values used in outgoing UDP packets. */ +#define ipconfigUDP_TIME_TO_LIVE 128 +#define ipconfigTCP_TIME_TO_LIVE 128 /* also defined in FreeRTOSIPConfigDefaults.h */ + +/* USE_TCP: Use TCP and all its features */ +#define ipconfigUSE_TCP ( 1 ) + +/* USE_WIN: Let TCP use windowing mechanism. */ +#define ipconfigUSE_TCP_WIN ( 1 ) + +/* The MTU is the maximum number of bytes the payload of a network frame can +contain. For normal Ethernet V2 frames the maximum MTU is 1500. Setting a +lower value can save RAM, depending on the buffer management scheme used. If +ipconfigCAN_FRAGMENT_OUTGOING_PACKETS is 1 then (ipconfigNETWORK_MTU - 28) must +be divisible by 8. */ +#define ipconfigNETWORK_MTU 1200U + +/* Set ipconfigUSE_DNS to 1 to include a basic DNS client/resolver. DNS is used +through the FreeRTOS_gethostbyname() API function. */ +#define ipconfigUSE_DNS 0 + +/* If ipconfigREPLY_TO_INCOMING_PINGS is set to 1 then the IP stack will +generate replies to incoming ICMP echo (ping) requests. */ +#define ipconfigREPLY_TO_INCOMING_PINGS 1 + +/* If ipconfigSUPPORT_OUTGOING_PINGS is set to 1 then the +FreeRTOS_SendPingRequest() API function is available. */ +#define ipconfigSUPPORT_OUTGOING_PINGS 0 + +/* If ipconfigSUPPORT_SELECT_FUNCTION is set to 1 then the FreeRTOS_select() +(and associated) API function is available. */ +#define ipconfigSUPPORT_SELECT_FUNCTION 1 + +/* If ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES is set to 1 then Ethernet frames +that are not in Ethernet II format will be dropped. This option is included for +potential future IP stack developments. */ +#define ipconfigFILTER_OUT_NON_ETHERNET_II_FRAMES 1 + +/* If ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES is set to 1 then it is the +responsibility of the Ethernet interface to filter out packets that are of no +interest. If the Ethernet interface does not implement this functionality, then +set ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES to 0 to have the IP stack +perform the filtering instead (it is much less efficient for the stack to do it +because the packet will already have been passed into the stack). If the +Ethernet driver does all the necessary filtering in hardware then software +filtering can be removed by using a value other than 1 or 0. */ +#define ipconfigETHERNET_DRIVER_FILTERS_FRAME_TYPES 1 + +/* The Linux simulator cannot really simulate MAC interrupts, and needs to +block occasionally to allow other tasks to run. */ +#define configWINDOWS_MAC_INTERRUPT_SIMULATOR_DELAY ( 20 / portTICK_PERIOD_MS ) + +/* Advanced only: in order to access 32-bit fields in the IP packets with +32-bit memory instructions, all packets will be stored 32-bit-aligned, plus 16-bits. +This has to do with the contents of the IP-packets: all 32-bit fields are +32-bit-aligned, plus 16-bit(!) */ +#define ipconfigPACKET_FILLER_SIZE 2U + +/* Define the size of the pool of TCP window descriptors. On the average, each +TCP socket will use up to 2 x 6 descriptors, meaning that it can have 2 x 6 +outstanding packets (for Rx and Tx). When using up to 10 TP sockets +simultaneously, one could define TCP_WIN_SEG_COUNT as 120. */ +#define ipconfigTCP_WIN_SEG_COUNT 240 + +/* Each TCP socket has a circular buffers for Rx and Tx, which have a fixed +maximum size. Define the size of Rx buffer for TCP sockets. */ +#define ipconfigTCP_RX_BUFFER_LENGTH ( 10000 ) + +/* Define the size of Tx buffer for TCP sockets. */ +#define ipconfigTCP_TX_BUFFER_LENGTH ( 10000 ) + +/* When using call-back handlers, the driver may check if the handler points to +real program memory (RAM or flash) or just has a random non-zero value. */ +#define ipconfigIS_VALID_PROG_ADDRESS(x) ( (x) != NULL ) + +/* Include support for TCP hang protection. All sockets in a connecting or +disconnecting stage will timeout after a period of non-activity. */ +#define ipconfigTCP_HANG_PROTECTION ( 0 ) +#define ipconfigTCP_HANG_PROTECTION_TIME ( 30 ) + +/* Include support for TCP keep-alive messages. */ +#define ipconfigTCP_KEEP_ALIVE ( 1 ) +#define ipconfigTCP_KEEP_ALIVE_INTERVAL ( 20 ) /* in seconds */ + +#define portINLINE __inline + +// suggested by https://github.com/FreeRTOS/FreeRTOS-Plus-TCP/tree/main/source/portable/NetworkInterface/STM32Fxx +#define ipconfigMAC_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ) +#define ipconfigUSE_RMII 1 +#define ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM 1 +#define ipconfigZERO_COPY_RX_DRIVER 1 +#define ipconfigZERO_COPY_TX_DRIVER 1 +#define ipconfigUSE_LINKED_RX_MESSAGES 1 + +// phyhandling.c will start searching for a PHY from address 0, trying these many addresses ("ports") +#define ipconfigPHY_MAX_PORTS 1 // we know LAN8724A in this board is at address 0, so one "port" is enough + +#endif /* FREERTOS_IP_CONFIG_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-tcp/README.md b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-tcp/README.md new file mode 100644 index 00000000..44db623b --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-tcp/README.md @@ -0,0 +1,7 @@ +# FreeRTOS+ TCP Web device dashboard on NUCLEO-F746ZG, built on Keil MDK + +- Open this example with Keil uVision +- Build it +- Run/Debug it + +Mongoose configuration is in mongoose_custom.h, inside Network_Library diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-tcp/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-tcp/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc new file mode 100644 index 00000000..7e823433 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos-tcp/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc @@ -0,0 +1,61 @@ + + + + + Keil + FrameworkCubeMX + STM32CubeMX generated pack description + project-path + + + - Generated: 24/03/2023 09:44:13 + + + + + STM32CubeMX Environment + + $SMDK/CubeMX/STM32CubeMXLauncher + $PRTE/Device/STM32F746ZGTx + + + + + + + + + + STM32Cube Framework + + + + Condition to include CMSIS core and Device Startup components + + + + + + + + + + + + + + Configuration via STM32CubeMX + + #define RTE_DEVICE_FRAMEWORK_CUBE_MX + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/MX_Device.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/MX_Device.h new file mode 100644 index 00000000..00adb2ad --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/MX_Device.h @@ -0,0 +1,212 @@ +/****************************************************************************** + * File Name : MX_Device.h + * Date : 14/03/2023 13:35:04 + * Description : STM32Cube MX parameter definitions + * Note : This file is generated by STM32CubeMX (DO NOT EDIT!) + ******************************************************************************/ + +#ifndef __MX_DEVICE_H +#define __MX_DEVICE_H + +/*---------------------------- Clock Configuration ---------------------------*/ + +#define MX_LSI_VALUE 32000 +#define MX_LSE_VALUE 32768 +#define MX_HSI_VALUE 16000000 +#define MX_HSE_VALUE 25000000 +#define MX_EXTERNAL_CLOCK_VALUE 12288000 +#define MX_SYSCLKFreq_VALUE 216000000 +#define MX_HCLKFreq_Value 216000000 +#define MX_FCLKCortexFreq_Value 216000000 +#define MX_CortexFreq_Value 216000000 +#define MX_AHBFreq_Value 216000000 +#define MX_APB1Freq_Value 54000000 +#define MX_APB2Freq_Value 108000000 +#define MX_APB1TimFreq_Value 108000000 +#define MX_APB2TimFreq_Value 216000000 +#define MX_EthernetFreq_Value 216000000 +#define MX_CECFreq_Value 32786 +#define MX_LCDTFToutputFreq_Value 96000000 +#define MX_I2C1Freq_Value 54000000 +#define MX_I2C2Freq_Value 54000000 +#define MX_I2C3Freq_Value 54000000 +#define MX_I2C4Freq_Value 54000000 +#define MX_I2SFreq_Value 192000000 +#define MX_SAI1Freq_Value 192000000 +#define MX_SAI2Freq_Value 192000000 +#define MX_SDMMCFreq_Value 216000000 +#define MX_RTCFreq_Value 32000 +#define MX_USART1Freq_Value 108000000 +#define MX_USART2Freq_Value 54000000 +#define MX_USART3Freq_Value 54000000 +#define MX_UART4Freq_Value 54000000 +#define MX_UART5Freq_Value 54000000 +#define MX_UART8Freq_Value 54000000 +#define MX_UART7Freq_Value 54000000 +#define MX_USART6Freq_Value 108000000 +#define MX_USBFreq_Value 48000000 +#define MX_WatchDogFreq_Value 32000 +#define MX_LPTIM1Freq_Value 54000000 +#define MX_SPDIFRXFreq_Value 192000000 +#define MX_MCO1PinFreq_Value 16000000 +#define MX_MCO2PinFreq_Value 216000000 + +/*-------------------------------- CORTEX_M7 --------------------------------*/ + +#define MX_CORTEX_M7 1 + +/* GPIO Configuration */ + +/*-------------------------------- ETH --------------------------------*/ + +#define MX_ETH 1 + +/* GPIO Configuration */ + +/* Pin PA1 */ +#define MX_ETH_REF_CLK_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_REF_CLK_Pin PA1 +#define MX_ETH_REF_CLK_GPIOx GPIOA +#define MX_ETH_REF_CLK_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_REF_CLK_GPIO_Pin GPIO_PIN_1 +#define MX_ETH_REF_CLK_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_REF_CLK_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PA7 */ +#define MX_ETH_CRS_DV_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_CRS_DV_Pin PA7 +#define MX_ETH_CRS_DV_GPIOx GPIOA +#define MX_ETH_CRS_DV_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_CRS_DV_GPIO_Pin GPIO_PIN_7 +#define MX_ETH_CRS_DV_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_CRS_DV_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC4 */ +#define MX_ETH_RXD0_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_RXD0_Pin PC4 +#define MX_ETH_RXD0_GPIOx GPIOC +#define MX_ETH_RXD0_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_RXD0_GPIO_Pin GPIO_PIN_4 +#define MX_ETH_RXD0_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_RXD0_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC5 */ +#define MX_ETH_RXD1_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_RXD1_Pin PC5 +#define MX_ETH_RXD1_GPIOx GPIOC +#define MX_ETH_RXD1_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_RXD1_GPIO_Pin GPIO_PIN_5 +#define MX_ETH_RXD1_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_RXD1_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PG11 */ +#define MX_ETH_TX_EN_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TX_EN_Pin PG11 +#define MX_ETH_TX_EN_GPIOx GPIOG +#define MX_ETH_TX_EN_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TX_EN_GPIO_Pin GPIO_PIN_11 +#define MX_ETH_TX_EN_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TX_EN_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PA2 */ +#define MX_ETH_MDIO_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_MDIO_Pin PA2 +#define MX_ETH_MDIO_GPIOx GPIOA +#define MX_ETH_MDIO_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_MDIO_GPIO_Pin GPIO_PIN_2 +#define MX_ETH_MDIO_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_MDIO_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PB13 */ +#define MX_ETH_TXD1_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TXD1_Pin PB13 +#define MX_ETH_TXD1_GPIOx GPIOB +#define MX_ETH_TXD1_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TXD1_GPIO_Pin GPIO_PIN_13 +#define MX_ETH_TXD1_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TXD1_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PG13 */ +#define MX_ETH_TXD0_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TXD0_Pin PG13 +#define MX_ETH_TXD0_GPIOx GPIOG +#define MX_ETH_TXD0_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TXD0_GPIO_Pin GPIO_PIN_13 +#define MX_ETH_TXD0_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TXD0_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC1 */ +#define MX_ETH_MDC_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_MDC_Pin PC1 +#define MX_ETH_MDC_GPIOx GPIOC +#define MX_ETH_MDC_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_MDC_GPIO_Pin GPIO_PIN_1 +#define MX_ETH_MDC_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_MDC_GPIO_Mode GPIO_MODE_AF_PP + +/* NVIC Configuration */ + +/* NVIC ETH_IRQn */ +#define MX_ETH_IRQn_interruptPremptionPriority 0 +#define MX_ETH_IRQn_PriorityGroup NVIC_PRIORITYGROUP_4 +#define MX_ETH_IRQn_Subriority 0 + +/*-------------------------------- RNG --------------------------------*/ + +#define MX_RNG 1 + +/* GPIO Configuration */ + +/*-------------------------------- SYS --------------------------------*/ + +#define MX_SYS 1 + +/* GPIO Configuration */ + +/*-------------------------------- USART3 --------------------------------*/ + +#define MX_USART3 1 + +#define MX_USART3_VM VM_ASYNC + +/* GPIO Configuration */ + +/* Pin PD8 */ +#define MX_USART3_TX_GPIO_ModeDefaultPP GPIO_MODE_AF_PP +#define MX_USART3_TX_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_USART3_TX_Pin PD8 +#define MX_USART3_TX_GPIOx GPIOD +#define MX_USART3_TX_GPIO_PuPd GPIO_NOPULL +#define MX_USART3_TX_GPIO_Pin GPIO_PIN_8 +#define MX_USART3_TX_GPIO_AF GPIO_AF7_USART3 + +/* Pin PD9 */ +#define MX_USART3_RX_GPIO_ModeDefaultPP GPIO_MODE_AF_PP +#define MX_USART3_RX_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_USART3_RX_Pin PD9 +#define MX_USART3_RX_GPIOx GPIOD +#define MX_USART3_RX_GPIO_PuPd GPIO_NOPULL +#define MX_USART3_RX_GPIO_Pin GPIO_PIN_9 +#define MX_USART3_RX_GPIO_AF GPIO_AF7_USART3 + +/*-------------------------------- NVIC --------------------------------*/ + +#define MX_NVIC 1 + +/*-------------------------------- GPIO --------------------------------*/ + +#define MX_GPIO 1 + +/* GPIO Configuration */ + +/* Pin PB7 */ +#define MX_PB7_GPIO_Speed GPIO_SPEED_FREQ_LOW +#define MX_PB7_Pin PB7 +#define MX_PB7_GPIOx GPIOB +#define MX_PB7_PinState GPIO_PIN_RESET +#define MX_PB7_GPIO_PuPd GPIO_NOPULL +#define MX_PB7_GPIO_Pin GPIO_PIN_7 +#define MX_PB7_GPIO_ModeDefaultOutputPP GPIO_MODE_OUTPUT_PP + +#endif /* __MX_DEVICE_H */ + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject new file mode 100644 index 00000000..9a8f5fd7 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject @@ -0,0 +1,12 @@ +[PreviousLibFiles] +LibFiles=Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rng.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f746xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\system_stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c; + +[] +SourceFiles=;; + +[PreviousGenFiles] +HeaderPath=..\Inc +HeaderFiles=stm32f7xx_it.h;stm32f7xx_hal_conf.h;main.h; +SourcePath=..\Src +SourceFiles=stm32f7xx_it.c;stm32f7xx_hal_msp.c;main.c; + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h new file mode 100644 index 00000000..280da443 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h new file mode 100644 index 00000000..21c37deb --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h @@ -0,0 +1,484 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f7xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)15U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define ART_ACCELERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE 1524 /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32f7xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h new file mode 100644 index 00000000..8ee5240e --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h @@ -0,0 +1,63 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_IT_H +#define __STM32F7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void DebugMon_Handler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_IT_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc new file mode 100644 index 00000000..780345ba --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc @@ -0,0 +1,178 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +ETH.IPParameters=MediaInterface +ETH.MediaInterface=HAL_ETH_RMII_MODE +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.CPN=STM32F746ZGT6 +Mcu.Family=STM32F7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=ETH +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=RNG +Mcu.IP5=SYS +Mcu.IP6=USART3 +Mcu.IPNb=7 +Mcu.Name=STM32F746ZGTx +Mcu.Package=LQFP144 +Mcu.Pin0=PC1 +Mcu.Pin1=PA1 +Mcu.Pin10=PG13 +Mcu.Pin11=PB7 +Mcu.Pin12=VP_RNG_VS_RNG +Mcu.Pin13=VP_SYS_VS_Systick +Mcu.Pin2=PA2 +Mcu.Pin3=PA7 +Mcu.Pin4=PC4 +Mcu.Pin5=PC5 +Mcu.Pin6=PB13 +Mcu.Pin7=PD8 +Mcu.Pin8=PD9 +Mcu.Pin9=PG11 +Mcu.PinsNb=14 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F746ZGTx +MxCube.Version=6.8.0 +MxDb.Version=DB.6.0.80 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ETH_IRQn=true\:0\:0\:false\:false\:false\:true\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:false\:true\:false +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA1.Mode=RMII +PA1.Signal=ETH_REF_CLK +PA2.Mode=RMII +PA2.Signal=ETH_MDIO +PA7.Mode=RMII +PA7.Signal=ETH_CRS_DV +PB13.Mode=RMII +PB13.Signal=ETH_TXD1 +PB7.Locked=true +PB7.Signal=GPIO_Output +PC1.Mode=RMII +PC1.Signal=ETH_MDC +PC4.Mode=RMII +PC4.Signal=ETH_RXD0 +PC5.Mode=RMII +PC5.Signal=ETH_RXD1 +PD8.Locked=true +PD8.Mode=Asynchronous +PD8.Signal=USART3_TX +PD9.Locked=true +PD9.Mode=Asynchronous +PD9.Signal=USART3_RX +PG11.Locked=true +PG11.Mode=RMII +PG11.Signal=ETH_TX_EN +PG13.Locked=true +PG13.Mode=RMII +PG13.Signal=ETH_TXD0 +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F746ZGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.17.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=2 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=true +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=STCubeGenerated.ioc +ProjectManager.ProjectName=STCubeGenerated +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_RNG_Init-RNG-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.AHBFreq_Value=216000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=54000000 +RCC.APB1TimFreq_Value=108000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=108000000 +RCC.APB2TimFreq_Value=216000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=216000000 +RCC.EthernetFreq_Value=216000000 +RCC.FCLKCortexFreq_Value=216000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=216000000 +RCC.HSE_VALUE=25000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=54000000 +RCC.I2C2Freq_Value=54000000 +RCC.I2C3Freq_Value=54000000 +RCC.I2C4Freq_Value=54000000 +RCC.I2SFreq_Value=192000000 +RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value +RCC.LCDTFToutputFreq_Value=96000000 +RCC.LPTIM1Freq_Value=54000000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=216000000 +RCC.PLLCLKFreq_Value=216000000 +RCC.PLLI2SPCLKFreq_Value=192000000 +RCC.PLLI2SQCLKFreq_Value=192000000 +RCC.PLLI2SRCLKFreq_Value=192000000 +RCC.PLLI2SRoutputFreq_Value=192000000 +RCC.PLLM=8 +RCC.PLLN=216 +RCC.PLLQ=9 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLQoutputFreq_Value=48000000 +RCC.PLLSAIPCLKFreq_Value=192000000 +RCC.PLLSAIQCLKFreq_Value=192000000 +RCC.PLLSAIRCLKFreq_Value=192000000 +RCC.PLLSAIoutputFreq_Value=192000000 +RCC.RNGFreq_Value=48000000 +RCC.SAI1Freq_Value=192000000 +RCC.SAI2Freq_Value=192000000 +RCC.SDMMCFreq_Value=216000000 +RCC.SPDIFRXFreq_Value=192000000 +RCC.SYSCLKFreq_VALUE=216000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=54000000 +RCC.UART5Freq_Value=54000000 +RCC.UART7Freq_Value=54000000 +RCC.UART8Freq_Value=54000000 +RCC.USART1Freq_Value=108000000 +RCC.USART2Freq_Value=54000000 +RCC.USART3Freq_Value=54000000 +RCC.USART6Freq_Value=108000000 +RCC.USBFreq_Value=48000000 +RCC.VCOI2SOutputFreq_Value=384000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutputFreq_Value=432000000 +RCC.VCOSAIOutputFreq_Value=384000000 +USART3.IPParameters=VirtualMode-Asynchronous +USART3.VirtualMode-Asynchronous=VM_ASYNC +VP_RNG_VS_RNG.Mode=RNG_Activate +VP_RNG_VS_RNG.Signal=RNG_VS_RNG +VP_SYS_VS_Systick.Mode=SysTick +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +board=custom diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c new file mode 100644 index 00000000..07d336b2 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c @@ -0,0 +1,330 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "string.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma location=0x2004c000 +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +#pragma location=0x2004c0a0 +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __CC_ARM ) /* MDK ARM Compiler */ + +__attribute__((at(0x2004c000))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +__attribute__((at(0x2004c0a0))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __GNUC__ ) /* GNU Compiler */ +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */ +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection"))); /* Ethernet Tx DMA Descriptors */ + +#endif + +ETH_TxPacketConfig TxConfig; + +ETH_HandleTypeDef heth; + +RNG_HandleTypeDef hrng; + +UART_HandleTypeDef huart3; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART3_UART_Init(void); +static void MX_ETH_Init(void); +static void MX_RNG_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +void mx_init(void) { + SystemClock_Config(); + MX_GPIO_Init(); + MX_USART3_UART_Init(); + MX_RNG_Init(); + MX_ETH_Init(); +} + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 216; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ETH Initialization Function + * @param None + * @retval None + */ +static void MX_ETH_Init(void) +{ + + /* USER CODE BEGIN ETH_Init 0 */ + + /* USER CODE END ETH_Init 0 */ + + static uint8_t MACAddr[6]; + + /* USER CODE BEGIN ETH_Init 1 */ + + /* USER CODE END ETH_Init 1 */ + heth.Instance = ETH; + MACAddr[0] = 0x00; + MACAddr[1] = 0x80; + MACAddr[2] = 0xE1; + MACAddr[3] = 0x00; + MACAddr[4] = 0x00; + MACAddr[5] = 0x00; + heth.Init.MACAddr = &MACAddr[0]; + heth.Init.MediaInterface = HAL_ETH_RMII_MODE; + heth.Init.TxDesc = DMATxDscrTab; + heth.Init.RxDesc = DMARxDscrTab; + heth.Init.RxBuffLen = 1524; + + /* USER CODE BEGIN MACADDRESS */ + + /* USER CODE END MACADDRESS */ + + if (HAL_ETH_Init(&heth) != HAL_OK) + { + Error_Handler(); + } + + memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig)); + TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; + TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; + TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; + /* USER CODE BEGIN ETH_Init 2 */ + + /* USER CODE END ETH_Init 2 */ + +} + +/** + * @brief RNG Initialization Function + * @param None + * @retval None + */ +static void MX_RNG_Init(void) +{ + + /* USER CODE BEGIN RNG_Init 0 */ + + /* USER CODE END RNG_Init 0 */ + + /* USER CODE BEGIN RNG_Init 1 */ + + /* USER CODE END RNG_Init 1 */ + hrng.Instance = RNG; + if (HAL_RNG_Init(&hrng) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RNG_Init 2 */ + + /* USER CODE END RNG_Init 2 */ + +} + +/** + * @brief USART3 Initialization Function + * @param None + * @retval None + */ +static void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET); + + /*Configure GPIO pin : PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c new file mode 100644 index 00000000..cff0eb5b --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c @@ -0,0 +1,326 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ETH MSP Initialization +* This function configures the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspInit 0 */ + + /* USER CODE END ETH_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ETH_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* ETH interrupt Init */ + HAL_NVIC_SetPriority(ETH_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspInit 1 */ + + /* USER CODE END ETH_MspInit 1 */ + } + +} + +/** +* @brief ETH MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspDeInit 0 */ + + /* USER CODE END ETH_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11|GPIO_PIN_13); + + /* ETH interrupt DeInit */ + HAL_NVIC_DisableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspDeInit 1 */ + + /* USER CODE END ETH_MspDeInit 1 */ + } + +} + +/** +* @brief RNG MSP Initialization +* This function configures the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspInit 0 */ + + /* USER CODE END RNG_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_RNG_CLK_ENABLE(); + /* USER CODE BEGIN RNG_MspInit 1 */ + + /* USER CODE END RNG_MspInit 1 */ + } + +} + +/** +* @brief RNG MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspDeInit 0 */ + + /* USER CODE END RNG_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RNG_CLK_DISABLE(); + /* USER CODE BEGIN RNG_MspDeInit 1 */ + + /* USER CODE END RNG_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; + PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9); + + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c new file mode 100644 index 00000000..e7760fd5 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c @@ -0,0 +1,163 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M7 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f7xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s new file mode 100644 index 00000000..9286c004 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s @@ -0,0 +1,468 @@ +;******************************************************************************* +;* File Name : startup_stm32f746xx.s +;* Author : MCD Application Team +;* Description : STM32F746xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2016 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000800 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000800 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c new file mode 100644 index 00000000..32e7fa5f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c @@ -0,0 +1,259 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS RAMDTCM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/project.script b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/project.script new file mode 100644 index 00000000..0f10b399 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Device/project.script @@ -0,0 +1,7 @@ +load STM32F746ZGTx +project name STCubeGenerated +project toolchain "MDK-ARM V5" +project path "C:\Users\scaprile\Documents\Keil\nucleo-f746zg-keil-baremetal\RTE\Device\STM32F746ZGTx\" +set tpl_path "C:\Users\scaprile\AppData\Local\Arm\Packs\Keil\STM32F7xx_DFP\2.15.1\MDK\CubeMX" +set dest_path "STM32F746ZGTx" +SetCopyLibrary "copy as reference" diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Network_Library/mongoose_custom.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Network_Library/mongoose_custom.h new file mode 100644 index 00000000..580d5616 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/Network_Library/mongoose_custom.h @@ -0,0 +1,77 @@ + +// <<< Use Configuration Wizard in Context Menu >>> + +// System Architecture +// <0=> Bare metal +// <1=> FreeRTOS +// <2=> CMSIS-RTOS v1 +// <3=> CMSIS-RTOS v2 +// Select either bare metal operation or a supported RTOS +// "FreeRTOS" uses direct FreeRTOS calls +// "CMSIS-RTOS v1" supports only Keil RTX through API v1 +// "CMSIS-RTOS v2" supports Keil RTX5 and FreeRTOS through API v2 + +#define MG_CMSISPACK_ARCH 1 + + +// Networking support +// Networking stack +// <0=> Built-in +// <1=> lwIP +// <2=> FreeRTOS-Plus-TCP +// <3=> MDK (RL) +// Select the networking stack to use with Mongoose Library +// The built-in stack can run on bare metal or over any RTOS +// "lwIP" requires using an RTOS and BSD socket mode +// "MDK" requires using CMSIS-RTOS1 (RTX + RL) or CMSIS-RTOS2 (MDK Plus or Pro), and BSD socket mode +#define MG_CMSISPACK_NET 0 + +// Use Mbed-TLS +// Mongoose will use Mbed-TLS calls for TLS-related functionality +#define MG_ENABLE_MBEDTLS 0 +// + + +// Enable custom mg_millis() +// Use a user-provided function to get uptime in milliseconds, otherwise Mongoose will default to using time(). Except for bare metal, Mongoose will use the time base for the configured architecture +//#define MG_ENABLE_CUSTOM_MILLIS 1 +// + + +// Enable custom mg_rand() +// Use a user-provided function to generate random numbers, otherwise Mongoose will default to using rand() +#define MG_ENABLE_CUSTOM_RANDOM 1 +// + + +// Filesystem support +// Enable packed (embedded) filesystem +#define MG_ENABLE_PACKED_FS 1 +// + + +// <<< end of configuration section >>> + +// Translate to Mongoose macros +#if MG_CMSISPACK_ARCH == 1 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_FREERTOS +#elif MG_CMSISPACK_ARCH == 2 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_CMSIS_RTOS1 +#elif MG_CMSISPACK_ARCH == 3 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_CMSIS_RTOS2 +#endif +#if MG_CMSISPACK_NET == 0 +#define MG_ENABLE_TCPIP 1 +#elif MG_CMSISPACK_NET == 1 +#define MG_ENABLE_LWIP 1 +#elif MG_CMSISPACK_NET == 2 +#define MG_ENABLE_FREERTOS_TCP 1 +#elif MG_CMSISPACK_NET == 3 +#define MG_ENABLE_RL 1 +#endif + + +// Add your customization below this comment diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/RTOS/FreeRTOSConfig.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/RTOS/FreeRTOSConfig.h new file mode 100644 index 00000000..37b8b258 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/RTOS/FreeRTOSConfig.h @@ -0,0 +1,162 @@ +/* + * FreeRTOS Kernel V10.4.0 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +#if (defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)) +#include + +extern uint32_t SystemCoreClock; +#endif + +/* Constants that describe the hardware and memory usage. */ +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configTOTAL_HEAP_SIZE ((size_t)1024 * 64) +#define configMINIMAL_STACK_SIZE ((uint16_t)128) +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configSUPPORT_STATIC_ALLOCATION 0 + +/* Constants related to the behaviour or the scheduler. */ +#define configMAX_PRIORITIES 5 +#define configUSE_PREEMPTION 1 +#define configUSE_TIME_SLICING 1 +#define configIDLE_SHOULD_YIELD 1 +#define configMAX_TASK_NAME_LEN (10) +#define configUSE_16_BIT_TICKS 0 + +/* Software timer definitions. */ +#define configUSE_TIMERS 0 +#define configTIMER_TASK_PRIORITY 2 +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +/* Constants that build features in or out. */ +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_TICKLESS_IDLE 0 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configUSE_CO_ROUTINES 0 + +/* Constants provided for debugging and optimisation assistance. */ +#define configCHECK_FOR_STACK_OVERFLOW 0 +#define configQUEUE_REGISTRY_SIZE 0 +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Constants that define which hook (callback) functions should be used. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 + +/* Port specific configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_MVE 0 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ((uint32_t)1024) +#define configRUN_FREERTOS_SECURE_ONLY 0 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __NVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + // CMSIS headers are not being pulled with this file + #define configPRIO_BITS 4 +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15 + +/* The highest interrupt priority that can be used by any interrupt service + * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT + * CALL INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A + * HIGHER PRIORITY THAN THIS! (higher priorities are lower numeric values). */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic + * to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! + * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is + * only necessary if the linker does not automatically remove functions that are + * not referenced anyway. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_xTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetIdleTaskHandle 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xQueueGetMutexHolder 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_uxTaskGetStackHighWaterMark2 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 + +/* Map the FreeRTOS port interrupt handlers to their CMSIS standard names. */ +#define xPortPendSVHandler PendSV_Handler +#define vPortSVCHandler SVC_Handler +// We'll handle SysTick_Handler and call xPortSysTickHandler ourselves, like CMSIS-RTOS2 + +#if (defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)) +/* Include debug event definitions */ +#include "freertos_evr.h" +#endif + +#endif /* FREERTOS_CONFIG_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/_Target_1/Pre_Include_Global.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/_Target_1/Pre_Include_Global.h new file mode 100644 index 00000000..8aabd0e0 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/_Target_1/Pre_Include_Global.h @@ -0,0 +1,17 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'device-dashboard' + * Target: 'Target 1' + */ + +#ifndef PRE_INCLUDE_GLOBAL_H +#define PRE_INCLUDE_GLOBAL_H + +/* Keil::Device:STM32Cube HAL:Common:1.3.0 */ +#define USE_HAL_DRIVER + + +#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/_Target_1/RTE_Components.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/_Target_1/RTE_Components.h new file mode 100644 index 00000000..b7d07897 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/RTE/_Target_1/RTE_Components.h @@ -0,0 +1,52 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'device-dashboard' + * Target: 'Target 1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f7xx.h" + +/* ARM.FreeRTOS::RTOS:Config:FreeRTOS:10.5.1 */ +#define RTE_RTOS_FreeRTOS_CONFIG /* RTOS FreeRTOS Config for FreeRTOS API */ +/* ARM.FreeRTOS::RTOS:Core:Cortex-M:10.5.1 */ +#define RTE_RTOS_FreeRTOS_CORE /* RTOS FreeRTOS Core */ +/* ARM.FreeRTOS::RTOS:Heap:Heap_4:10.5.1 */ +#define RTE_RTOS_FreeRTOS_HEAP_4 /* RTOS FreeRTOS Heap 4 */ +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:User:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ +/* Keil::Device:STM32Cube Framework:STM32CubeMX:1.1.0 */ +#define RTE_DEVICE_FRAMEWORK_CUBE_MX +/* Keil::Device:STM32Cube HAL:Common:1.3.0 */ +#define RTE_DEVICE_HAL_COMMON +/* Keil::Device:STM32Cube HAL:Cortex:1.3.0 */ +#define RTE_DEVICE_HAL_CORTEX +/* Keil::Device:STM32Cube HAL:DMA:1.3.0 */ +#define RTE_DEVICE_HAL_DMA +/* Keil::Device:STM32Cube HAL:ETH:1.3.0 */ +#define RTE_DEVICE_HAL_ETH +/* Keil::Device:STM32Cube HAL:GPIO:1.3.0 */ +#define RTE_DEVICE_HAL_GPIO +/* Keil::Device:STM32Cube HAL:PWR:1.3.0 */ +#define RTE_DEVICE_HAL_PWR +/* Keil::Device:STM32Cube HAL:RCC:1.3.0 */ +#define RTE_DEVICE_HAL_RCC +/* Keil::Device:STM32Cube HAL:RNG:1.3.0 */ +#define RTE_DEVICE_HAL_RNG +/* Keil::Device:STM32Cube HAL:UART:1.3.0 */ +#define RTE_DEVICE_HAL_UART +/* Keil::Device:Startup:1.2.5 */ +#define RTE_DEVICE_STARTUP_STM32F7XX /* Device Startup for STM32F7 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/device-dashboard.uvguix b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/device-dashboard.uvguix new file mode 100644 index 00000000..b1ec2fd2 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/device-dashboard.uvguix @@ -0,0 +1,3673 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 1920 + 1080 + + + + + + 1 + 0 + + 100 + 2 + + RTE\Network_Library\mongoose_custom.h + 0 + 44 + 68 + 1 + + 0 + + + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + 0 + 257 + 262 + 1 + + 0 + + + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + 5 + 80 + 84 + 1 + + 0 + + + .\main.c + 0 + 58 + 84 + 1 + + 0 + + + RTE\Device\STM32F746ZGTx\startup_stm32f746xx.s + 0 + 184 + 188 + 1 + + 0 + + + .\syscalls.c + 0 + 1 + 8 + 1 + + 0 + + + RTE\RTOS\FreeRTOSConfig.h + 2 + 1 + 14 + 1 + + 0 + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/device-dashboard.uvoptx b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/device-dashboard.uvoptx new file mode 100644 index 00000000..8e73cf9f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/device-dashboard.uvoptx @@ -0,0 +1,398 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 16000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(6017=561,219,750,555,0)(1008=-1,-1,-1,-1,0)(6016=21,136,279,789,1)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + ST-LINKIII-KEIL_SWO + -U-O206 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(5BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FF1STM32F7xTCM_1024.FLM -FS1200000 -FL1100000 -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + + + + + 0 + 0 + 98 + 1 +
134248896
+ 0 + 0 + 0 + 0 + 0 + 1 + .\main.c + + \\device_dashboard\main.c\98 + + + + + 0 + 1 + stack[6] + + + 1 + 1 + huart3 + + + + + 1 + 0 + 0x20013AD0 + 0 + + + + C:\Users\scaprile\AppData\Local\Arm\Packs\ARM\CMSIS-FreeRTOS\10.5.1\CMSIS\RTOS2\FreeRTOS\FreeRTOS.scvd + ARM.CMSIS-FreeRTOS.10.5.1 + 1 + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 1 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + .\hal.h + hal.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + .\net.c + net.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + .\packed_fs.c + packed_fs.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + .\syscalls.c + syscalls.c + 0 + 0 + + + + + :STM32CubeMX:Common Sources + 1 + 0 + 0 + 0 + + 2 + 6 + 1 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + main.c + 0 + 0 + + + 2 + 7 + 5 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Inc\stm32f7xx_it.h + stm32f7xx_it.h + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + stm32f7xx_it.c + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + + + ::Compiler + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + + ::Network Library + 0 + 0 + 0 + 1 + + + + ::RTOS + 1 + 0 + 0 + 1 + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/device-dashboard.uvprojx b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/device-dashboard.uvprojx new file mode 100644 index 00000000..9b862df4 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/device-dashboard.uvprojx @@ -0,0 +1,602 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + STM32F746ZGTx + STMicroelectronics + Keil.STM32F7xx_DFP.2.15.1 + https://www.keil.com/pack/ + IRAM(0x20010000,0x40000) IRAM2(0x20000000,0x10000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + 0 + $$Device:STM32F746ZGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h + + + + + + + + + + $$Device:STM32F746ZGTx$CMSIS\SVD\STM32F746.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + device-dashboard + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x200000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + + -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion -Wno-unused-parameter -Wconversion -Wno-sign-conversion -Wno-implicit-int-conversion -fno-common -fdata-sections + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20010000 + + + + + + + + + + + + + Source Group 1 + + + hal.h + 5 + .\hal.h + + + main.c + 1 + .\main.c + + + net.c + 1 + .\net.c + + + packed_fs.c + 1 + .\packed_fs.c + + + syscalls.c + 1 + .\syscalls.c + + + + + :STM32CubeMX:Common Sources + + + main.c + 1 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + + + stm32f7xx_it.h + 5 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Inc\stm32f7xx_it.h + + + stm32f7xx_it.c + 1 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + + + + + ::CMSIS + + + ::Compiler + + + ::Device + + + ::Network Library + + + ::RTOS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\STM32F746ZGTx\startup_stm32f746xx.s + + + + + + + + RTE\Device\STM32F746ZGTx\system_stm32f7xx.c + + + + + + + + RTE\Network_Library\mongoose_custom.h + + + + + + + + RTE\RTOS\FreeRTOSConfig.h + + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/hal.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/hal.h new file mode 100644 index 00000000..a0ec0b30 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/hal.h @@ -0,0 +1,21 @@ +// Copyright (c) 2022-23 Cesanta Software Limited +// All rights reserved +// https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf + +#pragma once + +#include + +#ifndef UART_DEBUG +#define UART_DEBUG USART3 +#endif + + +#define UUID ((uint8_t *) UID_BASE) // Unique 96-bit chip ID. TRM 41.1 + +// Helper macro for MAC generation +#define GENERATE_LOCALLY_ADMINISTERED_MAC() \ + { \ + 2, UUID[0] ^ UUID[1], UUID[2] ^ UUID[3], UUID[4] ^ UUID[5], \ + UUID[6] ^ UUID[7] ^ UUID[8], UUID[9] ^ UUID[10] ^ UUID[11] \ + } diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/main.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/main.c new file mode 100644 index 00000000..f9ff9405 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/main.c @@ -0,0 +1,84 @@ +// Copyright (c) 2023 Cesanta Software Limited +// All rights reserved + +#include "hal.h" +#include "mongoose.h" +#include "main.h" + +#define BLINK_PERIOD_MS 1000 // LED blinking period in millis + +extern void xPortSysTickHandler(void); +void SysTick_Handler (void) { + HAL_IncTick(); + // xPortSysTickHandler() must be called after vTaskStartScheduler() and mx_init() takes longer than 1ms + if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) + xPortSysTickHandler(); +} + +void mg_random(void *buf, size_t len) { // Use on-board RNG + extern RNG_HandleTypeDef hrng; + for (size_t n = 0; n < len; n += sizeof(uint32_t)) { + uint32_t r; + HAL_RNG_GenerateRandomNumber(&hrng, &r); + memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r)); + } +} + +static void timer_fn(void *arg) { + struct mg_tcpip_if *ifp = arg; // And show + const char *names[] = {"down", "up", "ready"}; // network stats + MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u", + names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent, + ifp->ndrop, ifp->nerr)); +} + +static void server(void *args) { + struct mg_mgr mgr; // Initialise Mongoose event manager + mg_mgr_init(&mgr); // and attach it to the interface + mg_log_set(MG_LL_DEBUG); // Set log level + + // Initialise Mongoose network stack + // Specify MAC address, and IP/mask/GW in network byte order for static + // IP configuration. If IP/mask/GW are unset, DHCP is going to be used + struct mg_tcpip_driver_stm32_data driver_data = {.mdc_cr = 4}; + struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(), + .driver = &mg_tcpip_driver_stm32, + .driver_data = &driver_data}; + mg_tcpip_init(&mgr, &mif); + mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif); + + MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac)); + while (mif.state != MG_TCPIP_STATE_READY) { + mg_mgr_poll(&mgr, 0); + } + + MG_INFO(("Initialising application...")); + extern void device_dashboard_fn(struct mg_connection *, int, void *, void *); + mg_http_listen(&mgr, "http://0.0.0.0", device_dashboard_fn, NULL); + + MG_INFO(("Starting event loop")); + for (;;) mg_mgr_poll(&mgr, 1); // Infinite event loop + (void) args; +} + +static void blinker(void *args) { + for (;;) { + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_7); // Blink On-board blue LED + vTaskDelay(pdMS_TO_TICKS(BLINK_PERIOD_MS)); + } + (void) args; +} + +extern void mx_init(void); + +int main(void) { + mx_init(); // Setup clock and all peripherals configured in CubeMX + // Initialise random number generator + // Initialise ethernet pins + // Start tasks. NOTE: stack sizes are in 32-bit words + xTaskCreate(blinker, "blinker", 128, ":)", configMAX_PRIORITIES - 1, NULL); + xTaskCreate(server, "server", 2048, 0, configMAX_PRIORITIES - 1, NULL); + + vTaskStartScheduler(); // This blocks + return 0; +} diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/syscalls.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/syscalls.c new file mode 100644 index 00000000..79113968 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos/syscalls.c @@ -0,0 +1,10 @@ +#include +#include + +#include "main.h" + +int stdout_putchar (int ch) { + extern UART_HandleTypeDef huart3; + HAL_UART_Transmit(&huart3, (const uint8_t *)&ch, 1, 100); + return ch; +} diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2-lwip/EventRecorderStub.scvd b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2-lwip/EventRecorderStub.scvd new file mode 100644 index 00000000..0fb3ee58 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2-lwip/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2-lwip/README.md b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2-lwip/README.md new file mode 100644 index 00000000..7c95a760 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2-lwip/README.md @@ -0,0 +1,9 @@ +# FreeRTOS + lwIP Web device dashboard on NUCLEO-F746ZG, built on Keil MDK + +- Open this example with Keil uVision +- Build it +- Run/Debug it + +Mongoose configuration is in mongoose_custom.h, inside Network_Library + +This example uses CMSIS-RTOS v2 API calls and configures lwIP to use CMSIS-RTOS v2 interface with FreeRTOS diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2-lwip/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2-lwip/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc new file mode 100644 index 00000000..e1c41156 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2-lwip/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc @@ -0,0 +1,64 @@ + + + + + Keil + FrameworkCubeMX + STM32CubeMX generated pack description + project-path + + + - Generated: 23/05/2023 19:16:15 + + + + + STM32CubeMX Environment + + $SMDK/CubeMX/STM32CubeMXLauncher + $PRTE/Device/STM32F746ZGTx + + + + + + + + + + STM32Cube Framework + + + + Condition to include CMSIS core and Device Startup components + + + + + + + + + + + + + + + Configuration via STM32CubeMX + + #define RTE_DEVICE_FRAMEWORK_CUBE_MX + + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/MX_Device.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/MX_Device.h new file mode 100644 index 00000000..23e3d712 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/MX_Device.h @@ -0,0 +1,212 @@ +/****************************************************************************** + * File Name : MX_Device.h + * Date : 23/05/2023 16:23:40 + * Description : STM32Cube MX parameter definitions + * Note : This file is generated by STM32CubeMX (DO NOT EDIT!) + ******************************************************************************/ + +#ifndef __MX_DEVICE_H +#define __MX_DEVICE_H + +/*---------------------------- Clock Configuration ---------------------------*/ + +#define MX_LSI_VALUE 32000 +#define MX_LSE_VALUE 32768 +#define MX_HSI_VALUE 16000000 +#define MX_HSE_VALUE 25000000 +#define MX_EXTERNAL_CLOCK_VALUE 12288000 +#define MX_SYSCLKFreq_VALUE 216000000 +#define MX_HCLKFreq_Value 216000000 +#define MX_FCLKCortexFreq_Value 216000000 +#define MX_CortexFreq_Value 216000000 +#define MX_AHBFreq_Value 216000000 +#define MX_APB1Freq_Value 54000000 +#define MX_APB2Freq_Value 108000000 +#define MX_APB1TimFreq_Value 108000000 +#define MX_APB2TimFreq_Value 216000000 +#define MX_EthernetFreq_Value 216000000 +#define MX_CECFreq_Value 32786 +#define MX_LCDTFToutputFreq_Value 96000000 +#define MX_I2C1Freq_Value 54000000 +#define MX_I2C2Freq_Value 54000000 +#define MX_I2C3Freq_Value 54000000 +#define MX_I2C4Freq_Value 54000000 +#define MX_I2SFreq_Value 192000000 +#define MX_SAI1Freq_Value 192000000 +#define MX_SAI2Freq_Value 192000000 +#define MX_SDMMCFreq_Value 216000000 +#define MX_RTCFreq_Value 32000 +#define MX_USART1Freq_Value 108000000 +#define MX_USART2Freq_Value 54000000 +#define MX_USART3Freq_Value 54000000 +#define MX_UART4Freq_Value 54000000 +#define MX_UART5Freq_Value 54000000 +#define MX_UART8Freq_Value 54000000 +#define MX_UART7Freq_Value 54000000 +#define MX_USART6Freq_Value 108000000 +#define MX_USBFreq_Value 48000000 +#define MX_WatchDogFreq_Value 32000 +#define MX_LPTIM1Freq_Value 54000000 +#define MX_SPDIFRXFreq_Value 192000000 +#define MX_MCO1PinFreq_Value 16000000 +#define MX_MCO2PinFreq_Value 216000000 + +/*-------------------------------- CORTEX_M7 --------------------------------*/ + +#define MX_CORTEX_M7 1 + +/* GPIO Configuration */ + +/*-------------------------------- ETH --------------------------------*/ + +#define MX_ETH 1 + +/* GPIO Configuration */ + +/* Pin PA1 */ +#define MX_ETH_REF_CLK_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_REF_CLK_Pin PA1 +#define MX_ETH_REF_CLK_GPIOx GPIOA +#define MX_ETH_REF_CLK_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_REF_CLK_GPIO_Pin GPIO_PIN_1 +#define MX_ETH_REF_CLK_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_REF_CLK_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PA7 */ +#define MX_ETH_CRS_DV_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_CRS_DV_Pin PA7 +#define MX_ETH_CRS_DV_GPIOx GPIOA +#define MX_ETH_CRS_DV_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_CRS_DV_GPIO_Pin GPIO_PIN_7 +#define MX_ETH_CRS_DV_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_CRS_DV_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC4 */ +#define MX_ETH_RXD0_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_RXD0_Pin PC4 +#define MX_ETH_RXD0_GPIOx GPIOC +#define MX_ETH_RXD0_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_RXD0_GPIO_Pin GPIO_PIN_4 +#define MX_ETH_RXD0_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_RXD0_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC5 */ +#define MX_ETH_RXD1_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_RXD1_Pin PC5 +#define MX_ETH_RXD1_GPIOx GPIOC +#define MX_ETH_RXD1_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_RXD1_GPIO_Pin GPIO_PIN_5 +#define MX_ETH_RXD1_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_RXD1_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PG11 */ +#define MX_ETH_TX_EN_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TX_EN_Pin PG11 +#define MX_ETH_TX_EN_GPIOx GPIOG +#define MX_ETH_TX_EN_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TX_EN_GPIO_Pin GPIO_PIN_11 +#define MX_ETH_TX_EN_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TX_EN_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PA2 */ +#define MX_ETH_MDIO_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_MDIO_Pin PA2 +#define MX_ETH_MDIO_GPIOx GPIOA +#define MX_ETH_MDIO_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_MDIO_GPIO_Pin GPIO_PIN_2 +#define MX_ETH_MDIO_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_MDIO_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PB13 */ +#define MX_ETH_TXD1_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TXD1_Pin PB13 +#define MX_ETH_TXD1_GPIOx GPIOB +#define MX_ETH_TXD1_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TXD1_GPIO_Pin GPIO_PIN_13 +#define MX_ETH_TXD1_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TXD1_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PG13 */ +#define MX_ETH_TXD0_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TXD0_Pin PG13 +#define MX_ETH_TXD0_GPIOx GPIOG +#define MX_ETH_TXD0_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TXD0_GPIO_Pin GPIO_PIN_13 +#define MX_ETH_TXD0_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TXD0_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC1 */ +#define MX_ETH_MDC_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_MDC_Pin PC1 +#define MX_ETH_MDC_GPIOx GPIOC +#define MX_ETH_MDC_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_MDC_GPIO_Pin GPIO_PIN_1 +#define MX_ETH_MDC_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_MDC_GPIO_Mode GPIO_MODE_AF_PP + +/* NVIC Configuration */ + +/* NVIC ETH_IRQn */ +#define MX_ETH_IRQn_interruptPremptionPriority 0 +#define MX_ETH_IRQn_PriorityGroup NVIC_PRIORITYGROUP_4 +#define MX_ETH_IRQn_Subriority 0 + +/*-------------------------------- RNG --------------------------------*/ + +#define MX_RNG 1 + +/* GPIO Configuration */ + +/*-------------------------------- SYS --------------------------------*/ + +#define MX_SYS 1 + +/* GPIO Configuration */ + +/*-------------------------------- USART3 --------------------------------*/ + +#define MX_USART3 1 + +#define MX_USART3_VM VM_ASYNC + +/* GPIO Configuration */ + +/* Pin PD8 */ +#define MX_USART3_TX_GPIO_ModeDefaultPP GPIO_MODE_AF_PP +#define MX_USART3_TX_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_USART3_TX_Pin PD8 +#define MX_USART3_TX_GPIOx GPIOD +#define MX_USART3_TX_GPIO_PuPd GPIO_NOPULL +#define MX_USART3_TX_GPIO_Pin GPIO_PIN_8 +#define MX_USART3_TX_GPIO_AF GPIO_AF7_USART3 + +/* Pin PD9 */ +#define MX_USART3_RX_GPIO_ModeDefaultPP GPIO_MODE_AF_PP +#define MX_USART3_RX_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_USART3_RX_Pin PD9 +#define MX_USART3_RX_GPIOx GPIOD +#define MX_USART3_RX_GPIO_PuPd GPIO_NOPULL +#define MX_USART3_RX_GPIO_Pin GPIO_PIN_9 +#define MX_USART3_RX_GPIO_AF GPIO_AF7_USART3 + +/*-------------------------------- NVIC --------------------------------*/ + +#define MX_NVIC 1 + +/*-------------------------------- GPIO --------------------------------*/ + +#define MX_GPIO 1 + +/* GPIO Configuration */ + +/* Pin PB7 */ +#define MX_PB7_GPIO_Speed GPIO_SPEED_FREQ_LOW +#define MX_PB7_Pin PB7 +#define MX_PB7_GPIOx GPIOB +#define MX_PB7_PinState GPIO_PIN_RESET +#define MX_PB7_GPIO_PuPd GPIO_NOPULL +#define MX_PB7_GPIO_Pin GPIO_PIN_7 +#define MX_PB7_GPIO_ModeDefaultOutputPP GPIO_MODE_OUTPUT_PP + +#endif /* __MX_DEVICE_H */ + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject new file mode 100644 index 00000000..dc78b54a --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject @@ -0,0 +1,12 @@ +[PreviousLibFiles] +LibFiles=Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rng.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f746xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\system_stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c; + +[] +SourceFiles=;; + +[PreviousGenFiles] +HeaderPath=..\Inc +HeaderFiles=stm32f7xx_it.h;stm32f7xx_hal_conf.h;main.h; +SourcePath=..\Src +SourceFiles=stm32f7xx_it.c;stm32f7xx_hal_msp.c;stm32f7xx_hal_timebase_tim.c;main.c; + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h new file mode 100644 index 00000000..280da443 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h new file mode 100644 index 00000000..6a6405d8 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h @@ -0,0 +1,484 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f7xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)15U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define ART_ACCELERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE 1524 /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32f7xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h new file mode 100644 index 00000000..8d598487 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h @@ -0,0 +1,64 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_IT_H +#define __STM32F7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void DebugMon_Handler(void); +void TIM6_DAC_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_IT_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc new file mode 100644 index 00000000..36522c17 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc @@ -0,0 +1,181 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +ETH.IPParameters=MediaInterface +ETH.MediaInterface=HAL_ETH_RMII_MODE +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.CPN=STM32F746ZGT6 +Mcu.Family=STM32F7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=ETH +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=RNG +Mcu.IP5=SYS +Mcu.IP6=USART3 +Mcu.IPNb=7 +Mcu.Name=STM32F746ZGTx +Mcu.Package=LQFP144 +Mcu.Pin0=PC1 +Mcu.Pin1=PA1 +Mcu.Pin10=PG13 +Mcu.Pin11=PB7 +Mcu.Pin12=VP_RNG_VS_RNG +Mcu.Pin13=VP_SYS_VS_tim6 +Mcu.Pin2=PA2 +Mcu.Pin3=PA7 +Mcu.Pin4=PC4 +Mcu.Pin5=PC5 +Mcu.Pin6=PB13 +Mcu.Pin7=PD8 +Mcu.Pin8=PD9 +Mcu.Pin9=PG11 +Mcu.PinsNb=14 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F746ZGTx +MxCube.Version=6.8.0 +MxDb.Version=DB.6.0.80 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ETH_IRQn=true\:0\:0\:false\:false\:false\:true\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:false\:true\:false +NVIC.TIM6_DAC_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true +NVIC.TimeBase=TIM6_DAC_IRQn +NVIC.TimeBaseIP=TIM6 +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA1.Mode=RMII +PA1.Signal=ETH_REF_CLK +PA2.Mode=RMII +PA2.Signal=ETH_MDIO +PA7.Mode=RMII +PA7.Signal=ETH_CRS_DV +PB13.Mode=RMII +PB13.Signal=ETH_TXD1 +PB7.Locked=true +PB7.Signal=GPIO_Output +PC1.Mode=RMII +PC1.Signal=ETH_MDC +PC4.Mode=RMII +PC4.Signal=ETH_RXD0 +PC5.Mode=RMII +PC5.Signal=ETH_RXD1 +PD8.Locked=true +PD8.Mode=Asynchronous +PD8.Signal=USART3_TX +PD9.Locked=true +PD9.Mode=Asynchronous +PD9.Signal=USART3_RX +PG11.Locked=true +PG11.Mode=RMII +PG11.Signal=ETH_TX_EN +PG13.Locked=true +PG13.Mode=RMII +PG13.Signal=ETH_TXD0 +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F746ZGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.17.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=2 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=true +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=STCubeGenerated.ioc +ProjectManager.ProjectName=STCubeGenerated +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_RNG_Init-RNG-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.AHBFreq_Value=216000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=54000000 +RCC.APB1TimFreq_Value=108000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=108000000 +RCC.APB2TimFreq_Value=216000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=216000000 +RCC.EthernetFreq_Value=216000000 +RCC.FCLKCortexFreq_Value=216000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=216000000 +RCC.HSE_VALUE=25000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=54000000 +RCC.I2C2Freq_Value=54000000 +RCC.I2C3Freq_Value=54000000 +RCC.I2C4Freq_Value=54000000 +RCC.I2SFreq_Value=192000000 +RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value +RCC.LCDTFToutputFreq_Value=96000000 +RCC.LPTIM1Freq_Value=54000000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=216000000 +RCC.PLLCLKFreq_Value=216000000 +RCC.PLLI2SPCLKFreq_Value=192000000 +RCC.PLLI2SQCLKFreq_Value=192000000 +RCC.PLLI2SRCLKFreq_Value=192000000 +RCC.PLLI2SRoutputFreq_Value=192000000 +RCC.PLLM=8 +RCC.PLLN=216 +RCC.PLLQ=9 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLQoutputFreq_Value=48000000 +RCC.PLLSAIPCLKFreq_Value=192000000 +RCC.PLLSAIQCLKFreq_Value=192000000 +RCC.PLLSAIRCLKFreq_Value=192000000 +RCC.PLLSAIoutputFreq_Value=192000000 +RCC.RNGFreq_Value=48000000 +RCC.SAI1Freq_Value=192000000 +RCC.SAI2Freq_Value=192000000 +RCC.SDMMCFreq_Value=216000000 +RCC.SPDIFRXFreq_Value=192000000 +RCC.SYSCLKFreq_VALUE=216000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=54000000 +RCC.UART5Freq_Value=54000000 +RCC.UART7Freq_Value=54000000 +RCC.UART8Freq_Value=54000000 +RCC.USART1Freq_Value=108000000 +RCC.USART2Freq_Value=54000000 +RCC.USART3Freq_Value=54000000 +RCC.USART6Freq_Value=108000000 +RCC.USBFreq_Value=48000000 +RCC.VCOI2SOutputFreq_Value=384000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutputFreq_Value=432000000 +RCC.VCOSAIOutputFreq_Value=384000000 +USART3.IPParameters=VirtualMode-Asynchronous +USART3.VirtualMode-Asynchronous=VM_ASYNC +VP_RNG_VS_RNG.Mode=RNG_Activate +VP_RNG_VS_RNG.Signal=RNG_VS_RNG +VP_SYS_VS_tim6.Mode=TIM6 +VP_SYS_VS_tim6.Signal=SYS_VS_tim6 +board=custom diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c new file mode 100644 index 00000000..6004c6bb --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c @@ -0,0 +1,352 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "string.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "cmsis_os2.h" + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma location=0x2004c000 +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +#pragma location=0x2004c0a0 +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __CC_ARM ) /* MDK ARM Compiler */ + +__attribute__((at(0x2004c000))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +__attribute__((at(0x2004c0a0))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __GNUC__ ) /* GNU Compiler */ +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */ +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection"))); /* Ethernet Tx DMA Descriptors */ + +#endif + +ETH_TxPacketConfig TxConfig; + +ETH_HandleTypeDef heth; + +RNG_HandleTypeDef hrng; + +UART_HandleTypeDef huart3; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART3_UART_Init(void); +static void MX_ETH_Init(void); +static void MX_RNG_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +void mx_init(void) { + SystemClock_Config(); + MX_GPIO_Init(); + MX_USART3_UART_Init(); + MX_RNG_Init(); + MX_ETH_Init(); +} + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 216; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ETH Initialization Function + * @param None + * @retval None + */ +static void MX_ETH_Init(void) +{ + + /* USER CODE BEGIN ETH_Init 0 */ + + /* USER CODE END ETH_Init 0 */ + + static uint8_t MACAddr[6]; + + /* USER CODE BEGIN ETH_Init 1 */ + + /* USER CODE END ETH_Init 1 */ + heth.Instance = ETH; + MACAddr[0] = 0x00; + MACAddr[1] = 0x80; + MACAddr[2] = 0xE1; + MACAddr[3] = 0x00; + MACAddr[4] = 0x00; + MACAddr[5] = 0x00; + heth.Init.MACAddr = &MACAddr[0]; + heth.Init.MediaInterface = HAL_ETH_RMII_MODE; + heth.Init.TxDesc = DMATxDscrTab; + heth.Init.RxDesc = DMARxDscrTab; + heth.Init.RxBuffLen = 1524; + + /* USER CODE BEGIN MACADDRESS */ + + /* USER CODE END MACADDRESS */ + + if (HAL_ETH_Init(&heth) != HAL_OK) + { + Error_Handler(); + } + + memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig)); + TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; + TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; + TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; + /* USER CODE BEGIN ETH_Init 2 */ + + /* USER CODE END ETH_Init 2 */ + +} + +/** + * @brief RNG Initialization Function + * @param None + * @retval None + */ +static void MX_RNG_Init(void) +{ + + /* USER CODE BEGIN RNG_Init 0 */ + + /* USER CODE END RNG_Init 0 */ + + /* USER CODE BEGIN RNG_Init 1 */ + + /* USER CODE END RNG_Init 1 */ + hrng.Instance = RNG; + if (HAL_RNG_Init(&hrng) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RNG_Init 2 */ + + /* USER CODE END RNG_Init 2 */ + +} + +/** + * @brief USART3 Initialization Function + * @param None + * @retval None + */ +static void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET); + + /*Configure GPIO pin : PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM6 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM6) { + HAL_IncTick(); + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c new file mode 100644 index 00000000..cff0eb5b --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c @@ -0,0 +1,326 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ETH MSP Initialization +* This function configures the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspInit 0 */ + + /* USER CODE END ETH_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ETH_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* ETH interrupt Init */ + HAL_NVIC_SetPriority(ETH_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspInit 1 */ + + /* USER CODE END ETH_MspInit 1 */ + } + +} + +/** +* @brief ETH MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspDeInit 0 */ + + /* USER CODE END ETH_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11|GPIO_PIN_13); + + /* ETH interrupt DeInit */ + HAL_NVIC_DisableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspDeInit 1 */ + + /* USER CODE END ETH_MspDeInit 1 */ + } + +} + +/** +* @brief RNG MSP Initialization +* This function configures the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspInit 0 */ + + /* USER CODE END RNG_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_RNG_CLK_ENABLE(); + /* USER CODE BEGIN RNG_MspInit 1 */ + + /* USER CODE END RNG_MspInit 1 */ + } + +} + +/** +* @brief RNG MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspDeInit 0 */ + + /* USER CODE END RNG_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RNG_CLK_DISABLE(); + /* USER CODE BEGIN RNG_MspDeInit 1 */ + + /* USER CODE END RNG_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; + PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9); + + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_timebase_tim.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_timebase_tim.c new file mode 100644 index 00000000..b322b56f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_timebase_tim.c @@ -0,0 +1,137 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_timebase_TIM.c + * @brief HAL time base based on the hardware TIM. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" +#include "stm32f7xx_hal_tim.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_HandleTypeDef htim6; +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the TIM6 as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock, uwAPB1Prescaler = 0U; + + uint32_t uwPrescalerValue = 0U; + uint32_t pFLatency; + HAL_StatusTypeDef status; + + /* Enable TIM6 clock */ + __HAL_RCC_TIM6_CLK_ENABLE(); + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + + /* Get APB1 prescaler */ + uwAPB1Prescaler = clkconfig.APB1CLKDivider; + /* Compute TIM6 clock */ + if (uwAPB1Prescaler == RCC_HCLK_DIV1) + { + uwTimclock = HAL_RCC_GetPCLK1Freq(); + } + else + { + uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); + } + + /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + + /* Initialize TIM6 */ + htim6.Instance = TIM6; + + /* Initialize TIMx peripheral as follow: + + + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + + ClockDivision = 0 + + Counter direction = Up + */ + htim6.Init.Period = (1000000U / 1000U) - 1U; + htim6.Init.Prescaler = uwPrescalerValue; + htim6.Init.ClockDivision = 0; + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + + status = HAL_TIM_Base_Init(&htim6); + if (status == HAL_OK) + { + /* Start the TIM time Base generation in interrupt mode */ + status = HAL_TIM_Base_Start_IT(&htim6); + if (status == HAL_OK) + { + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Configure the TIM IRQ priority */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling TIM6 update interrupt. + * @param None + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable TIM6 update Interrupt */ + __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling TIM6 update interrupt. + * @param None + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Enable TIM6 Update interrupt */ + __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE); +} + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c new file mode 100644 index 00000000..31d671be --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c @@ -0,0 +1,178 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern TIM_HandleTypeDef htim6; + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M7 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + */ +void TIM6_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_TIM_IRQHandler(&htim6); + /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + + /* USER CODE END TIM6_DAC_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s new file mode 100644 index 00000000..e44d7b3f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s @@ -0,0 +1,468 @@ +;******************************************************************************* +;* File Name : startup_stm32f746xx.s +;* Author : MCD Application Team +;* Description : STM32F746xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2016 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000800 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00010000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c new file mode 100644 index 00000000..32e7fa5f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c @@ -0,0 +1,259 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS RAMDTCM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/project.script b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/project.script new file mode 100644 index 00000000..0f10b399 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Device/project.script @@ -0,0 +1,7 @@ +load STM32F746ZGTx +project name STCubeGenerated +project toolchain "MDK-ARM V5" +project path "C:\Users\scaprile\Documents\Keil\nucleo-f746zg-keil-baremetal\RTE\Device\STM32F746ZGTx\" +set tpl_path "C:\Users\scaprile\AppData\Local\Arm\Packs\Keil\STM32F7xx_DFP\2.15.1\MDK\CubeMX" +set dest_path "STM32F746ZGTx" +SetCopyLibrary "copy as reference" diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Network_Library/mongoose_custom.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Network_Library/mongoose_custom.h new file mode 100644 index 00000000..a0726b9f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/Network_Library/mongoose_custom.h @@ -0,0 +1,77 @@ + +// <<< Use Configuration Wizard in Context Menu >>> + +// System Architecture +// <0=> Bare metal +// <1=> FreeRTOS +// <2=> CMSIS-RTOS v1 +// <3=> CMSIS-RTOS v2 +// Select either bare metal operation or a supported RTOS +// "FreeRTOS" uses direct FreeRTOS calls +// "CMSIS-RTOS v1" supports only Keil RTX through API v1 +// "CMSIS-RTOS v2" supports Keil RTX5 and FreeRTOS through API v2 + +#define MG_CMSISPACK_ARCH 3 + + +// Networking support +// Networking stack +// <0=> Built-in +// <1=> lwIP +// <2=> FreeRTOS-Plus-TCP +// <3=> MDK (RL) +// Select the networking stack to use with Mongoose Library +// The built-in stack can run on bare metal or over any RTOS +// "lwIP" requires using an RTOS and BSD socket mode +// "MDK" requires using CMSIS-RTOS1 (RTX + RL) or CMSIS-RTOS2 (MDK Plus or Pro), and BSD socket mode +#define MG_CMSISPACK_NET 0 + +// Use Mbed-TLS +// Mongoose will use Mbed-TLS calls for TLS-related functionality +#define MG_ENABLE_MBEDTLS 0 +// + + +// Enable custom mg_millis() +// Use a user-provided function to get uptime in milliseconds, otherwise Mongoose will default to using time(). Except for bare metal, Mongoose will use the time base for the configured architecture +//#define MG_ENABLE_CUSTOM_MILLIS 1 +// + + +// Enable custom mg_rand() +// Use a user-provided function to generate random numbers, otherwise Mongoose will default to using rand() +#define MG_ENABLE_CUSTOM_RANDOM 1 +// + + +// Filesystem support +// Enable packed (embedded) filesystem +#define MG_ENABLE_PACKED_FS 1 +// + + +// <<< end of configuration section >>> + +// Translate to Mongoose macros +#if MG_CMSISPACK_ARCH == 1 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_FREERTOS +#elif MG_CMSISPACK_ARCH == 2 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_CMSIS_RTOS1 +#elif MG_CMSISPACK_ARCH == 3 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_CMSIS_RTOS2 +#endif +#if MG_CMSISPACK_NET == 0 +#define MG_ENABLE_TCPIP 1 +#elif MG_CMSISPACK_NET == 1 +#define MG_ENABLE_LWIP 1 +#elif MG_CMSISPACK_NET == 2 +#define MG_ENABLE_FREERTOS_TCP 1 +#elif MG_CMSISPACK_NET == 3 +#define MG_ENABLE_RL 1 +#endif + + +// Add your customization below this comment diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/RTOS/FreeRTOSConfig.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/RTOS/FreeRTOSConfig.h new file mode 100644 index 00000000..af58fc50 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/RTOS/FreeRTOSConfig.h @@ -0,0 +1,276 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * -------------------------------------------------------------------------- + * + * $Revision: V10.4.0 + * + * Project: CMSIS-FreeRTOS + * Title: FreeRTOS configuration definitions + * + * --------------------------------------------------------------------------*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +#if (defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)) +#include + +#include "RTE_Components.h" +#include CMSIS_device_header +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Minimal stack size [words] <0-65535> +// Stack for idle task and default task stack in words. +// Default: 128 +#define configMINIMAL_STACK_SIZE ((uint16_t)(128)) + +// Total heap size [bytes] <0-0xFFFFFFFF> +// Heap memory size in bytes. +// Default: 8192 +#define configTOTAL_HEAP_SIZE ((size_t)65536) + +// Kernel tick frequency [Hz] <0-0xFFFFFFFF> +// Kernel tick rate in Hz. +// Default: 1000 +#define configTICK_RATE_HZ ((TickType_t)1000) + +// Timer task stack depth [words] <0-65535> +// Stack for timer task in words. +// Default: 80 +#define configTIMER_TASK_STACK_DEPTH 80 + +// Timer task priority <0-56> +// Timer task priority. +// Default: 40 (High) +#define configTIMER_TASK_PRIORITY 40 + +// Timer queue length <0-1024> +// Timer command queue length. +// Default: 5 +#define configTIMER_QUEUE_LENGTH 5 + +// Preemption interrupt priority +// Maximum priority of interrupts that are safe to call FreeRTOS API. +// Default: 16 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 16 + +// Use time slicing +// Enable setting to use timeslicing. +// Default: 1 +#define configUSE_TIME_SLICING 1 + +// Use tickless idle +// Enable low power tickless mode to stop the periodic tick interrupt during idle periods or +// disable it to keep the tick interrupt running at all times. +// Default: 0 +#define configUSE_TICKLESS_IDLE 0 + +// Idle should yield +// Control Yield behaviour of the idle task. +// Default: 1 +#define configIDLE_SHOULD_YIELD 1 + +// Check for stack overflow +// <0=>Disable <1=>Method one <2=>Method two +// Enable or disable stack overflow checking. +// Callback function vApplicationStackOverflowHook implementation is required when stack checking is enabled. +// Default: 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 + +// Use idle hook +// Enable callback function call on each idle task iteration. +// Callback function vApplicationIdleHook implementation is required when idle hook is enabled. +// Default: 0 +#define configUSE_IDLE_HOOK 0 + +// Use tick hook +// Enable callback function call during each tick interrupt. +// Callback function vApplicationTickHook implementation is required when tick hook is enabled. +// Default: 0 +#define configUSE_TICK_HOOK 0 + +// Use deamon task startup hook +// Enable callback function call when timer service starts. +// Callback function vApplicationDaemonTaskStartupHook implementation is required when deamon task startup hook is enabled. +// Default: 0 +#define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + +// Use malloc failed hook +// Enable callback function call when out of dynamic memory. +// Callback function vApplicationMallocFailedHook implementation is required when malloc failed hook is enabled. +// Default: 0 +#define configUSE_MALLOC_FAILED_HOOK 0 + +// Queue registry size +// Define maximum number of queue objects registered for debug purposes. +// The queue registry is used by kernel aware debuggers to locate queue and semaphore structures and display associated text names. +// Default: 0 +#define configQUEUE_REGISTRY_SIZE 0 + +// Event Recorder configuration +// Initialize and setup Event Recorder level filtering. +// Settings have no effect when Event Recorder is not present. + +// Initialize Event Recorder +// Initialize Event Recorder before FreeRTOS kernel start. +// Default: 1 +#define configEVR_INITIALIZE 1 + +// Setup recording level filter +// Enable configuration of FreeRTOS events recording level +// Default: 1 +#define configEVR_SETUP_LEVEL 1 + +// Tasks functions +// Define event recording level bitmask for events generated from Tasks functions. +// Default: 0x05 +// <0x00=>Off <0x01=>Errors <0x05=>Errors + Operation <0x0F=>All +#define configEVR_LEVEL_TASKS 0x05 + +// Queue functions +// Define event recording level bitmask for events generated from Queue functions. +// Default: 0x05 +// <0x00=>Off <0x01=>Errors <0x05=>Errors + Operation <0x0F=>All +#define configEVR_LEVEL_QUEUE 0x05 + +// Timer functions +// Define event recording level bitmask for events generated from Timer functions. +// Default: 0x05 +// <0x00=>Off <0x01=>Errors <0x05=>Errors + Operation <0x0F=>All +#define configEVR_LEVEL_TIMERS 0x05 + +// Event Groups functions +// Define event recording level bitmask for events generated from Event Groups functions. +// Default: 0x05 +// <0x00=>Off <0x01=>Errors <0x05=>Errors + Operation <0x0F=>All +#define configEVR_LEVEL_EVENTGROUPS 0x05 + +// Heap functions +// Define event recording level bitmask for events generated from Heap functions. +// Default: 0x05 +// <0x00=>Off <0x01=>Errors <0x05=>Errors + Operation <0x0F=>All +#define configEVR_LEVEL_HEAP 0x05 + +// Stream Buffer functions +// Define event recording level bitmask for events generated from Stream Buffer functions. +// Default: 0x05 +// <0x00=>Off <0x01=>Errors <0x05=>Errors + Operation <0x0F=>All +#define configEVR_LEVEL_STREAMBUFFER 0x05 +// +// + +// Port Specific Features +// Enable and configure port specific features. +// Check FreeRTOS documentation for definitions that apply for the used port. + +// Use Floating Point Unit +// Using Floating Point Unit (FPU) affects context handling. +// Enable FPU when application uses floating point operations. +// Default: 1 +#define configENABLE_FPU 1 + +// Use M-Profile Vector Extension +// Using M-Profile Vector Extension (MVE) affects context handling. +// Enable MVE when application uses signal processing and ML algorithms. +// Default: 0 +#define configENABLE_MVE 0 + +// Use Memory Protection Unit +// Using Memory Protection Unit (MPU) requires detailed memory map definition. +// This setting is only releavant for MPU enabled ports. +// Default: 0 +#define configENABLE_MPU 0 + +// Use TrustZone Secure Side Only +// This settings prevents FreeRTOS contex switch to Non-Secure side. +// Enable this setting when FreeRTOS runs on the Secure side only. +#define configRUN_FREERTOS_SECURE_ONLY 0 + +// Use TrustZone Security Extension +// Using TrustZone affects context handling. +// Enable TrustZone when FreeRTOS runs on the Non-Secure side and calls functions from the Secure side. +// Default: 1 +#define configENABLE_TRUSTZONE 0 + +// Minimal secure stack size [words] <0-65535> +// Stack for idle task Secure side context in words. +// This setting is only relevant when TrustZone extension is enabled. +// Default: 128 +#define configMINIMAL_SECURE_STACK_SIZE ((uint32_t)128) +// + +//------------- <<< end of configuration section >>> --------------------------- + +/* Defines needed by FreeRTOS to implement CMSIS RTOS2 API. Do not change! */ +#define configCPU_CLOCK_HZ (SystemCoreClock) +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 +#define configUSE_PREEMPTION 1 +#define configUSE_TIMERS 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_TASK_NOTIFICATIONS 1 +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configMAX_PRIORITIES 56 +#define configKERNEL_INTERRUPT_PRIORITY 255 + +/* Defines that include FreeRTOS functions which implement CMSIS RTOS2 API. Do not change! */ +#define INCLUDE_xEventGroupSetBitsFromISR 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskDelayUntil 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +/* Map the FreeRTOS port interrupt handlers to their CMSIS standard names. */ +#define xPortPendSVHandler PendSV_Handler +#define vPortSVCHandler SVC_Handler + +/* Ensure Cortex-M port compatibility. */ +#define SysTick_Handler xPortSysTickHandler + +#if (defined(__ARMCC_VERSION) || defined(__GNUC__) || defined(__ICCARM__)) +/* Include debug event definitions */ +#include "freertos_evr.h" +#endif + +#endif /* FREERTOS_CONFIG_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/_Target_1/Pre_Include_Global.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/_Target_1/Pre_Include_Global.h new file mode 100644 index 00000000..8aabd0e0 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/_Target_1/Pre_Include_Global.h @@ -0,0 +1,17 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'device-dashboard' + * Target: 'Target 1' + */ + +#ifndef PRE_INCLUDE_GLOBAL_H +#define PRE_INCLUDE_GLOBAL_H + +/* Keil::Device:STM32Cube HAL:Common:1.3.0 */ +#define USE_HAL_DRIVER + + +#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/_Target_1/RTE_Components.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/_Target_1/RTE_Components.h new file mode 100644 index 00000000..8d6b1d26 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/RTE/_Target_1/RTE_Components.h @@ -0,0 +1,61 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'device-dashboard' + * Target: 'Target 1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f7xx.h" + +/* ARM.FreeRTOS::RTOS:Config:CMSIS RTOS2:10.5.1 */ +#define RTE_RTOS_FreeRTOS_CONFIG_RTOS2 /* RTOS FreeRTOS Config for CMSIS RTOS2 API */ +/* ARM.FreeRTOS::RTOS:Core:Cortex-M:10.5.1 */ +#define RTE_RTOS_FreeRTOS_CORE /* RTOS FreeRTOS Core */ +/* ARM.FreeRTOS::RTOS:Event Groups:10.5.1 */ +#define RTE_RTOS_FreeRTOS_EVENTGROUPS /* RTOS FreeRTOS Event Groups */ +/* ARM.FreeRTOS::RTOS:Heap:Heap_4:10.5.1 */ +#define RTE_RTOS_FreeRTOS_HEAP_4 /* RTOS FreeRTOS Heap 4 */ +/* ARM.FreeRTOS::RTOS:Timers:10.5.1 */ +#define RTE_RTOS_FreeRTOS_TIMERS /* RTOS FreeRTOS Timers */ +/* ARM::CMSIS:RTOS2:FreeRTOS:Cortex-M:10.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_FreeRTOS /* CMSIS-RTOS2 FreeRTOS */ +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:User:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ +/* Keil::Device:STM32Cube Framework:STM32CubeMX:1.1.0 */ +#define RTE_DEVICE_FRAMEWORK_CUBE_MX +/* Keil::Device:STM32Cube HAL:Common:1.3.0 */ +#define RTE_DEVICE_HAL_COMMON +/* Keil::Device:STM32Cube HAL:Cortex:1.3.0 */ +#define RTE_DEVICE_HAL_CORTEX +/* Keil::Device:STM32Cube HAL:DMA:1.3.0 */ +#define RTE_DEVICE_HAL_DMA +/* Keil::Device:STM32Cube HAL:ETH:1.3.0 */ +#define RTE_DEVICE_HAL_ETH +/* Keil::Device:STM32Cube HAL:GPIO:1.3.0 */ +#define RTE_DEVICE_HAL_GPIO +/* Keil::Device:STM32Cube HAL:PWR:1.3.0 */ +#define RTE_DEVICE_HAL_PWR +/* Keil::Device:STM32Cube HAL:RCC:1.3.0 */ +#define RTE_DEVICE_HAL_RCC +/* Keil::Device:STM32Cube HAL:RNG:1.3.0 */ +#define RTE_DEVICE_HAL_RNG +/* Keil::Device:STM32Cube HAL:TIM:1.3.0 */ +#define RTE_DEVICE_HAL_TIM +/* Keil::Device:STM32Cube HAL:UART:1.3.0 */ +#define RTE_DEVICE_HAL_UART +/* Keil::Device:Startup:1.2.5 */ +#define RTE_DEVICE_STARTUP_STM32F7XX /* Device Startup for STM32F7 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/device-dashboard.uvguix b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/device-dashboard.uvguix new file mode 100644 index 00000000..021f818a --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/device-dashboard.uvguix @@ -0,0 +1,3662 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 1920 + 1080 + + + + + + 1 + 0 + + 100 + 2 + + RTE\Network_Library\mongoose_custom.h + 0 + 1 + 1 + 1 + + 0 + + + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + 43 + 79 + 91 + 1 + + 0 + + + .\main.c + 0 + 1 + 72 + 1 + + 0 + + + RTE\Device\STM32F746ZGTx\startup_stm32f746xx.s + 0 + 180 + 188 + 1 + + 0 + + + RTE\RTOS\FreeRTOSConfig.h + 29 + 190 + 191 + 1 + + 0 + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/device-dashboard.uvoptx b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/device-dashboard.uvoptx new file mode 100644 index 00000000..cea4bd03 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/device-dashboard.uvoptx @@ -0,0 +1,369 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 16000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + ST-LINKIII-KEIL_SWO + -U-O206 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(5BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FF1STM32F7xTCM_1024.FLM -FS1200000 -FL1100000 -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + + + + + + 1 + 0 + 0x20000000 + 0 + + + + C:\Users\scaprile\AppData\Local\Arm\Packs\ARM\CMSIS-FreeRTOS\10.5.1\CMSIS\RTOS2\FreeRTOS\FreeRTOS.scvd + ARM.CMSIS-FreeRTOS.10.5.1 + 1 + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 1 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + .\hal.h + hal.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + .\net.c + net.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + .\packed_fs.c + packed_fs.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + .\syscalls.c + syscalls.c + 0 + 0 + + + + + :STM32CubeMX:Common Sources + 1 + 0 + 0 + 0 + + 2 + 6 + 1 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + main.c + 0 + 0 + + + 2 + 7 + 5 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Inc\stm32f7xx_it.h + stm32f7xx_it.h + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + stm32f7xx_it.c + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + + + ::Compiler + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + + ::Network Library + 0 + 0 + 0 + 1 + + + + ::RTOS + 1 + 0 + 0 + 1 + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/device-dashboard.uvprojx b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/device-dashboard.uvprojx new file mode 100644 index 00000000..fb1834bd --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/device-dashboard.uvprojx @@ -0,0 +1,632 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + STM32F746ZGTx + STMicroelectronics + Keil.STM32F7xx_DFP.2.15.1 + https://www.keil.com/pack/ + IRAM(0x20010000,0x40000) IRAM2(0x20000000,0x10000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + 0 + $$Device:STM32F746ZGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h + + + + + + + + + + $$Device:STM32F746ZGTx$CMSIS\SVD\STM32F746.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + device-dashboard + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x200000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 6 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + + -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion -Wno-unused-parameter -Wconversion -Wno-sign-conversion -fno-common -fdata-sections + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20010000 + + + + + + + + + + + + + Source Group 1 + + + hal.h + 5 + .\hal.h + + + main.c + 1 + .\main.c + + + net.c + 1 + .\net.c + + + packed_fs.c + 1 + .\packed_fs.c + + + syscalls.c + 1 + .\syscalls.c + + + + + :STM32CubeMX:Common Sources + + + main.c + 1 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + + + stm32f7xx_it.h + 5 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Inc\stm32f7xx_it.h + + + stm32f7xx_it.c + 1 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + + + + + ::CMSIS + + + ::Compiler + + + ::Device + + + ::Network Library + + + ::RTOS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\STM32F746ZGTx\startup_stm32f746xx.s + + + + + + + + RTE\Device\STM32F746ZGTx\system_stm32f7xx.c + + + + + + + + RTE\Network_Library\mongoose_custom.h + + + + + + + + RTE\RTOS\FreeRTOSConfig.h + + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/hal.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/hal.h new file mode 100644 index 00000000..a0ec0b30 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/hal.h @@ -0,0 +1,21 @@ +// Copyright (c) 2022-23 Cesanta Software Limited +// All rights reserved +// https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf + +#pragma once + +#include + +#ifndef UART_DEBUG +#define UART_DEBUG USART3 +#endif + + +#define UUID ((uint8_t *) UID_BASE) // Unique 96-bit chip ID. TRM 41.1 + +// Helper macro for MAC generation +#define GENERATE_LOCALLY_ADMINISTERED_MAC() \ + { \ + 2, UUID[0] ^ UUID[1], UUID[2] ^ UUID[3], UUID[4] ^ UUID[5], \ + UUID[6] ^ UUID[7] ^ UUID[8], UUID[9] ^ UUID[10] ^ UUID[11] \ + } diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/main.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/main.c new file mode 100644 index 00000000..75167959 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/main.c @@ -0,0 +1,81 @@ +// Copyright (c) 2023 Cesanta Software Limited +// All rights reserved + +#include "hal.h" +#include "mongoose.h" +#include "main.h" +#include "cmsis_os2.h" + +#define BLINK_PERIOD_MS 1000 // LED blinking period in millis + + +void mg_random(void *buf, size_t len) { // Use on-board RNG + extern RNG_HandleTypeDef hrng; + for (size_t n = 0; n < len; n += sizeof(uint32_t)) { + uint32_t r; + HAL_RNG_GenerateRandomNumber(&hrng, &r); + memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r)); + } +} + +static void timer_fn(void *arg) { + struct mg_tcpip_if *ifp = arg; // And show + const char *names[] = {"down", "up", "ready"}; // network stats + MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u", + names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent, + ifp->ndrop, ifp->nerr)); +} + +static void server(void *args) { + struct mg_mgr mgr; // Initialise Mongoose event manager + mg_mgr_init(&mgr); // and attach it to the interface + mg_log_set(MG_LL_DEBUG); // Set log level + + // Initialise Mongoose network stack + // Specify MAC address, and IP/mask/GW in network byte order for static + // IP configuration. If IP/mask/GW are unset, DHCP is going to be used + struct mg_tcpip_driver_stm32_data driver_data = {.mdc_cr = 4}; + struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(), + .driver = &mg_tcpip_driver_stm32, + .driver_data = &driver_data}; + mg_tcpip_init(&mgr, &mif); + mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif); + + MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac)); + while (mif.state != MG_TCPIP_STATE_READY) { + mg_mgr_poll(&mgr, 0); + } + + MG_INFO(("Initialising application...")); + extern void device_dashboard_fn(struct mg_connection *, int, void *, void *); + mg_http_listen(&mgr, "http://0.0.0.0", device_dashboard_fn, NULL); + + MG_INFO(("Starting event loop")); + for (;;) mg_mgr_poll(&mgr, 1); // Infinite event loop + (void) args; +} + +static void blinker(void *args) { + for (;;) { + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_7); // Blink On-board blue LED + osDelay((osKernelGetTickFreq() * BLINK_PERIOD_MS) / 1000U); + } + (void) args; +} + +extern void mx_init(void); + +int main(void) { + mx_init(); // Setup clock and all peripherals configured in CubeMX + // Initialise random number generator + // Initialise ethernet pins + osKernelInitialize(); // Initialize CMSIS-RTOS + osThreadNew(blinker, NULL, NULL); // Create the blinker thread with a default stack size + const osThreadAttr_t server_attr = { + .stack_size = 8192 // Create the server thread with a stack size of 8KB bytes + }; + osThreadNew(server, NULL, &server_attr); + osKernelStart(); // This blocks + return 0; +} + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/syscalls.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/syscalls.c new file mode 100644 index 00000000..79113968 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-freertos_cmsis2/syscalls.c @@ -0,0 +1,10 @@ +#include +#include + +#include "main.h" + +int stdout_putchar (int ch) { + extern UART_HandleTypeDef huart3; + HAL_UART_Transmit(&huart3, (const uint8_t *)&ch, 1, 100); + return ch; +} diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx-mdk/EventRecorderStub.scvd b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx-mdk/EventRecorderStub.scvd new file mode 100644 index 00000000..0fb3ee58 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx-mdk/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx-mdk/README.md b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx-mdk/README.md new file mode 100644 index 00000000..b8358a0b --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx-mdk/README.md @@ -0,0 +1,7 @@ +# Web device dashboard on NUCLEO-F746ZG, built on Keil MDK using RTX and the MDK Plus stack + +- Open this example with Keil uVision +- Build it +- Run/Debug it + +Mongoose configuration is in mongoose_custom.h, inside Network_Library diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx-mdk/RTE/CMSIS/RTX_Conf_CM.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx-mdk/RTE/CMSIS/RTX_Conf_CM.c new file mode 100644 index 00000000..62662fbb --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx-mdk/RTE/CMSIS/RTX_Conf_CM.c @@ -0,0 +1,304 @@ +/*---------------------------------------------------------------------------- + * CMSIS-RTOS - RTX + *---------------------------------------------------------------------------- + * Name: RTX_Conf_CM.C + * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M + * Rev.: V4.70.1 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2016 ARM Germany GmbH. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + +#include "cmsis_os.h" + + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Thread Configuration +// ======================= +// +// Number of concurrent running user threads <1-250> +// Defines max. number of user threads that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 6 +#endif + +// Default Thread stack size [bytes] <64-4096:8><#/4> +// Defines default stack size for threads with osThreadDef stacksz = 0 +// Default: 200 +#ifndef OS_STKSIZE + #define OS_STKSIZE 50 // this stack size value is in words +#endif + +// Main Thread stack size [bytes] <64-32768:8><#/4> +// Defines stack size for main thread. +// Default: 200 +#ifndef OS_MAINSTKSIZE + #define OS_MAINSTKSIZE 256 // this stack size value is in words +#endif + +// Number of threads with user-provided stack size <0-250> +// Defines the number of threads with user-provided stack size. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 4 +#endif + +// Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4> +// Defines the combined stack size for threads with user-provided stack size. +// Default: 0 +#ifndef OS_PRIVSTKSIZE + #define OS_PRIVSTKSIZE 16384 // this stack size value is in words +#endif + +// Stack overflow checking +// Enable stack overflow checks at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Stack usage watermark +// Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer. +// Enabling this option increases significantly the execution time of osThreadCreate. +#ifndef OS_STKINIT +#define OS_STKINIT 0 +#endif + +// Processor mode for thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 1 +#endif + +// + +// RTX Kernel Timer Tick Configuration +// ====================================== +// Use Cortex-M SysTick timer as RTX Kernel Timer +// Cortex-M processors provide in most cases a SysTick timer that can be used as +// as time-base for RTX. +#ifndef OS_SYSTICK + #define OS_SYSTICK 1 +#endif +// +// RTOS Kernel Timer input clock frequency [Hz] <1-1000000000> +// Defines the input frequency of the RTOS Kernel Timer. +// When the Cortex-M SysTick timer is used, the input clock +// is on most systems identical with the core clock. +#ifndef OS_CLOCK + #define OS_CLOCK 216000000 +#endif + +// RTX Timer tick interval value [us] <1-1000000> +// The RTX Timer tick interval value is used to calculate timeout values. +// When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer. +// Default: 1000 (1ms) +#ifndef OS_TICK + #define OS_TICK 1000 +#endif + +// + +// System Configuration +// ======================= +// +// Round-Robin Thread switching +// =============================== +// +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Defines how long a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// User Timers +// ============== +// Enables user Timers +#ifndef OS_TIMERS + #define OS_TIMERS 1 +#endif + +// Timer Thread Priority +// <1=> Low +// <2=> Below Normal <3=> Normal <4=> Above Normal +// <5=> High +// <6=> Realtime (highest) +// Defines priority for Timer Thread +// Default: High +#ifndef OS_TIMERPRIO + #define OS_TIMERPRIO 5 +#endif + +// Timer Thread stack size [bytes] <64-4096:8><#/4> +// Defines stack size for Timer thread. +// Default: 200 +#ifndef OS_TIMERSTKSZ + #define OS_TIMERSTKSZ 50 // this stack size value is in words +#endif + +// Timer Callback Queue size <1-32> +// Number of concurrent active timer callback functions. +// Default: 4 +#ifndef OS_TIMERCBQS + #define OS_TIMERCBQS 4 +#endif + +// + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the interrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +/// \brief The idle demon is running when no other thread is ready to run +void os_idle_demon (void) { + + for (;;) { + /* HERE: include optional user code to be executed when no thread runs.*/ + } +} + +#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer + +/*--------------------------- os_tick_init ----------------------------------*/ + +/// \brief Initializes an alternative hardware timer as RTX kernel timer +/// \return IRQ number of the alternative hardware timer +int os_tick_init (void) { + return (-1); /* Return IRQ number of timer (0..239) */ +} + +/*--------------------------- os_tick_val -----------------------------------*/ + +/// \brief Get alternative hardware timer's current value (0 .. OS_TRV) +/// \return Current value of the alternative hardware timer +uint32_t os_tick_val (void) { + return (0); +} + +/*--------------------------- os_tick_ovf -----------------------------------*/ + +/// \brief Get alternative hardware timer's overflow flag +/// \return Overflow flag\n +/// - 1 : overflow +/// - 0 : no overflow +uint32_t os_tick_ovf (void) { + return (0); +} + +/*--------------------------- os_tick_irqack --------------------------------*/ + +/// \brief Acknowledge alternative hardware timer interrupt +void os_tick_irqack (void) { + /* ... */ +} + +#endif // (OS_SYSTICK == 0) + +/*--------------------------- os_error --------------------------------------*/ + +/* OS Error Codes */ +#define OS_ERROR_STACK_OVF 1 +#define OS_ERROR_FIFO_OVF 2 +#define OS_ERROR_MBX_OVF 3 +#define OS_ERROR_TIMER_OVF 4 + +extern osThreadId svcThreadGetId (void); + +/// \brief Called when a runtime error is detected +/// \param[in] error_code actual error code that has been detected +void os_error (uint32_t error_code) { + + /* HERE: include optional code to be executed on runtime error. */ + switch (error_code) { + case OS_ERROR_STACK_OVF: + /* Stack overflow detected for the currently running task. */ + /* Thread can be identified by calling svcThreadGetId(). */ + break; + case OS_ERROR_FIFO_OVF: + /* ISR FIFO Queue buffer overflow detected. */ + break; + case OS_ERROR_MBX_OVF: + /* Mailbox overflow detected. */ + break; + case OS_ERROR_TIMER_OVF: + /* User Timer Callback Queue overflow detected. */ + break; + default: + break; + } + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include "RTX_CM_lib.h" + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx-mdk/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx-mdk/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc new file mode 100644 index 00000000..891cb840 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx-mdk/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc @@ -0,0 +1,64 @@ + + + + + Keil + FrameworkCubeMX + STM32CubeMX generated pack description + project-path + + + - Generated: 23/05/2023 17:18:35 + + + + + STM32CubeMX Environment + + $SMDK/CubeMX/STM32CubeMXLauncher + $PRTE/Device/STM32F746ZGTx + + + + + + + + + + STM32Cube Framework + + + + Condition to include CMSIS core and Device Startup components + + + + + + + + + + + + + + + Configuration via STM32CubeMX + + #define RTE_DEVICE_FRAMEWORK_CUBE_MX + + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/MX_Device.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/MX_Device.h new file mode 100644 index 00000000..2d89e311 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/MX_Device.h @@ -0,0 +1,212 @@ +/****************************************************************************** + * File Name : MX_Device.h + * Date : 23/05/2023 17:02:23 + * Description : STM32Cube MX parameter definitions + * Note : This file is generated by STM32CubeMX (DO NOT EDIT!) + ******************************************************************************/ + +#ifndef __MX_DEVICE_H +#define __MX_DEVICE_H + +/*---------------------------- Clock Configuration ---------------------------*/ + +#define MX_LSI_VALUE 32000 +#define MX_LSE_VALUE 32768 +#define MX_HSI_VALUE 16000000 +#define MX_HSE_VALUE 25000000 +#define MX_EXTERNAL_CLOCK_VALUE 12288000 +#define MX_SYSCLKFreq_VALUE 216000000 +#define MX_HCLKFreq_Value 216000000 +#define MX_FCLKCortexFreq_Value 216000000 +#define MX_CortexFreq_Value 216000000 +#define MX_AHBFreq_Value 216000000 +#define MX_APB1Freq_Value 54000000 +#define MX_APB2Freq_Value 108000000 +#define MX_APB1TimFreq_Value 108000000 +#define MX_APB2TimFreq_Value 216000000 +#define MX_EthernetFreq_Value 216000000 +#define MX_CECFreq_Value 32786 +#define MX_LCDTFToutputFreq_Value 96000000 +#define MX_I2C1Freq_Value 54000000 +#define MX_I2C2Freq_Value 54000000 +#define MX_I2C3Freq_Value 54000000 +#define MX_I2C4Freq_Value 54000000 +#define MX_I2SFreq_Value 192000000 +#define MX_SAI1Freq_Value 192000000 +#define MX_SAI2Freq_Value 192000000 +#define MX_SDMMCFreq_Value 216000000 +#define MX_RTCFreq_Value 32000 +#define MX_USART1Freq_Value 108000000 +#define MX_USART2Freq_Value 54000000 +#define MX_USART3Freq_Value 54000000 +#define MX_UART4Freq_Value 54000000 +#define MX_UART5Freq_Value 54000000 +#define MX_UART8Freq_Value 54000000 +#define MX_UART7Freq_Value 54000000 +#define MX_USART6Freq_Value 108000000 +#define MX_USBFreq_Value 48000000 +#define MX_WatchDogFreq_Value 32000 +#define MX_LPTIM1Freq_Value 54000000 +#define MX_SPDIFRXFreq_Value 192000000 +#define MX_MCO1PinFreq_Value 16000000 +#define MX_MCO2PinFreq_Value 216000000 + +/*-------------------------------- CORTEX_M7 --------------------------------*/ + +#define MX_CORTEX_M7 1 + +/* GPIO Configuration */ + +/*-------------------------------- ETH --------------------------------*/ + +#define MX_ETH 1 + +/* GPIO Configuration */ + +/* Pin PA1 */ +#define MX_ETH_REF_CLK_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_REF_CLK_Pin PA1 +#define MX_ETH_REF_CLK_GPIOx GPIOA +#define MX_ETH_REF_CLK_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_REF_CLK_GPIO_Pin GPIO_PIN_1 +#define MX_ETH_REF_CLK_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_REF_CLK_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PA7 */ +#define MX_ETH_CRS_DV_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_CRS_DV_Pin PA7 +#define MX_ETH_CRS_DV_GPIOx GPIOA +#define MX_ETH_CRS_DV_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_CRS_DV_GPIO_Pin GPIO_PIN_7 +#define MX_ETH_CRS_DV_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_CRS_DV_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC4 */ +#define MX_ETH_RXD0_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_RXD0_Pin PC4 +#define MX_ETH_RXD0_GPIOx GPIOC +#define MX_ETH_RXD0_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_RXD0_GPIO_Pin GPIO_PIN_4 +#define MX_ETH_RXD0_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_RXD0_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC5 */ +#define MX_ETH_RXD1_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_RXD1_Pin PC5 +#define MX_ETH_RXD1_GPIOx GPIOC +#define MX_ETH_RXD1_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_RXD1_GPIO_Pin GPIO_PIN_5 +#define MX_ETH_RXD1_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_RXD1_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PG11 */ +#define MX_ETH_TX_EN_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TX_EN_Pin PG11 +#define MX_ETH_TX_EN_GPIOx GPIOG +#define MX_ETH_TX_EN_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TX_EN_GPIO_Pin GPIO_PIN_11 +#define MX_ETH_TX_EN_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TX_EN_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PA2 */ +#define MX_ETH_MDIO_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_MDIO_Pin PA2 +#define MX_ETH_MDIO_GPIOx GPIOA +#define MX_ETH_MDIO_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_MDIO_GPIO_Pin GPIO_PIN_2 +#define MX_ETH_MDIO_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_MDIO_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PB13 */ +#define MX_ETH_TXD1_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TXD1_Pin PB13 +#define MX_ETH_TXD1_GPIOx GPIOB +#define MX_ETH_TXD1_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TXD1_GPIO_Pin GPIO_PIN_13 +#define MX_ETH_TXD1_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TXD1_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PG13 */ +#define MX_ETH_TXD0_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TXD0_Pin PG13 +#define MX_ETH_TXD0_GPIOx GPIOG +#define MX_ETH_TXD0_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TXD0_GPIO_Pin GPIO_PIN_13 +#define MX_ETH_TXD0_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TXD0_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC1 */ +#define MX_ETH_MDC_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_MDC_Pin PC1 +#define MX_ETH_MDC_GPIOx GPIOC +#define MX_ETH_MDC_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_MDC_GPIO_Pin GPIO_PIN_1 +#define MX_ETH_MDC_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_MDC_GPIO_Mode GPIO_MODE_AF_PP + +/* NVIC Configuration */ + +/* NVIC ETH_IRQn */ +#define MX_ETH_IRQn_interruptPremptionPriority 0 +#define MX_ETH_IRQn_PriorityGroup NVIC_PRIORITYGROUP_4 +#define MX_ETH_IRQn_Subriority 0 + +/*-------------------------------- RNG --------------------------------*/ + +#define MX_RNG 1 + +/* GPIO Configuration */ + +/*-------------------------------- SYS --------------------------------*/ + +#define MX_SYS 1 + +/* GPIO Configuration */ + +/*-------------------------------- USART3 --------------------------------*/ + +#define MX_USART3 1 + +#define MX_USART3_VM VM_ASYNC + +/* GPIO Configuration */ + +/* Pin PD8 */ +#define MX_USART3_TX_GPIO_ModeDefaultPP GPIO_MODE_AF_PP +#define MX_USART3_TX_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_USART3_TX_Pin PD8 +#define MX_USART3_TX_GPIOx GPIOD +#define MX_USART3_TX_GPIO_PuPd GPIO_NOPULL +#define MX_USART3_TX_GPIO_Pin GPIO_PIN_8 +#define MX_USART3_TX_GPIO_AF GPIO_AF7_USART3 + +/* Pin PD9 */ +#define MX_USART3_RX_GPIO_ModeDefaultPP GPIO_MODE_AF_PP +#define MX_USART3_RX_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_USART3_RX_Pin PD9 +#define MX_USART3_RX_GPIOx GPIOD +#define MX_USART3_RX_GPIO_PuPd GPIO_NOPULL +#define MX_USART3_RX_GPIO_Pin GPIO_PIN_9 +#define MX_USART3_RX_GPIO_AF GPIO_AF7_USART3 + +/*-------------------------------- NVIC --------------------------------*/ + +#define MX_NVIC 1 + +/*-------------------------------- GPIO --------------------------------*/ + +#define MX_GPIO 1 + +/* GPIO Configuration */ + +/* Pin PB7 */ +#define MX_PB7_GPIO_Speed GPIO_SPEED_FREQ_LOW +#define MX_PB7_Pin PB7 +#define MX_PB7_GPIOx GPIOB +#define MX_PB7_PinState GPIO_PIN_RESET +#define MX_PB7_GPIO_PuPd GPIO_NOPULL +#define MX_PB7_GPIO_Pin GPIO_PIN_7 +#define MX_PB7_GPIO_ModeDefaultOutputPP GPIO_MODE_OUTPUT_PP + +#endif /* __MX_DEVICE_H */ + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject new file mode 100644 index 00000000..dc78b54a --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject @@ -0,0 +1,12 @@ +[PreviousLibFiles] +LibFiles=Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rng.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f746xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\system_stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c; + +[] +SourceFiles=;; + +[PreviousGenFiles] +HeaderPath=..\Inc +HeaderFiles=stm32f7xx_it.h;stm32f7xx_hal_conf.h;main.h; +SourcePath=..\Src +SourceFiles=stm32f7xx_it.c;stm32f7xx_hal_msp.c;stm32f7xx_hal_timebase_tim.c;main.c; + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h new file mode 100644 index 00000000..280da443 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h new file mode 100644 index 00000000..6a6405d8 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h @@ -0,0 +1,484 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f7xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)15U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define ART_ACCELERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE 1524 /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32f7xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h new file mode 100644 index 00000000..8d598487 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h @@ -0,0 +1,64 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_IT_H +#define __STM32F7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void DebugMon_Handler(void); +void TIM6_DAC_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_IT_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc new file mode 100644 index 00000000..36522c17 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc @@ -0,0 +1,181 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +ETH.IPParameters=MediaInterface +ETH.MediaInterface=HAL_ETH_RMII_MODE +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.CPN=STM32F746ZGT6 +Mcu.Family=STM32F7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=ETH +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=RNG +Mcu.IP5=SYS +Mcu.IP6=USART3 +Mcu.IPNb=7 +Mcu.Name=STM32F746ZGTx +Mcu.Package=LQFP144 +Mcu.Pin0=PC1 +Mcu.Pin1=PA1 +Mcu.Pin10=PG13 +Mcu.Pin11=PB7 +Mcu.Pin12=VP_RNG_VS_RNG +Mcu.Pin13=VP_SYS_VS_tim6 +Mcu.Pin2=PA2 +Mcu.Pin3=PA7 +Mcu.Pin4=PC4 +Mcu.Pin5=PC5 +Mcu.Pin6=PB13 +Mcu.Pin7=PD8 +Mcu.Pin8=PD9 +Mcu.Pin9=PG11 +Mcu.PinsNb=14 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F746ZGTx +MxCube.Version=6.8.0 +MxDb.Version=DB.6.0.80 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ETH_IRQn=true\:0\:0\:false\:false\:false\:true\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:false\:true\:false +NVIC.TIM6_DAC_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true +NVIC.TimeBase=TIM6_DAC_IRQn +NVIC.TimeBaseIP=TIM6 +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA1.Mode=RMII +PA1.Signal=ETH_REF_CLK +PA2.Mode=RMII +PA2.Signal=ETH_MDIO +PA7.Mode=RMII +PA7.Signal=ETH_CRS_DV +PB13.Mode=RMII +PB13.Signal=ETH_TXD1 +PB7.Locked=true +PB7.Signal=GPIO_Output +PC1.Mode=RMII +PC1.Signal=ETH_MDC +PC4.Mode=RMII +PC4.Signal=ETH_RXD0 +PC5.Mode=RMII +PC5.Signal=ETH_RXD1 +PD8.Locked=true +PD8.Mode=Asynchronous +PD8.Signal=USART3_TX +PD9.Locked=true +PD9.Mode=Asynchronous +PD9.Signal=USART3_RX +PG11.Locked=true +PG11.Mode=RMII +PG11.Signal=ETH_TX_EN +PG13.Locked=true +PG13.Mode=RMII +PG13.Signal=ETH_TXD0 +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F746ZGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.17.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=2 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=true +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=STCubeGenerated.ioc +ProjectManager.ProjectName=STCubeGenerated +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_RNG_Init-RNG-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.AHBFreq_Value=216000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=54000000 +RCC.APB1TimFreq_Value=108000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=108000000 +RCC.APB2TimFreq_Value=216000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=216000000 +RCC.EthernetFreq_Value=216000000 +RCC.FCLKCortexFreq_Value=216000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=216000000 +RCC.HSE_VALUE=25000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=54000000 +RCC.I2C2Freq_Value=54000000 +RCC.I2C3Freq_Value=54000000 +RCC.I2C4Freq_Value=54000000 +RCC.I2SFreq_Value=192000000 +RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value +RCC.LCDTFToutputFreq_Value=96000000 +RCC.LPTIM1Freq_Value=54000000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=216000000 +RCC.PLLCLKFreq_Value=216000000 +RCC.PLLI2SPCLKFreq_Value=192000000 +RCC.PLLI2SQCLKFreq_Value=192000000 +RCC.PLLI2SRCLKFreq_Value=192000000 +RCC.PLLI2SRoutputFreq_Value=192000000 +RCC.PLLM=8 +RCC.PLLN=216 +RCC.PLLQ=9 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLQoutputFreq_Value=48000000 +RCC.PLLSAIPCLKFreq_Value=192000000 +RCC.PLLSAIQCLKFreq_Value=192000000 +RCC.PLLSAIRCLKFreq_Value=192000000 +RCC.PLLSAIoutputFreq_Value=192000000 +RCC.RNGFreq_Value=48000000 +RCC.SAI1Freq_Value=192000000 +RCC.SAI2Freq_Value=192000000 +RCC.SDMMCFreq_Value=216000000 +RCC.SPDIFRXFreq_Value=192000000 +RCC.SYSCLKFreq_VALUE=216000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=54000000 +RCC.UART5Freq_Value=54000000 +RCC.UART7Freq_Value=54000000 +RCC.UART8Freq_Value=54000000 +RCC.USART1Freq_Value=108000000 +RCC.USART2Freq_Value=54000000 +RCC.USART3Freq_Value=54000000 +RCC.USART6Freq_Value=108000000 +RCC.USBFreq_Value=48000000 +RCC.VCOI2SOutputFreq_Value=384000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutputFreq_Value=432000000 +RCC.VCOSAIOutputFreq_Value=384000000 +USART3.IPParameters=VirtualMode-Asynchronous +USART3.VirtualMode-Asynchronous=VM_ASYNC +VP_RNG_VS_RNG.Mode=RNG_Activate +VP_RNG_VS_RNG.Signal=RNG_VS_RNG +VP_SYS_VS_tim6.Mode=TIM6 +VP_SYS_VS_tim6.Signal=SYS_VS_tim6 +board=custom diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c new file mode 100644 index 00000000..625cd310 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c @@ -0,0 +1,352 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "string.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "cmsis_os.h" + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma location=0x2004c000 +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +#pragma location=0x2004c0a0 +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __CC_ARM ) /* MDK ARM Compiler */ + +__attribute__((at(0x2004c000))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +__attribute__((at(0x2004c0a0))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __GNUC__ ) /* GNU Compiler */ +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */ +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection"))); /* Ethernet Tx DMA Descriptors */ + +#endif + +ETH_TxPacketConfig TxConfig; + +ETH_HandleTypeDef heth; + +RNG_HandleTypeDef hrng; + +UART_HandleTypeDef huart3; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART3_UART_Init(void); +static void MX_ETH_Init(void); +static void MX_RNG_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +void mx_init(void) { + SystemClock_Config(); + MX_GPIO_Init(); + MX_USART3_UART_Init(); + MX_RNG_Init(); + MX_ETH_Init(); +} + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 216; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ETH Initialization Function + * @param None + * @retval None + */ +static void MX_ETH_Init(void) +{ + + /* USER CODE BEGIN ETH_Init 0 */ + + /* USER CODE END ETH_Init 0 */ + + static uint8_t MACAddr[6]; + + /* USER CODE BEGIN ETH_Init 1 */ + + /* USER CODE END ETH_Init 1 */ + heth.Instance = ETH; + MACAddr[0] = 0x00; + MACAddr[1] = 0x80; + MACAddr[2] = 0xE1; + MACAddr[3] = 0x00; + MACAddr[4] = 0x00; + MACAddr[5] = 0x00; + heth.Init.MACAddr = &MACAddr[0]; + heth.Init.MediaInterface = HAL_ETH_RMII_MODE; + heth.Init.TxDesc = DMATxDscrTab; + heth.Init.RxDesc = DMARxDscrTab; + heth.Init.RxBuffLen = 1524; + + /* USER CODE BEGIN MACADDRESS */ + + /* USER CODE END MACADDRESS */ + + if (HAL_ETH_Init(&heth) != HAL_OK) + { + Error_Handler(); + } + + memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig)); + TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; + TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; + TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; + /* USER CODE BEGIN ETH_Init 2 */ + + /* USER CODE END ETH_Init 2 */ + +} + +/** + * @brief RNG Initialization Function + * @param None + * @retval None + */ +static void MX_RNG_Init(void) +{ + + /* USER CODE BEGIN RNG_Init 0 */ + + /* USER CODE END RNG_Init 0 */ + + /* USER CODE BEGIN RNG_Init 1 */ + + /* USER CODE END RNG_Init 1 */ + hrng.Instance = RNG; + if (HAL_RNG_Init(&hrng) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RNG_Init 2 */ + + /* USER CODE END RNG_Init 2 */ + +} + +/** + * @brief USART3 Initialization Function + * @param None + * @retval None + */ +static void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET); + + /*Configure GPIO pin : PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM6 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM6) { + HAL_IncTick(); + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c new file mode 100644 index 00000000..cff0eb5b --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c @@ -0,0 +1,326 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ETH MSP Initialization +* This function configures the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspInit 0 */ + + /* USER CODE END ETH_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ETH_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* ETH interrupt Init */ + HAL_NVIC_SetPriority(ETH_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspInit 1 */ + + /* USER CODE END ETH_MspInit 1 */ + } + +} + +/** +* @brief ETH MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspDeInit 0 */ + + /* USER CODE END ETH_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11|GPIO_PIN_13); + + /* ETH interrupt DeInit */ + HAL_NVIC_DisableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspDeInit 1 */ + + /* USER CODE END ETH_MspDeInit 1 */ + } + +} + +/** +* @brief RNG MSP Initialization +* This function configures the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspInit 0 */ + + /* USER CODE END RNG_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_RNG_CLK_ENABLE(); + /* USER CODE BEGIN RNG_MspInit 1 */ + + /* USER CODE END RNG_MspInit 1 */ + } + +} + +/** +* @brief RNG MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspDeInit 0 */ + + /* USER CODE END RNG_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RNG_CLK_DISABLE(); + /* USER CODE BEGIN RNG_MspDeInit 1 */ + + /* USER CODE END RNG_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; + PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9); + + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_timebase_tim.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_timebase_tim.c new file mode 100644 index 00000000..b322b56f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_timebase_tim.c @@ -0,0 +1,137 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_timebase_TIM.c + * @brief HAL time base based on the hardware TIM. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" +#include "stm32f7xx_hal_tim.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_HandleTypeDef htim6; +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the TIM6 as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock, uwAPB1Prescaler = 0U; + + uint32_t uwPrescalerValue = 0U; + uint32_t pFLatency; + HAL_StatusTypeDef status; + + /* Enable TIM6 clock */ + __HAL_RCC_TIM6_CLK_ENABLE(); + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + + /* Get APB1 prescaler */ + uwAPB1Prescaler = clkconfig.APB1CLKDivider; + /* Compute TIM6 clock */ + if (uwAPB1Prescaler == RCC_HCLK_DIV1) + { + uwTimclock = HAL_RCC_GetPCLK1Freq(); + } + else + { + uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); + } + + /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + + /* Initialize TIM6 */ + htim6.Instance = TIM6; + + /* Initialize TIMx peripheral as follow: + + + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + + ClockDivision = 0 + + Counter direction = Up + */ + htim6.Init.Period = (1000000U / 1000U) - 1U; + htim6.Init.Prescaler = uwPrescalerValue; + htim6.Init.ClockDivision = 0; + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + + status = HAL_TIM_Base_Init(&htim6); + if (status == HAL_OK) + { + /* Start the TIM time Base generation in interrupt mode */ + status = HAL_TIM_Base_Start_IT(&htim6); + if (status == HAL_OK) + { + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Configure the TIM IRQ priority */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling TIM6 update interrupt. + * @param None + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable TIM6 update Interrupt */ + __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling TIM6 update interrupt. + * @param None + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Enable TIM6 Update interrupt */ + __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE); +} + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c new file mode 100644 index 00000000..31d671be --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c @@ -0,0 +1,178 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern TIM_HandleTypeDef htim6; + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M7 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + */ +void TIM6_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_TIM_IRQHandler(&htim6); + /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + + /* USER CODE END TIM6_DAC_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s new file mode 100644 index 00000000..cfb82fec --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s @@ -0,0 +1,468 @@ +;******************************************************************************* +;* File Name : startup_stm32f746xx.s +;* Author : MCD Application Team +;* Description : STM32F746xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2016 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00010000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c new file mode 100644 index 00000000..32e7fa5f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c @@ -0,0 +1,259 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS RAMDTCM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/project.script b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/project.script new file mode 100644 index 00000000..0f10b399 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Device/project.script @@ -0,0 +1,7 @@ +load STM32F746ZGTx +project name STCubeGenerated +project toolchain "MDK-ARM V5" +project path "C:\Users\scaprile\Documents\Keil\nucleo-f746zg-keil-baremetal\RTE\Device\STM32F746ZGTx\" +set tpl_path "C:\Users\scaprile\AppData\Local\Arm\Packs\Keil\STM32F7xx_DFP\2.15.1\MDK\CubeMX" +set dest_path "STM32F746ZGTx" +SetCopyLibrary "copy as reference" diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Network_Library/mongoose_custom.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Network_Library/mongoose_custom.h new file mode 100644 index 00000000..bea94279 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/Network_Library/mongoose_custom.h @@ -0,0 +1,77 @@ + +// <<< Use Configuration Wizard in Context Menu >>> + +// System Architecture +// <0=> Bare metal +// <1=> FreeRTOS +// <2=> CMSIS-RTOS v1 +// <3=> CMSIS-RTOS v2 +// Select either bare metal operation or a supported RTOS +// FreeRTOS uses direct FreeRTOS calls +// CMSIS-RTOS1 supports only Keil RTX through API v1 +// CMSIS-RTOS2 supports Keil RTX5 and FreeRTOS through API v2 + +#define MG_CMSISPACK_ARCH 2 + + +// Networking support +// Networking stack +// <0=> Built-in +// <1=> lwIP +// <2=> FreeRTOS-Plus-TCP +// <3=> MDK (RL) +// Select the networking stack to use with Mongoose Library +// The built-in stack can run on bare metal or over any RTOS +// "lwIP" requires using an RTOS and BSD socket mode +// "MDK" requires using CMSIS-RTOS1 (RTX + RL) or CMSIS-RTOS2 (MDK Plus or Pro), and BSD socket mode +#define MG_CMSISPACK_NET 0 + +// Use Mbed-TLS +// Mongoose will use Mbed-TLS calls for TLS-related functionality +#define MG_ENABLE_MBEDTLS 0 +// + + +// Enable custom mg_millis() +// Use a user-provided function to get uptime in milliseconds, otherwise Mongoose will default to using time(). Except for bare metal, Mongoose will use the time base for the configured architecture +//#define MG_ENABLE_CUSTOM_MILLIS 1 +// + + +// Enable custom mg_rand() +// Use a user-provided function to generate random numbers, otherwise Mongoose will default to using rand() +#define MG_ENABLE_CUSTOM_RANDOM 1 +// + + +// Filesystem support +// Enable packed (embedded) filesystem +#define MG_ENABLE_PACKED_FS 1 +// + + +// <<< end of configuration section >>> + +// Translate to Mongoose macros +#if MG_CMSISPACK_ARCH == 1 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_FREERTOS +#elif MG_CMSISPACK_ARCH == 2 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_CMSIS_RTOS1 +#elif MG_CMSISPACK_ARCH == 3 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_CMSIS_RTOS2 +#endif +#if MG_CMSISPACK_NET == 0 +#define MG_ENABLE_TCPIP 1 +#elif MG_CMSISPACK_NET == 1 +#define MG_ENABLE_LWIP 1 +#elif MG_CMSISPACK_NET == 2 +#define MG_ENABLE_FREERTOS_TCP 1 +#elif MG_CMSISPACK_NET == 3 +#define MG_ENABLE_RL 1 +#endif + + +// Add your customization below this comment diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/_Target_1/Pre_Include_Global.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/_Target_1/Pre_Include_Global.h new file mode 100644 index 00000000..8aabd0e0 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/_Target_1/Pre_Include_Global.h @@ -0,0 +1,17 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'device-dashboard' + * Target: 'Target 1' + */ + +#ifndef PRE_INCLUDE_GLOBAL_H +#define PRE_INCLUDE_GLOBAL_H + +/* Keil::Device:STM32Cube HAL:Common:1.3.0 */ +#define USE_HAL_DRIVER + + +#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/_Target_1/RTE_Components.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/_Target_1/RTE_Components.h new file mode 100644 index 00000000..bbaa2ec6 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/RTE/_Target_1/RTE_Components.h @@ -0,0 +1,51 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'device-dashboard' + * Target: 'Target 1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f7xx.h" + +/* ARM::CMSIS:RTOS:Keil RTX:4.82.0 */ +#define RTE_CMSIS_RTOS /* CMSIS-RTOS */ + #define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */ +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:User:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ +/* Keil::Device:STM32Cube Framework:STM32CubeMX:1.1.0 */ +#define RTE_DEVICE_FRAMEWORK_CUBE_MX +/* Keil::Device:STM32Cube HAL:Common:1.3.0 */ +#define RTE_DEVICE_HAL_COMMON +/* Keil::Device:STM32Cube HAL:Cortex:1.3.0 */ +#define RTE_DEVICE_HAL_CORTEX +/* Keil::Device:STM32Cube HAL:DMA:1.3.0 */ +#define RTE_DEVICE_HAL_DMA +/* Keil::Device:STM32Cube HAL:ETH:1.3.0 */ +#define RTE_DEVICE_HAL_ETH +/* Keil::Device:STM32Cube HAL:GPIO:1.3.0 */ +#define RTE_DEVICE_HAL_GPIO +/* Keil::Device:STM32Cube HAL:PWR:1.3.0 */ +#define RTE_DEVICE_HAL_PWR +/* Keil::Device:STM32Cube HAL:RCC:1.3.0 */ +#define RTE_DEVICE_HAL_RCC +/* Keil::Device:STM32Cube HAL:RNG:1.3.0 */ +#define RTE_DEVICE_HAL_RNG +/* Keil::Device:STM32Cube HAL:TIM:1.3.0 */ +#define RTE_DEVICE_HAL_TIM +/* Keil::Device:STM32Cube HAL:UART:1.3.0 */ +#define RTE_DEVICE_HAL_UART +/* Keil::Device:Startup:1.2.5 */ +#define RTE_DEVICE_STARTUP_STM32F7XX /* Device Startup for STM32F7 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/device-dashboard.uvguix b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/device-dashboard.uvguix new file mode 100644 index 00000000..f3c4cf70 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/device-dashboard.uvguix @@ -0,0 +1,3664 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 1920 + 1080 + + + + + + 1 + 0 + + 100 + 3 + + RTE\Network_Library\mongoose_custom.h + 0 + 1 + 1 + 1 + + 0 + + + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + 0 + 76 + 101 + 1 + + 0 + + + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + 5 + 83 + 84 + 1 + + 0 + + + .\main.c + 0 + 1 + 12 + 1 + + 0 + + + RTE\Device\STM32F746ZGTx\startup_stm32f746xx.s + 0 + 180 + 188 + 1 + + 0 + + + RTE\CMSIS\RTX_Conf_CM.c + 0 + 264 + 272 + 1 + + 0 + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/device-dashboard.uvoptx b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/device-dashboard.uvoptx new file mode 100644 index 00000000..5621b64d --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/device-dashboard.uvoptx @@ -0,0 +1,363 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 16000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=44,510,420,746,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + ST-LINKIII-KEIL_SWO + -U-O206 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(5BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FF1STM32F7xTCM_1024.FLM -FS1200000 -FL1100000 -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + + + + + + 0 + 1 + buf + + + + + 1 + 0 + 0x20010E40 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 1 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + .\hal.h + hal.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + .\net.c + net.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + .\packed_fs.c + packed_fs.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + .\syscalls.c + syscalls.c + 0 + 0 + + + + + :STM32CubeMX:Common Sources + 1 + 0 + 0 + 0 + + 2 + 6 + 1 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + main.c + 0 + 0 + + + 2 + 7 + 5 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Inc\stm32f7xx_it.h + stm32f7xx_it.h + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + stm32f7xx_it.c + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + + + ::Compiler + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + + ::Network Library + 1 + 0 + 0 + 1 + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/device-dashboard.uvprojx b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/device-dashboard.uvprojx new file mode 100644 index 00000000..a4f277a1 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/device-dashboard.uvprojx @@ -0,0 +1,599 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + STM32F746ZGTx + STMicroelectronics + Keil.STM32F7xx_DFP.2.15.1 + https://www.keil.com/pack/ + IRAM(0x20010000,0x40000) IRAM2(0x20000000,0x10000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + 0 + $$Device:STM32F746ZGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h + + + + + + + + + + $$Device:STM32F746ZGTx$CMSIS\SVD\STM32F746.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + device-dashboard + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x200000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 6 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + + -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion -Wno-unused-parameter -Wno-macro-redefined -Wconversion -Wno-sign-conversion -fno-common -fdata-sections + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20010000 + + + + + + + + + + + + + Source Group 1 + + + hal.h + 5 + .\hal.h + + + main.c + 1 + .\main.c + + + net.c + 1 + .\net.c + + + packed_fs.c + 1 + .\packed_fs.c + + + syscalls.c + 1 + .\syscalls.c + + + + + :STM32CubeMX:Common Sources + + + main.c + 1 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + + + stm32f7xx_it.h + 5 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Inc\stm32f7xx_it.h + + + stm32f7xx_it.c + 1 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + + + + + ::CMSIS + + + ::Compiler + + + ::Device + + + ::Network Library + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Conf_CM.c + + + + + + + + RTE\Device\STM32F746ZGTx\startup_stm32f746xx.s + + + + + + + + RTE\Device\STM32F746ZGTx\system_stm32f7xx.c + + + + + + + + RTE\Network_Library\mongoose_custom.h + + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/hal.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/hal.h new file mode 100644 index 00000000..a0ec0b30 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/hal.h @@ -0,0 +1,21 @@ +// Copyright (c) 2022-23 Cesanta Software Limited +// All rights reserved +// https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf + +#pragma once + +#include + +#ifndef UART_DEBUG +#define UART_DEBUG USART3 +#endif + + +#define UUID ((uint8_t *) UID_BASE) // Unique 96-bit chip ID. TRM 41.1 + +// Helper macro for MAC generation +#define GENERATE_LOCALLY_ADMINISTERED_MAC() \ + { \ + 2, UUID[0] ^ UUID[1], UUID[2] ^ UUID[3], UUID[4] ^ UUID[5], \ + UUID[6] ^ UUID[7] ^ UUID[8], UUID[9] ^ UUID[10] ^ UUID[11] \ + } diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/main.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/main.c new file mode 100644 index 00000000..63105325 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/main.c @@ -0,0 +1,80 @@ +// Copyright (c) 2023 Cesanta Software Limited +// All rights reserved + +#include "hal.h" +#include "mongoose.h" +#include "main.h" +#include "cmsis_os.h" + +#define BLINK_PERIOD_MS 1000 // LED blinking period in millis + + +void mg_random(void *buf, size_t len) { // Use on-board RNG + extern RNG_HandleTypeDef hrng; + for (size_t n = 0; n < len; n += sizeof(uint32_t)) { + uint32_t r; + HAL_RNG_GenerateRandomNumber(&hrng, &r); + memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r)); + } +} + +static void timer_fn(void *arg) { + struct mg_tcpip_if *ifp = arg; // And show + const char *names[] = {"down", "up", "ready"}; // network stats + MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u", + names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent, + ifp->ndrop, ifp->nerr)); +} + +static void server(const void *args) { + struct mg_mgr mgr; // Initialise Mongoose event manager + mg_mgr_init(&mgr); // and attach it to the interface + mg_log_set(MG_LL_DEBUG); // Set log level + + // Initialise Mongoose network stack + // Specify MAC address, and IP/mask/GW in network byte order for static + // IP configuration. If IP/mask/GW are unset, DHCP is going to be used + struct mg_tcpip_driver_stm32_data driver_data = {.mdc_cr = 4}; + struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(), + .driver = &mg_tcpip_driver_stm32, + .driver_data = &driver_data}; + mg_tcpip_init(&mgr, &mif); + mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif); + + MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac)); + while (mif.state != MG_TCPIP_STATE_READY) { + mg_mgr_poll(&mgr, 0); + } + + MG_INFO(("Initialising application...")); + extern void device_dashboard_fn(struct mg_connection *, int, void *, void *); + mg_http_listen(&mgr, "http://0.0.0.0", device_dashboard_fn, NULL); + + MG_INFO(("Starting event loop")); + for (;;) mg_mgr_poll(&mgr, 1); // Infinite event loop + (void) args; +} + +static void blinker(const void *args) { + for (;;) { + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_7); // Blink On-board blue LED + osDelay(BLINK_PERIOD_MS); // CMSIS-RTOS v1 uses milliseconds + } + (void) args; +} + +extern void mx_init(void); +osThreadDef(server, osPriorityNormal, 1, 8192); // Create the server thread with a stack size of 8KB +osThreadDef(blinker, osPriorityNormal, 1, 0); // Create the blinker thread with default stack size + +int main(void) { // this is not actually baremetal main() but the "main" thread + osKernelInitialize(); // Stop kernel + mx_init(); // Setup clock and all peripherals configured in CubeMX + // Initialise random number generator + // Initialise ethernet pins + osThreadCreate(osThread(blinker), NULL); // Create the blinker thread + osThreadCreate(osThread(server), NULL); // Create the server thread + osKernelStart(); // Start kernel again and exit main thread + return 0; +} + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/syscalls.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/syscalls.c new file mode 100644 index 00000000..79113968 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx/syscalls.c @@ -0,0 +1,10 @@ +#include +#include + +#include "main.h" + +int stdout_putchar (int ch) { + extern UART_HandleTypeDef huart3; + HAL_UART_Transmit(&huart3, (const uint8_t *)&ch, 1, 100); + return ch; +} diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/EventRecorderStub.scvd b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/EventRecorderStub.scvd new file mode 100644 index 00000000..0fb3ee58 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/README.md b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/README.md new file mode 100644 index 00000000..33651e06 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/README.md @@ -0,0 +1,7 @@ +# RTX5 + lwIP Web device dashboard on NUCLEO-F746ZG, built on Keil MDK + +- Open this example with Keil uVision +- Build it +- Run/Debug it + +Mongoose configuration is in mongoose_custom.h, inside Network_Library diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/RTE/CMSIS/RTX_Config.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/RTE/CMSIS/RTX_Config.c new file mode 100644 index 00000000..938a5658 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/RTE/CMSIS/RTX_Config.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/RTE/CMSIS/RTX_Config.h new file mode 100644 index 00000000..68090cf5 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,580 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.2 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 65536 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc new file mode 100644 index 00000000..75584461 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-lwip/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc @@ -0,0 +1,64 @@ + + + + + Keil + FrameworkCubeMX + STM32CubeMX generated pack description + project-path + + + - Generated: 23/05/2023 17:10:15 + + + + + STM32CubeMX Environment + + $SMDK/CubeMX/STM32CubeMXLauncher + $PRTE/Device/STM32F746ZGTx + + + + + + + + + + STM32Cube Framework + + + + Condition to include CMSIS core and Device Startup components + + + + + + + + + + + + + + + Configuration via STM32CubeMX + + #define RTE_DEVICE_FRAMEWORK_CUBE_MX + + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/MX_Device.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/MX_Device.h new file mode 100644 index 00000000..8fa6c2fd --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/MX_Device.h @@ -0,0 +1,212 @@ +/****************************************************************************** + * File Name : MX_Device.h + * Date : 23/05/2023 17:14:48 + * Description : STM32Cube MX parameter definitions + * Note : This file is generated by STM32CubeMX (DO NOT EDIT!) + ******************************************************************************/ + +#ifndef __MX_DEVICE_H +#define __MX_DEVICE_H + +/*---------------------------- Clock Configuration ---------------------------*/ + +#define MX_LSI_VALUE 32000 +#define MX_LSE_VALUE 32768 +#define MX_HSI_VALUE 16000000 +#define MX_HSE_VALUE 25000000 +#define MX_EXTERNAL_CLOCK_VALUE 12288000 +#define MX_SYSCLKFreq_VALUE 216000000 +#define MX_HCLKFreq_Value 216000000 +#define MX_FCLKCortexFreq_Value 216000000 +#define MX_CortexFreq_Value 216000000 +#define MX_AHBFreq_Value 216000000 +#define MX_APB1Freq_Value 54000000 +#define MX_APB2Freq_Value 108000000 +#define MX_APB1TimFreq_Value 108000000 +#define MX_APB2TimFreq_Value 216000000 +#define MX_EthernetFreq_Value 216000000 +#define MX_CECFreq_Value 32786 +#define MX_LCDTFToutputFreq_Value 96000000 +#define MX_I2C1Freq_Value 54000000 +#define MX_I2C2Freq_Value 54000000 +#define MX_I2C3Freq_Value 54000000 +#define MX_I2C4Freq_Value 54000000 +#define MX_I2SFreq_Value 192000000 +#define MX_SAI1Freq_Value 192000000 +#define MX_SAI2Freq_Value 192000000 +#define MX_SDMMCFreq_Value 216000000 +#define MX_RTCFreq_Value 32000 +#define MX_USART1Freq_Value 108000000 +#define MX_USART2Freq_Value 54000000 +#define MX_USART3Freq_Value 54000000 +#define MX_UART4Freq_Value 54000000 +#define MX_UART5Freq_Value 54000000 +#define MX_UART8Freq_Value 54000000 +#define MX_UART7Freq_Value 54000000 +#define MX_USART6Freq_Value 108000000 +#define MX_USBFreq_Value 48000000 +#define MX_WatchDogFreq_Value 32000 +#define MX_LPTIM1Freq_Value 54000000 +#define MX_SPDIFRXFreq_Value 192000000 +#define MX_MCO1PinFreq_Value 16000000 +#define MX_MCO2PinFreq_Value 216000000 + +/*-------------------------------- CORTEX_M7 --------------------------------*/ + +#define MX_CORTEX_M7 1 + +/* GPIO Configuration */ + +/*-------------------------------- ETH --------------------------------*/ + +#define MX_ETH 1 + +/* GPIO Configuration */ + +/* Pin PA1 */ +#define MX_ETH_REF_CLK_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_REF_CLK_Pin PA1 +#define MX_ETH_REF_CLK_GPIOx GPIOA +#define MX_ETH_REF_CLK_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_REF_CLK_GPIO_Pin GPIO_PIN_1 +#define MX_ETH_REF_CLK_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_REF_CLK_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PA7 */ +#define MX_ETH_CRS_DV_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_CRS_DV_Pin PA7 +#define MX_ETH_CRS_DV_GPIOx GPIOA +#define MX_ETH_CRS_DV_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_CRS_DV_GPIO_Pin GPIO_PIN_7 +#define MX_ETH_CRS_DV_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_CRS_DV_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC4 */ +#define MX_ETH_RXD0_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_RXD0_Pin PC4 +#define MX_ETH_RXD0_GPIOx GPIOC +#define MX_ETH_RXD0_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_RXD0_GPIO_Pin GPIO_PIN_4 +#define MX_ETH_RXD0_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_RXD0_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC5 */ +#define MX_ETH_RXD1_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_RXD1_Pin PC5 +#define MX_ETH_RXD1_GPIOx GPIOC +#define MX_ETH_RXD1_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_RXD1_GPIO_Pin GPIO_PIN_5 +#define MX_ETH_RXD1_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_RXD1_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PG11 */ +#define MX_ETH_TX_EN_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TX_EN_Pin PG11 +#define MX_ETH_TX_EN_GPIOx GPIOG +#define MX_ETH_TX_EN_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TX_EN_GPIO_Pin GPIO_PIN_11 +#define MX_ETH_TX_EN_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TX_EN_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PA2 */ +#define MX_ETH_MDIO_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_MDIO_Pin PA2 +#define MX_ETH_MDIO_GPIOx GPIOA +#define MX_ETH_MDIO_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_MDIO_GPIO_Pin GPIO_PIN_2 +#define MX_ETH_MDIO_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_MDIO_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PB13 */ +#define MX_ETH_TXD1_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TXD1_Pin PB13 +#define MX_ETH_TXD1_GPIOx GPIOB +#define MX_ETH_TXD1_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TXD1_GPIO_Pin GPIO_PIN_13 +#define MX_ETH_TXD1_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TXD1_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PG13 */ +#define MX_ETH_TXD0_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_TXD0_Pin PG13 +#define MX_ETH_TXD0_GPIOx GPIOG +#define MX_ETH_TXD0_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_TXD0_GPIO_Pin GPIO_PIN_13 +#define MX_ETH_TXD0_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_TXD0_GPIO_Mode GPIO_MODE_AF_PP + +/* Pin PC1 */ +#define MX_ETH_MDC_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_ETH_MDC_Pin PC1 +#define MX_ETH_MDC_GPIOx GPIOC +#define MX_ETH_MDC_GPIO_PuPd GPIO_NOPULL +#define MX_ETH_MDC_GPIO_Pin GPIO_PIN_1 +#define MX_ETH_MDC_GPIO_AF GPIO_AF11_ETH +#define MX_ETH_MDC_GPIO_Mode GPIO_MODE_AF_PP + +/* NVIC Configuration */ + +/* NVIC ETH_IRQn */ +#define MX_ETH_IRQn_interruptPremptionPriority 0 +#define MX_ETH_IRQn_PriorityGroup NVIC_PRIORITYGROUP_4 +#define MX_ETH_IRQn_Subriority 0 + +/*-------------------------------- RNG --------------------------------*/ + +#define MX_RNG 1 + +/* GPIO Configuration */ + +/*-------------------------------- SYS --------------------------------*/ + +#define MX_SYS 1 + +/* GPIO Configuration */ + +/*-------------------------------- USART3 --------------------------------*/ + +#define MX_USART3 1 + +#define MX_USART3_VM VM_ASYNC + +/* GPIO Configuration */ + +/* Pin PD8 */ +#define MX_USART3_TX_GPIO_ModeDefaultPP GPIO_MODE_AF_PP +#define MX_USART3_TX_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_USART3_TX_Pin PD8 +#define MX_USART3_TX_GPIOx GPIOD +#define MX_USART3_TX_GPIO_PuPd GPIO_NOPULL +#define MX_USART3_TX_GPIO_Pin GPIO_PIN_8 +#define MX_USART3_TX_GPIO_AF GPIO_AF7_USART3 + +/* Pin PD9 */ +#define MX_USART3_RX_GPIO_ModeDefaultPP GPIO_MODE_AF_PP +#define MX_USART3_RX_GPIO_Speed GPIO_SPEED_FREQ_VERY_HIGH +#define MX_USART3_RX_Pin PD9 +#define MX_USART3_RX_GPIOx GPIOD +#define MX_USART3_RX_GPIO_PuPd GPIO_NOPULL +#define MX_USART3_RX_GPIO_Pin GPIO_PIN_9 +#define MX_USART3_RX_GPIO_AF GPIO_AF7_USART3 + +/*-------------------------------- NVIC --------------------------------*/ + +#define MX_NVIC 1 + +/*-------------------------------- GPIO --------------------------------*/ + +#define MX_GPIO 1 + +/* GPIO Configuration */ + +/* Pin PB7 */ +#define MX_PB7_GPIO_Speed GPIO_SPEED_FREQ_LOW +#define MX_PB7_Pin PB7 +#define MX_PB7_GPIOx GPIOB +#define MX_PB7_PinState GPIO_PIN_RESET +#define MX_PB7_GPIO_PuPd GPIO_NOPULL +#define MX_PB7_GPIO_Pin GPIO_PIN_7 +#define MX_PB7_GPIO_ModeDefaultOutputPP GPIO_MODE_OUTPUT_PP + +#endif /* __MX_DEVICE_H */ + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject new file mode 100644 index 00000000..dc78b54a --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/.mxproject @@ -0,0 +1,12 @@ +[PreviousLibFiles] +LibFiles=Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_cortex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rcc_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_flash_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_gpio.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_dma_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_pwr_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_i2c_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_exti.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_eth.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_rng.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_tim_ex.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart.c;Drivers\STM32F7xx_HAL_Driver\Src\stm32f7xx_hal_uart_ex.c;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_cortex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rcc_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_bus.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rcc.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_system.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_utils.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_flash_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_gpio_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_gpio.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_dma_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dma.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_dmamux.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_pwr_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_pwr.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_def.h;Drivers\STM32F7xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_i2c_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_exti.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_eth.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_rng.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_tim_ex.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_ll_usart.h;Drivers\STM32F7xx_HAL_Driver\Inc\stm32f7xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f746xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Include\system_stm32f7xx.h;Drivers\CMSIS\Device\ST\STM32F7xx\Source\Templates\system_stm32f7xx.c; + +[] +SourceFiles=;; + +[PreviousGenFiles] +HeaderPath=..\Inc +HeaderFiles=stm32f7xx_it.h;stm32f7xx_hal_conf.h;main.h; +SourcePath=..\Src +SourceFiles=stm32f7xx_it.c;stm32f7xx_hal_msp.c;stm32f7xx_hal_timebase_tim.c;main.c; + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h new file mode 100644 index 00000000..280da443 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/main.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.h + * @brief : Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void Error_Handler(void); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h new file mode 100644 index 00000000..6a6405d8 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_hal_conf.h @@ -0,0 +1,484 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f7xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED + + /* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CAN_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_DAC_MODULE_ENABLED */ +/* #define HAL_DCMI_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +#define HAL_ETH_MODULE_ENABLED +/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_QSPI_MODULE_ENABLED */ +#define HAL_RNG_MODULE_ENABLED +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_DFSDM_MODULE_ENABLED */ +/* #define HAL_DSI_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_MDIOS_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_EXTI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300U /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)15U) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define ART_ACCELERATOR_ENABLE 0U /* To enable instruction cache and prefetch */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE 1524 /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848_PHY_ADDRESS Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ + +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32f7xx_hal_eth_legacy.h" +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h new file mode 100644 index 00000000..8d598487 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Inc/stm32f7xx_it.h @@ -0,0 +1,64 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_IT_H +#define __STM32F7xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void DebugMon_Handler(void); +void TIM6_DAC_IRQHandler(void); +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_IT_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc new file mode 100644 index 00000000..36522c17 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/STCubeGenerated.ioc @@ -0,0 +1,181 @@ +#MicroXplorer Configuration settings - do not modify +CAD.formats= +CAD.pinconfig= +CAD.provider= +ETH.IPParameters=MediaInterface +ETH.MediaInterface=HAL_ETH_RMII_MODE +File.Version=6 +GPIO.groupedBy= +KeepUserPlacement=false +Mcu.CPN=STM32F746ZGT6 +Mcu.Family=STM32F7 +Mcu.IP0=CORTEX_M7 +Mcu.IP1=ETH +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=RNG +Mcu.IP5=SYS +Mcu.IP6=USART3 +Mcu.IPNb=7 +Mcu.Name=STM32F746ZGTx +Mcu.Package=LQFP144 +Mcu.Pin0=PC1 +Mcu.Pin1=PA1 +Mcu.Pin10=PG13 +Mcu.Pin11=PB7 +Mcu.Pin12=VP_RNG_VS_RNG +Mcu.Pin13=VP_SYS_VS_tim6 +Mcu.Pin2=PA2 +Mcu.Pin3=PA7 +Mcu.Pin4=PC4 +Mcu.Pin5=PC5 +Mcu.Pin6=PB13 +Mcu.Pin7=PD8 +Mcu.Pin8=PD9 +Mcu.Pin9=PG11 +Mcu.PinsNb=14 +Mcu.ThirdPartyNb=0 +Mcu.UserConstants= +Mcu.UserName=STM32F746ZGTx +MxCube.Version=6.8.0 +MxDb.Version=DB.6.0.80 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.ETH_IRQn=true\:0\:0\:false\:false\:false\:true\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false +NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:false\:true\:false +NVIC.TIM6_DAC_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true +NVIC.TimeBase=TIM6_DAC_IRQn +NVIC.TimeBaseIP=TIM6 +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +PA1.Mode=RMII +PA1.Signal=ETH_REF_CLK +PA2.Mode=RMII +PA2.Signal=ETH_MDIO +PA7.Mode=RMII +PA7.Signal=ETH_CRS_DV +PB13.Mode=RMII +PB13.Signal=ETH_TXD1 +PB7.Locked=true +PB7.Signal=GPIO_Output +PC1.Mode=RMII +PC1.Signal=ETH_MDC +PC4.Mode=RMII +PC4.Signal=ETH_RXD0 +PC5.Mode=RMII +PC5.Signal=ETH_RXD1 +PD8.Locked=true +PD8.Mode=Asynchronous +PD8.Signal=USART3_TX +PD9.Locked=true +PD9.Mode=Asynchronous +PD9.Signal=USART3_RX +PG11.Locked=true +PG11.Mode=RMII +PG11.Signal=ETH_TX_EN +PG13.Locked=true +PG13.Mode=RMII +PG13.Signal=ETH_TXD0 +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=false +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F746ZGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.17.0 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=2 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=true +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=STCubeGenerated.ioc +ProjectManager.ProjectName=STCubeGenerated +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=MDK-ARM V5 +ProjectManager.ToolChainLocation= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART3_UART_Init-USART3-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_RNG_Init-RNG-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.AHBFreq_Value=216000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=54000000 +RCC.APB1TimFreq_Value=108000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=108000000 +RCC.APB2TimFreq_Value=216000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=216000000 +RCC.EthernetFreq_Value=216000000 +RCC.FCLKCortexFreq_Value=216000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=216000000 +RCC.HSE_VALUE=25000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=54000000 +RCC.I2C2Freq_Value=54000000 +RCC.I2C3Freq_Value=54000000 +RCC.I2C4Freq_Value=54000000 +RCC.I2SFreq_Value=192000000 +RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value +RCC.LCDTFToutputFreq_Value=96000000 +RCC.LPTIM1Freq_Value=54000000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=216000000 +RCC.PLLCLKFreq_Value=216000000 +RCC.PLLI2SPCLKFreq_Value=192000000 +RCC.PLLI2SQCLKFreq_Value=192000000 +RCC.PLLI2SRCLKFreq_Value=192000000 +RCC.PLLI2SRoutputFreq_Value=192000000 +RCC.PLLM=8 +RCC.PLLN=216 +RCC.PLLQ=9 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLQoutputFreq_Value=48000000 +RCC.PLLSAIPCLKFreq_Value=192000000 +RCC.PLLSAIQCLKFreq_Value=192000000 +RCC.PLLSAIRCLKFreq_Value=192000000 +RCC.PLLSAIoutputFreq_Value=192000000 +RCC.RNGFreq_Value=48000000 +RCC.SAI1Freq_Value=192000000 +RCC.SAI2Freq_Value=192000000 +RCC.SDMMCFreq_Value=216000000 +RCC.SPDIFRXFreq_Value=192000000 +RCC.SYSCLKFreq_VALUE=216000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=54000000 +RCC.UART5Freq_Value=54000000 +RCC.UART7Freq_Value=54000000 +RCC.UART8Freq_Value=54000000 +RCC.USART1Freq_Value=108000000 +RCC.USART2Freq_Value=54000000 +RCC.USART3Freq_Value=54000000 +RCC.USART6Freq_Value=108000000 +RCC.USBFreq_Value=48000000 +RCC.VCOI2SOutputFreq_Value=384000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutputFreq_Value=432000000 +RCC.VCOSAIOutputFreq_Value=384000000 +USART3.IPParameters=VirtualMode-Asynchronous +USART3.VirtualMode-Asynchronous=VM_ASYNC +VP_RNG_VS_RNG.Mode=RNG_Activate +VP_RNG_VS_RNG.Signal=RNG_VS_RNG +VP_SYS_VS_tim6.Mode=TIM6 +VP_SYS_VS_tim6.Signal=SYS_VS_tim6 +board=custom diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c new file mode 100644 index 00000000..6004c6bb --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/main.c @@ -0,0 +1,352 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "string.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "cmsis_os2.h" + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma location=0x2004c000 +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +#pragma location=0x2004c0a0 +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __CC_ARM ) /* MDK ARM Compiler */ + +__attribute__((at(0x2004c000))) ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */ +__attribute__((at(0x2004c0a0))) ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */ + +#elif defined ( __GNUC__ ) /* GNU Compiler */ +ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */ +ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection"))); /* Ethernet Tx DMA Descriptors */ + +#endif + +ETH_TxPacketConfig TxConfig; + +ETH_HandleTypeDef heth; + +RNG_HandleTypeDef hrng; + +UART_HandleTypeDef huart3; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART3_UART_Init(void); +static void MX_ETH_Init(void); +static void MX_RNG_Init(void); +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +void mx_init(void) { + SystemClock_Config(); + MX_GPIO_Init(); + MX_USART3_UART_Init(); + MX_RNG_Init(); + MX_ETH_Init(); +} + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 216; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief ETH Initialization Function + * @param None + * @retval None + */ +static void MX_ETH_Init(void) +{ + + /* USER CODE BEGIN ETH_Init 0 */ + + /* USER CODE END ETH_Init 0 */ + + static uint8_t MACAddr[6]; + + /* USER CODE BEGIN ETH_Init 1 */ + + /* USER CODE END ETH_Init 1 */ + heth.Instance = ETH; + MACAddr[0] = 0x00; + MACAddr[1] = 0x80; + MACAddr[2] = 0xE1; + MACAddr[3] = 0x00; + MACAddr[4] = 0x00; + MACAddr[5] = 0x00; + heth.Init.MACAddr = &MACAddr[0]; + heth.Init.MediaInterface = HAL_ETH_RMII_MODE; + heth.Init.TxDesc = DMATxDscrTab; + heth.Init.RxDesc = DMARxDscrTab; + heth.Init.RxBuffLen = 1524; + + /* USER CODE BEGIN MACADDRESS */ + + /* USER CODE END MACADDRESS */ + + if (HAL_ETH_Init(&heth) != HAL_OK) + { + Error_Handler(); + } + + memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig)); + TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD; + TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC; + TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT; + /* USER CODE BEGIN ETH_Init 2 */ + + /* USER CODE END ETH_Init 2 */ + +} + +/** + * @brief RNG Initialization Function + * @param None + * @retval None + */ +static void MX_RNG_Init(void) +{ + + /* USER CODE BEGIN RNG_Init 0 */ + + /* USER CODE END RNG_Init 0 */ + + /* USER CODE BEGIN RNG_Init 1 */ + + /* USER CODE END RNG_Init 1 */ + hrng.Instance = RNG; + if (HAL_RNG_Init(&hrng) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN RNG_Init 2 */ + + /* USER CODE END RNG_Init 2 */ + +} + +/** + * @brief USART3 Initialization Function + * @param None + * @retval None + */ +static void MX_USART3_UART_Init(void) +{ + + /* USER CODE BEGIN USART3_Init 0 */ + + /* USER CODE END USART3_Init 0 */ + + /* USER CODE BEGIN USART3_Init 1 */ + + /* USER CODE END USART3_Init 1 */ + huart3.Instance = USART3; + huart3.Init.BaudRate = 115200; + huart3.Init.WordLength = UART_WORDLENGTH_8B; + huart3.Init.StopBits = UART_STOPBITS_1; + huart3.Init.Parity = UART_PARITY_NONE; + huart3.Init.Mode = UART_MODE_TX_RX; + huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart3.Init.OverSampling = UART_OVERSAMPLING_16; + huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart3) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART3_Init 2 */ + + /* USER CODE END USART3_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, GPIO_PIN_7, GPIO_PIN_RESET); + + /*Configure GPIO pin : PB7 */ + GPIO_InitStruct.Pin = GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM6 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM6) { + HAL_IncTick(); + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c new file mode 100644 index 00000000..cff0eb5b --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_msp.c @@ -0,0 +1,326 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_msp.c + * @brief This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN Define */ + +/* USER CODE END Define */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN Macro */ + +/* USER CODE END Macro */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* External functions --------------------------------------------------------*/ +/* USER CODE BEGIN ExternalFunctions */ + +/* USER CODE END ExternalFunctions */ + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +/** +* @brief ETH MSP Initialization +* This function configures the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspInit 0 */ + + /* USER CODE END ETH_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ETH_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_13; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* ETH interrupt Init */ + HAL_NVIC_SetPriority(ETH_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspInit 1 */ + + /* USER CODE END ETH_MspInit 1 */ + } + +} + +/** +* @brief ETH MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param heth: ETH handle pointer +* @retval None +*/ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if(heth->Instance==ETH) + { + /* USER CODE BEGIN ETH_MspDeInit 0 */ + + /* USER CODE END ETH_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + + /**ETH GPIO Configuration + PC1 ------> ETH_MDC + PA1 ------> ETH_REF_CLK + PA2 ------> ETH_MDIO + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + PB13 ------> ETH_TXD1 + PG11 ------> ETH_TX_EN + PG13 ------> ETH_TXD0 + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5); + + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7); + + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13); + + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11|GPIO_PIN_13); + + /* ETH interrupt DeInit */ + HAL_NVIC_DisableIRQ(ETH_IRQn); + /* USER CODE BEGIN ETH_MspDeInit 1 */ + + /* USER CODE END ETH_MspDeInit 1 */ + } + +} + +/** +* @brief RNG MSP Initialization +* This function configures the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) +{ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspInit 0 */ + + /* USER CODE END RNG_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_RNG_CLK_ENABLE(); + /* USER CODE BEGIN RNG_MspInit 1 */ + + /* USER CODE END RNG_MspInit 1 */ + } + +} + +/** +* @brief RNG MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hrng: RNG handle pointer +* @retval None +*/ +void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) +{ + if(hrng->Instance==RNG) + { + /* USER CODE BEGIN RNG_MspDeInit 0 */ + + /* USER CODE END RNG_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_RNG_CLK_DISABLE(); + /* USER CODE BEGIN RNG_MspDeInit 1 */ + + /* USER CODE END RNG_MspDeInit 1 */ + } + +} + +/** +* @brief UART MSP Initialization +* This function configures the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspInit 0 */ + + /* USER CODE END USART3_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3; + PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* Peripheral clock enable */ + __HAL_RCC_USART3_CLK_ENABLE(); + + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF7_USART3; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* USER CODE BEGIN USART3_MspInit 1 */ + + /* USER CODE END USART3_MspInit 1 */ + } + +} + +/** +* @brief UART MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param huart: UART handle pointer +* @retval None +*/ +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + if(huart->Instance==USART3) + { + /* USER CODE BEGIN USART3_MspDeInit 0 */ + + /* USER CODE END USART3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART3_CLK_DISABLE(); + + /**USART3 GPIO Configuration + PD8 ------> USART3_TX + PD9 ------> USART3_RX + */ + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9); + + /* USER CODE BEGIN USART3_MspDeInit 1 */ + + /* USER CODE END USART3_MspDeInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_timebase_tim.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_timebase_tim.c new file mode 100644 index 00000000..b322b56f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_hal_timebase_tim.c @@ -0,0 +1,137 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_timebase_TIM.c + * @brief HAL time base based on the hardware TIM. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" +#include "stm32f7xx_hal_tim.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +TIM_HandleTypeDef htim6; +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the TIM6 as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock, uwAPB1Prescaler = 0U; + + uint32_t uwPrescalerValue = 0U; + uint32_t pFLatency; + HAL_StatusTypeDef status; + + /* Enable TIM6 clock */ + __HAL_RCC_TIM6_CLK_ENABLE(); + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + + /* Get APB1 prescaler */ + uwAPB1Prescaler = clkconfig.APB1CLKDivider; + /* Compute TIM6 clock */ + if (uwAPB1Prescaler == RCC_HCLK_DIV1) + { + uwTimclock = HAL_RCC_GetPCLK1Freq(); + } + else + { + uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); + } + + /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ + uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); + + /* Initialize TIM6 */ + htim6.Instance = TIM6; + + /* Initialize TIMx peripheral as follow: + + + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + + ClockDivision = 0 + + Counter direction = Up + */ + htim6.Init.Period = (1000000U / 1000U) - 1U; + htim6.Init.Prescaler = uwPrescalerValue; + htim6.Init.ClockDivision = 0; + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + + status = HAL_TIM_Base_Init(&htim6); + if (status == HAL_OK) + { + /* Start the TIM time Base generation in interrupt mode */ + status = HAL_TIM_Base_Start_IT(&htim6); + if (status == HAL_OK) + { + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Configure the TIM IRQ priority */ + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + status = HAL_ERROR; + } + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling TIM6 update interrupt. + * @param None + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable TIM6 update Interrupt */ + __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling TIM6 update interrupt. + * @param None + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Enable TIM6 Update interrupt */ + __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE); +} + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c new file mode 100644 index 00000000..31d671be --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/STCubeGenerated/Src/stm32f7xx_it.c @@ -0,0 +1,178 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32f7xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "stm32f7xx_it.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN TD */ + +/* USER CODE END TD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ +extern TIM_HandleTypeDef htim6; + +/* USER CODE BEGIN EV */ + +/* USER CODE END EV */ + +/******************************************************************************/ +/* Cortex-M7 Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + { + } + /* USER CODE END NonMaskableInt_IRQn 1 */ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + /* USER CODE END W1_HardFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + /* USER CODE END W1_MemoryManagement_IRQn 0 */ + } +} + +/** + * @brief This function handles Pre-fetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + /* USER CODE END W1_BusFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + { + /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + /* USER CODE END W1_UsageFault_IRQn 0 */ + } +} + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F7xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f7xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + */ +void TIM6_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_TIM_IRQHandler(&htim6); + /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + + /* USER CODE END TIM6_DAC_IRQn 1 */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s new file mode 100644 index 00000000..e44d7b3f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/startup_stm32f746xx.s @@ -0,0 +1,468 @@ +;******************************************************************************* +;* File Name : startup_stm32f746xx.s +;* Author : MCD Application Team +;* Description : STM32F746xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;* Copyright (c) 2016 STMicroelectronics. +;* All rights reserved. +;* +;* This software is licensed under terms that can be found in the LICENSE file +;* in the root directory of this software component. +;* If no LICENSE file comes with this software, it is provided AS-IS. +; +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000800 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00010000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c new file mode 100644 index 00000000..32e7fa5f --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/STM32F746ZGTx/system_stm32f7xx.c @@ -0,0 +1,259 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS RAMDTCM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/project.script b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/project.script new file mode 100644 index 00000000..0f10b399 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Device/project.script @@ -0,0 +1,7 @@ +load STM32F746ZGTx +project name STCubeGenerated +project toolchain "MDK-ARM V5" +project path "C:\Users\scaprile\Documents\Keil\nucleo-f746zg-keil-baremetal\RTE\Device\STM32F746ZGTx\" +set tpl_path "C:\Users\scaprile\AppData\Local\Arm\Packs\Keil\STM32F7xx_DFP\2.15.1\MDK\CubeMX" +set dest_path "STM32F746ZGTx" +SetCopyLibrary "copy as reference" diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config.c new file mode 100644 index 00000000..9b50813a --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config.c @@ -0,0 +1,173 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config.c + * Purpose: Network Configuration + * Rev.: V7.1.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Network System Settings +// Global Network System definitions +// Local Host Name +// This is the name under which embedded host can be +// accessed on a local area network. +// Default: "my_host" +#define NET_HOST_NAME "my_host" + +// Memory Pool Size <1536-262144:4> +// This is the size of a memory pool in bytes. Buffers for +// network packets are allocated from this memory pool. +// Default: 12000 bytes +#define NET_MEM_POOL_SIZE 12000 + +// Start System Services +// If enabled, the system will automatically start server services +// (HTTP, FTP, TFTP server, ...) when initializing the network system. +// Default: Enabled +#define NET_START_SERVICE 1 + +// OS Resource Settings +// These settings are used to optimize usage of OS resources. +// Core Thread Stack Size <512-65535:4> +// Default: 1024 bytes +#define NET_THREAD_STACK_SIZE 1024 + +// Core Thread Priority +#define NET_THREAD_PRIORITY osPriorityNormal + +// +// + +//------------- <<< end of configuration section >>> --------------------------- + +#include "RTE_Components.h" + +#ifdef RTE_Network_Interface_ETH_0 +#include "Net_Config_ETH_0.h" +#endif +#ifdef RTE_Network_Interface_ETH_1 +#include "Net_Config_ETH_1.h" +#endif + +#ifdef RTE_Network_Interface_WiFi_0 +#include "Net_Config_WiFi_0.h" +#endif + +#ifdef RTE_Network_Interface_WiFi_1 +#include "Net_Config_WiFi_1.h" +#endif + +#ifdef RTE_Network_Interface_PPP +#include "Net_Config_PPP.h" +#endif + +#ifdef RTE_Network_Interface_SLIP +#include "Net_Config_SLIP.h" +#endif + +#ifdef RTE_Network_Socket_UDP +#include "Net_Config_UDP.h" +#endif +#ifdef RTE_Network_Socket_TCP +#include "Net_Config_TCP.h" +#endif +#ifdef RTE_Network_Socket_BSD +#include "Net_Config_BSD.h" +#endif + +#ifdef RTE_Network_Web_Server_RO +#include "Net_Config_HTTP_Server.h" +#endif +#ifdef RTE_Network_Web_Server_FS +#include "Net_Config_HTTP_Server.h" +#endif + +#ifdef RTE_Network_Telnet_Server +#include "Net_Config_Telnet_Server.h" +#endif + +#ifdef RTE_Network_TFTP_Server +#include "Net_Config_TFTP_Server.h" +#endif +#ifdef RTE_Network_TFTP_Client +#include "Net_Config_TFTP_Client.h" +#endif + +#ifdef RTE_Network_FTP_Server +#include "Net_Config_FTP_Server.h" +#endif +#ifdef RTE_Network_FTP_Client +#include "Net_Config_FTP_Client.h" +#endif + +#ifdef RTE_Network_DNS_Client +#include "Net_Config_DNS_Client.h" +#endif + +#ifdef RTE_Network_SMTP_Client +#include "Net_Config_SMTP_Client.h" +#endif + +#ifdef RTE_Network_SNMP_Agent +#include "Net_Config_SNMP_Agent.h" +#endif + +#ifdef RTE_Network_SNTP_Client +#include "Net_Config_SNTP_Client.h" +#endif + +#include "net_config.h" + +/** +\addtogroup net_genFunc +@{ +*/ +/** + \fn void net_sys_error (NET_ERROR error) + \ingroup net_cores + \brief Network system error handler. +*/ +void net_sys_error (NET_ERROR error) { + /* This function is called when a fatal error is encountered. */ + /* The normal program execution is not possible anymore. */ + + switch (error) { + case NET_ERROR_MEM_ALLOC: + /* Out of memory */ + break; + + case NET_ERROR_MEM_FREE: + /* Trying to release non existing memory block */ + break; + + case NET_ERROR_MEM_CORRUPT: + /* Memory Link pointer corrupted */ + /* More data written than the size of allocated memory block */ + break; + + case NET_ERROR_CONFIG: + /* Network configuration error detected */ + break; + + case NET_ERROR_UDP_ALLOC: + /* Out of UDP Sockets */ + break; + + case NET_ERROR_TCP_ALLOC: + /* Out of TCP Sockets */ + break; + + case NET_ERROR_TCP_STATE: + /* TCP State machine in undefined state */ + break; + } + + /* End-less loop */ + while (1); +} +/** +@} +*/ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config_BSD.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config_BSD.h new file mode 100644 index 00000000..6c6505d1 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config_BSD.h @@ -0,0 +1,38 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Socket + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_BSD.h + * Purpose: Network Configuration for BSD Sockets + * Rev.: V5.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Berkley (BSD) Sockets +#define BSD_ENABLE 1 + +// Number of BSD Sockets <1-20> +// Number of available Berkeley Sockets +// Default: 2 +#define BSD_NUM_SOCKS 10 + +// Number of Streaming Server Sockets <0-20> +// Defines a number of Streaming (TCP) Server sockets, +// that listen for an incoming connection from the client. +// Default: 1 +#define BSD_SERVER_SOCKS 2 + +// Receive Timeout in seconds <0-600> +// A timeout for socket receive in blocking mode. +// Timeout value of 0 means indefinite timeout. +// Default: 20 +#define BSD_RECEIVE_TOUT 20 + +// Hostname Resolver +// Enable or disable Berkeley style hostname resolver. +#define BSD_HOSTNAME_ENABLE 0 + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config_ETH_0.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config_ETH_0.h new file mode 100644 index 00000000..c34d6fe9 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config_ETH_0.h @@ -0,0 +1,265 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Interface + * Copyright (c) 2004-2021 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_ETH_0.h + * Purpose: Network Configuration for ETH Interface + * Rev.: V7.4.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Ethernet Network Interface 0 +#define ETH0_ENABLE 1 + +// Connect to hardware via Driver_ETH# <0-255> +// Select driver control block for MAC and PHY interface +#define ETH0_DRIVER 0 + +// MAC Address +// Ethernet MAC Address in text representation +// Value FF-FF-FF-FF-FF-FF is not allowed, +// LSB of first byte must be 0 (an ethernet Multicast bit). +// Default: "1E-30-6C-A2-45-5E" +#define ETH0_MAC_ADDR "1E-30-6C-A2-45-5E" + +// VLAN +// Enable or disable Virtual LAN +#define ETH0_VLAN_ENABLE 0 + +// VLAN Identifier <1-4093> +// A unique 12-bit numeric value +// Default: 1 +#define ETH0_VLAN_ID 1 +// + +// IPv4 +// Enable IPv4 Protocol for Network Interface +#define ETH0_IP4_ENABLE 1 + +// IP Address +// Static IPv4 Address in text representation +// Default: "192.168.0.100" +#define ETH0_IP4_ADDR "192.168.0.100" + +// Subnet mask +// Local Subnet mask in text representation +// Default: "255.255.255.0" +#define ETH0_IP4_MASK "255.255.255.0" + +// Default Gateway +// IP Address of Default Gateway in text representation +// Default: "192.168.0.254" +#define ETH0_IP4_GATEWAY "192.168.0.254" + +// Primary DNS Server +// IP Address of Primary DNS Server in text representation +// Default: "8.8.8.8" +#define ETH0_IP4_PRIMARY_DNS "8.8.8.8" + +// Secondary DNS Server +// IP Address of Secondary DNS Server in text representation +// Default: "8.8.4.4" +#define ETH0_IP4_SECONDARY_DNS "8.8.4.4" + +// IP Fragmentation +// This option enables fragmentation of outgoing IP datagrams, +// and reassembling the fragments of incoming IP datagrams. +// Default: enabled +#define ETH0_IP4_FRAG_ENABLE 1 + +// MTU size <576-1500> +// Maximum Transmission Unit in bytes +// Default: 1500 +#define ETH0_IP4_MTU 1500 +// + +// ARP Address Resolution +// ARP cache and node address resolver settings +// Cache Table size <5-100> +// Number of cached MAC/IP addresses +// Default: 10 +#define ETH0_ARP_TAB_SIZE 10 + +// Cache Timeout in seconds <5-255> +// A timeout for cached hardware/IP addresses +// Default: 150 +#define ETH0_ARP_CACHE_TOUT 150 + +// Number of Retries <0-20> +// Number of Retries to resolve an IP address +// before ARP module gives up +// Default: 4 +#define ETH0_ARP_MAX_RETRY 4 + +// Resend Timeout in seconds <1-10> +// A timeout to resend the ARP Request +// Default: 2 +#define ETH0_ARP_RESEND_TOUT 2 + +// Send Notification on Address changes +// When this option is enabled, the embedded host +// will send a Gratuitous ARP notification at startup, +// or when the device IP address has changed. +// Default: Disabled +#define ETH0_ARP_NOTIFY 0 +// + +// IGMP Group Management +// Enable or disable Internet Group Management Protocol +#define ETH0_IGMP_ENABLE 0 + +// Membership Table size <2-50> +// Number of Groups this host can join +// Default: 5 +#define ETH0_IGMP_TAB_SIZE 5 +// + +// NetBIOS Name Service +// When this option is enabled, the embedded host can be +// accessed by its name on local LAN using NBNS protocol. +#define ETH0_NBNS_ENABLE 0 + +// Dynamic Host Configuration +// When this option is enabled, local IP address, Net Mask +// and Default Gateway are obtained automatically from +// the DHCP Server on local LAN. +#define ETH0_DHCP_ENABLE 1 + +// Vendor Class Identifier +// This value is optional. If specified, it is added +// to DHCP request message, identifying vendor type. +// Default: "" +#define ETH0_DHCP_VCID "" + +// Bootfile Name +// This value is optional. If enabled, the Bootfile Name +// (option 67) is also requested from DHCP server. +// Default: disabled +#define ETH0_DHCP_BOOTFILE 0 + +// NTP Servers +// This value is optional. If enabled, a list of NTP Servers +// (option 42) is also requested from DHCP server. +// Default: disabled +#define ETH0_DHCP_NTP_SERVERS 0 +// + +// Disable ICMP Echo response +#define ETH0_ICMP_NO_ECHO 0 +// + +// IPv6 +// Enable IPv6 Protocol for Network Interface +#define ETH0_IP6_ENABLE 0 + +// IPv6 Address +// Static IPv6 Address in text representation +// Use unspecified address "::" when static +// IPv6 address is not used. +// Default: "fec0::2" +#define ETH0_IP6_ADDR "fec0::2" + +// Subnet prefix-length <1-128> +// Number of bits that define network address +// Default: 64 +#define ETH0_IP6_PREFIX_LEN 64 + +// Default Gateway +// Default Gateway IPv6 Address in text representation +// Default: "fec0::1" +#define ETH0_IP6_GATEWAY "fec0::1" + +// Primary DNS Server +// Primary DNS Server IPv6 Address in text representation +// Default: "2001:4860:4860::8888" +#define ETH0_IP6_PRIMARY_DNS "2001:4860:4860::8888" + +// Secondary DNS Server +// Secondary DNS Server IPv6 Address in text representation +// Default: "2001:4860:4860::8844" +#define ETH0_IP6_SECONDARY_DNS "2001:4860:4860::8844" + +// IPv6 Fragmentation +// This option enables fragmentation of outgoing IPv6 datagrams, +// and reassembling the fragments of incoming IPv6 datagrams. +// Default: enabled +#define ETH0_IP6_FRAG_ENABLE 1 + +// MTU size <1280-1500> +// Maximum Transmission Unit in bytes +// Default: 1500 +#define ETH0_IP6_MTU 1500 +// + +// Neighbor Discovery +// Neighbor cache and node address resolver settings +// Cache Table size <5-100> +// Number of cached node addresses +// Default: 5 +#define ETH0_NDP_TAB_SIZE 5 + +// Cache Timeout in seconds <5-255> +// Timeout for cached node addresses +// Default: 150 +#define ETH0_NDP_CACHE_TOUT 150 + +// Number of Retries <0-20> +// Number of retries to resolve an IP address +// before NDP module gives up +// Default: 4 +#define ETH0_NDP_MAX_RETRY 4 + +// Resend Timeout in seconds <1-10> +// A timeout to resend Neighbor Solicitation +// Default: 2 +#define ETH0_NDP_RESEND_TOUT 2 +// + +// Dynamic Host Configuration +// When this option is enabled, local IPv6 address is +// automatically configured. +#define ETH0_DHCP6_ENABLE 1 + +// DHCPv6 Client Mode <0=>Stateless Mode <1=>Statefull Mode +// Stateless DHCPv6 Client uses router advertisements +// for IPv6 address autoconfiguration (SLAAC). +// Statefull DHCPv6 Client connects to DHCPv6 server for a +// leased IPv6 address and DNS server IPv6 addresses. +#define ETH0_DHCP6_MODE 1 + +// Vendor Class Option +// If enabled, Vendor Class option is added to DHCPv6 +// request message, identifying vendor type. +// Default: disabled +#define ETH0_DHCP6_VCLASS_ENABLE 0 + +// Enterprise ID +// Enterprise-number as registered with IANA. +// Default: 0 (Reserved) +#define ETH0_DHCP6_VCLASS_EID 0 + +// Vendor Class Data +// This string identifies vendor type. +// Default: "" +#define ETH0_DHCP6_VCLASS_DATA "" +// +// + +// Disable ICMP6 Echo response +#define ETH0_ICMP6_NO_ECHO 0 +// + +// OS Resource Settings +// These settings are used to optimize usage of OS resources. +// Interface Thread Stack Size <512-65535:4> +// Default: 512 bytes +#define ETH0_THREAD_STACK_SIZE 512 + +// Interface Thread Priority +#define ETH0_THREAD_PRIORITY osPriorityAboveNormal + +// +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config_TCP.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config_TCP.h new file mode 100644 index 00000000..602fcb90 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config_TCP.h @@ -0,0 +1,69 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Socket + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_TCP.h + * Purpose: Network Configuration for TCP Sockets + * Rev.: V7.1.1 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// TCP Sockets +#define TCP_ENABLE 1 + +// Number of TCP Sockets <1-20> +// Number of available TCP sockets +// Default: 6 +#define TCP_NUM_SOCKS 10 + +// Number of Retries <0-20> +// How many times TCP module will try to retransmit data +// before giving up. Increase this value for high-latency +// and low throughput networks. +// Default: 5 +#define TCP_MAX_RETRY 5 + +// Retry Timeout in seconds <1-10> +// If data frame not acknowledged within this time frame, +// TCP module will try to resend the data again. +// Default: 4 +#define TCP_RETRY_TOUT 4 + +// Default Connect Timeout in seconds <1-65535> +// If no TCP data frame has been exchanged during this time, +// the TCP connection is either closed or a keep-alive frame +// is sent to verify that the connection still exists. +// Default: 120 +#define TCP_DEFAULT_TOUT 120 + +// Maximum Segment Size <536-1440> +// The Maximum Segment Size specifies the maximum +// number of bytes in the TCP segment's Data field. +// Default: 1440 +#define TCP_MAX_SEG_SIZE 1440 + +// Receive Window Size <536-65535> +// Receive Window Size specifies the size of data, +// that the socket is able to buffer in flow-control mode. +// Default: 4320 +#define TCP_RECEIVE_WIN_SIZE 4320 + +// + +// TCP Initial Retransmit period in seconds +#define TCP_INITIAL_RETRY_TOUT 1 + +// TCP SYN frame retransmit period in seconds +#define TCP_SYN_RETRY_TOUT 2 + +// Number of retries to establish a connection +#define TCP_CONNECT_RETRY 7 + +// Dynamic port start (default 49152) +#define TCP_DYN_PORT_START 49152 + +// Dynamic port end (default 65535) +#define TCP_DYN_PORT_END 65535 + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config_UDP.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config_UDP.h new file mode 100644 index 00000000..a1ccacd3 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network/Net_Config_UDP.h @@ -0,0 +1,28 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Socket + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_UDP.h + * Purpose: Network Configuration for UDP Sockets + * Rev.: V5.1.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// UDP Sockets +#define UDP_ENABLE 1 + +// Number of UDP Sockets <1-20> +// Number of available UDP sockets +// Default: 5 +#define UDP_NUM_SOCKS 11 + +// + +// Dynamic port start (default 49152) +#define UDP_DYN_PORT_START 49152 + +// Dynamic port end (default 65535) +#define UDP_DYN_PORT_END 65535 + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network_Library/mongoose_custom.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network_Library/mongoose_custom.h new file mode 100644 index 00000000..7406a9cd --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/Network_Library/mongoose_custom.h @@ -0,0 +1,77 @@ + +// <<< Use Configuration Wizard in Context Menu >>> + +// System Architecture +// <0=> Bare metal +// <1=> FreeRTOS +// <2=> CMSIS-RTOS v1 +// <3=> CMSIS-RTOS v2 +// Select either bare metal operation or a supported RTOS +// "FreeRTOS" uses direct FreeRTOS calls +// "CMSIS-RTOS v1" supports only Keil RTX through API v1 +// "CMSIS-RTOS v2" supports Keil RTX5 and FreeRTOS through API v2 + +#define MG_CMSISPACK_ARCH 3 + + +// Networking support +// Networking stack +// <0=> Built-in +// <1=> lwIP +// <2=> FreeRTOS-Plus-TCP +// <3=> MDK (RL) +// Select the networking stack to use with Mongoose Library +// The built-in stack can run on bare metal or over any RTOS +// "lwIP" requires using an RTOS and BSD socket mode +// "MDK" requires using CMSIS-RTOS1 (RTX + RL) or CMSIS-RTOS2 (MDK Plus or Pro), and BSD socket mode +#define MG_CMSISPACK_NET 3 + +// Use Mbed-TLS +// Mongoose will use Mbed-TLS calls for TLS-related functionality +#define MG_ENABLE_MBEDTLS 0 +// + + +// Enable custom mg_millis() +// Use a user-provided function to get uptime in milliseconds, otherwise Mongoose will default to using time(). Except for bare metal, Mongoose will use the time base for the configured architecture +//#define MG_ENABLE_CUSTOM_MILLIS 1 +// + + +// Enable custom mg_rand() +// Use a user-provided function to generate random numbers, otherwise Mongoose will default to using rand() +#define MG_ENABLE_CUSTOM_RANDOM 1 +// + + +// Filesystem support +// Enable packed (embedded) filesystem +#define MG_ENABLE_PACKED_FS 1 +// + + +// <<< end of configuration section >>> + +// Translate to Mongoose macros +#if MG_CMSISPACK_ARCH == 1 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_FREERTOS +#elif MG_CMSISPACK_ARCH == 2 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_CMSIS_RTOS1 +#elif MG_CMSISPACK_ARCH == 3 +#undef MG_ARCH +#define MG_ARCH MG_ARCH_CMSIS_RTOS2 +#endif +#if MG_CMSISPACK_NET == 0 +#define MG_ENABLE_TCPIP 1 +#elif MG_CMSISPACK_NET == 1 +#define MG_ENABLE_LWIP 1 +#elif MG_CMSISPACK_NET == 2 +#define MG_ENABLE_FREERTOS_TCP 1 +#elif MG_CMSISPACK_NET == 3 +#define MG_ENABLE_RL 1 +#endif + + +// Add your customization below this comment diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/_Target_1/Pre_Include_Global.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/_Target_1/Pre_Include_Global.h new file mode 100644 index 00000000..8aabd0e0 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/_Target_1/Pre_Include_Global.h @@ -0,0 +1,17 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'device-dashboard' + * Target: 'Target 1' + */ + +#ifndef PRE_INCLUDE_GLOBAL_H +#define PRE_INCLUDE_GLOBAL_H + +/* Keil::Device:STM32Cube HAL:Common:1.3.0 */ +#define USE_HAL_DRIVER + + +#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/_Target_1/RTE_Components.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/_Target_1/RTE_Components.h new file mode 100644 index 00000000..5c8ea711 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/RTE/_Target_1/RTE_Components.h @@ -0,0 +1,68 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'device-dashboard' + * Target: 'Target 1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f7xx.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.4 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:User:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_User /* Compiler I/O: STDOUT User */ +/* Keil.MDK-Plus::Network:CORE:IPv4 Release:7.18.0 */ +#define RTE_Network_Core /* Network Core */ + #define RTE_Network_IPv4 /* Network IPv4 Stack */ + #define RTE_Network_Release /* Network Release Version */ +/* Keil.MDK-Plus::Network:Interface:ETH:7.18.0 */ +#define RTE_Network_Interface_ETH_0 /* Network Interface ETH 0 */ + +/* Keil.MDK-Plus::Network:Socket:BSD:7.18.0 */ +#define RTE_Network_Socket_BSD /* Network Socket BSD */ +/* Keil.MDK-Plus::Network:Socket:TCP:7.18.0 */ +#define RTE_Network_Socket_TCP /* Network Socket TCP */ +/* Keil.MDK-Plus::Network:Socket:UDP:7.18.0 */ +#define RTE_Network_Socket_UDP /* Network Socket UDP */ +/* Keil::CMSIS Driver:Ethernet MAC:1.12.0 */ +#define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */ +/* Keil::CMSIS Driver:Ethernet PHY:LAN8742A:1.3.0 */ +#define RTE_Drivers_PHY_LAN8742A /* Driver PHY LAN8742A */ +/* Keil::Device:STM32Cube Framework:STM32CubeMX:1.1.0 */ +#define RTE_DEVICE_FRAMEWORK_CUBE_MX +/* Keil::Device:STM32Cube HAL:Common:1.3.0 */ +#define RTE_DEVICE_HAL_COMMON +/* Keil::Device:STM32Cube HAL:Cortex:1.3.0 */ +#define RTE_DEVICE_HAL_CORTEX +/* Keil::Device:STM32Cube HAL:DMA:1.3.0 */ +#define RTE_DEVICE_HAL_DMA +/* Keil::Device:STM32Cube HAL:ETH:1.3.0 */ +#define RTE_DEVICE_HAL_ETH +/* Keil::Device:STM32Cube HAL:GPIO:1.3.0 */ +#define RTE_DEVICE_HAL_GPIO +/* Keil::Device:STM32Cube HAL:PWR:1.3.0 */ +#define RTE_DEVICE_HAL_PWR +/* Keil::Device:STM32Cube HAL:RCC:1.3.0 */ +#define RTE_DEVICE_HAL_RCC +/* Keil::Device:STM32Cube HAL:RNG:1.3.0 */ +#define RTE_DEVICE_HAL_RNG +/* Keil::Device:STM32Cube HAL:TIM:1.3.0 */ +#define RTE_DEVICE_HAL_TIM +/* Keil::Device:STM32Cube HAL:UART:1.3.0 */ +#define RTE_DEVICE_HAL_UART +/* Keil::Device:Startup:1.2.5 */ +#define RTE_DEVICE_STARTUP_STM32F7XX /* Device Startup for STM32F7 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/device-dashboard.uvguix b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/device-dashboard.uvguix new file mode 100644 index 00000000..23b1eaa3 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/device-dashboard.uvguix @@ -0,0 +1,3709 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 1920 + 1080 + + + + + + 1 + 0 + + 100 + 0 + + RTE\Network_Library\mongoose_custom.h + 41 + 1 + 11 + 1 + + 0 + + + RTE\CMSIS\RTX_Config.h + 22 + 130 + 149 + 1 + + 0 + + + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + 43 + 76 + 91 + 1 + + 0 + + + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + 15 + 1 + 1 + 1 + + 0 + + + .\main.c + 0 + 34 + 35 + 1 + + 0 + + + RTE\Device\STM32F746ZGTx\startup_stm32f746xx.s + 0 + 184 + 188 + 1 + + 0 + + + RTE\Network\Net_Config.c + 0 + 1 + 1 + 1 + + 0 + + + RTE\Network\Net_Config_BSD.h + 0 + 1 + 1 + 1 + + 0 + + + RTE\Network\Net_Config_ETH_0.h + 0 + 1 + 1 + 1 + + 0 + + + RTE\Network\Net_Config_TCP.h + 0 + 1 + 1 + 1 + + 0 + + + RTE\Network\Net_Config_UDP.h + 0 + 1 + 1 + 1 + + 0 + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/device-dashboard.uvoptx b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/device-dashboard.uvoptx new file mode 100644 index 00000000..c14b5281 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/device-dashboard.uvoptx @@ -0,0 +1,382 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp; *.cc; *.cxx + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 16000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 18 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(6017=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(6016=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + ST-LINKIII-KEIL_SWO + -U-O206 -O206 -SF10000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP (ARM Core") -D00(5BA02477) -L00(0) -TO131090 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024.FLM -FS08000000 -FL0100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FF1STM32F7xTCM_1024.FLM -FS1200000 -FL1100000 -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + + + + + + 1 + 0 + 0x20017800 + 0 + + + + C:\Users\scaprile\AppData\Local\Arm\Packs\ARM\CMSIS\5.9.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.9.0 + 1 + + + C:\Users\scaprile\AppData\Local\Arm\Packs\Keil\MDK-Middleware\7.16.0\Network\Network.scvd + Keil.MDK-Middleware.7.16.0 + 1 + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 10000000 + + + + + + Source Group 1 + 1 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + .\hal.h + hal.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + .\net.c + net.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + .\packed_fs.c + packed_fs.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + .\syscalls.c + syscalls.c + 0 + 0 + + + + + :STM32CubeMX:Common Sources + 1 + 0 + 0 + 0 + + 2 + 6 + 1 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + main.c + 0 + 0 + + + 2 + 7 + 5 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Inc\stm32f7xx_it.h + stm32f7xx_it.h + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + stm32f7xx_it.c + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + + + ::CMSIS Driver + 1 + 0 + 0 + 1 + + + + ::Compiler + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + + ::Network + 1 + 0 + 0 + 1 + + + + ::Network Library + 1 + 0 + 0 + 1 + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/device-dashboard.uvprojx b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/device-dashboard.uvprojx new file mode 100644 index 00000000..d9207b4c --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/device-dashboard.uvprojx @@ -0,0 +1,707 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + STM32F746ZGTx + STMicroelectronics + Keil.STM32F7xx_DFP.2.15.1 + https://www.keil.com/pack/ + IRAM(0x20010000,0x40000) IRAM2(0x20000000,0x10000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746ZGTx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + 0 + $$Device:STM32F746ZGTx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h + + + + + + + + + + $$Device:STM32F746ZGTx$CMSIS\SVD\STM32F746.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + device-dashboard + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x200000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 6 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 0 + + -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion -Wno-unused-parameter -Wconversion -Wno-sign-conversion -fno-common -fdata-sections + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20010000 + + + + + --diag_suppress 6918 + + + + + + + + Source Group 1 + + + hal.h + 5 + .\hal.h + + + main.c + 1 + .\main.c + + + net.c + 1 + .\net.c + + + packed_fs.c + 1 + .\packed_fs.c + + + syscalls.c + 1 + .\syscalls.c + + + + + :STM32CubeMX:Common Sources + + + main.c + 1 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\main.c + + + stm32f7xx_it.h + 5 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Inc\stm32f7xx_it.h + + + stm32f7xx_it.c + 1 + .\RTE\Device\STM32F746ZGTx\STCubeGenerated\Src\stm32f7xx_it.c + + + + + ::CMSIS + + + ::CMSIS Driver + + + ::Compiler + + + ::Device + + + ::Network + + + ::Network Library + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Device\STM32F746ZGTx\startup_stm32f746xx.s + + + + + + + + RTE\Device\STM32F746ZGTx\system_stm32f7xx.c + + + + + + + + RTE\Network\Net_Config.c + + + + + + + + RTE\Network\Net_Config_BSD.h + + + + + + + + RTE\Network\Net_Config_ETH_0.h + + + + + + + + RTE\Network\Net_Config_TCP.h + + + + + + + + RTE\Network\Net_Config_UDP.h + + + + + + + + RTE\Network_Library\mongoose_custom.h + + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/hal.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/hal.h new file mode 100644 index 00000000..0516da74 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/hal.h @@ -0,0 +1,11 @@ +// Copyright (c) 2022-23 Cesanta Software Limited +// All rights reserved +// https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf + +#pragma once + +#include + +#ifndef UART_DEBUG +#define UART_DEBUG USART3 +#endif diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/main.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/main.c new file mode 100644 index 00000000..f3b6ce01 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/main.c @@ -0,0 +1,84 @@ +// Copyright (c) 2023 Cesanta Software Limited +// All rights reserved + +#include "hal.h" +#include "mongoose.h" +#include "main.h" +#include "cmsis_os2.h" + +#define BLINK_PERIOD_MS 1000 // LED blinking period in millis + + +void mg_random(void *buf, size_t len) { // Use on-board RNG + extern RNG_HandleTypeDef hrng; + for (size_t n = 0; n < len; n += sizeof(uint32_t)) { + uint32_t r; + HAL_RNG_GenerateRandomNumber(&hrng, &r); + memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r)); + } +} + +static void server(void *args) { + struct mg_mgr mgr; // Initialise Mongoose event manager + mg_mgr_init(&mgr); // and attach it to the interface + mg_log_set(MG_LL_DEBUG); // Set log level + + MG_INFO(("Initialising application...")); + extern void device_dashboard_fn(struct mg_connection *, int, void *, void *); + mg_http_listen(&mgr, "http://0.0.0.0", device_dashboard_fn, NULL); + + MG_INFO(("Starting event loop")); + for (;;) mg_mgr_poll(&mgr, 1000); // Infinite event loop + (void) args; +} + +static void blinker(void *args) { + for (;;) { + HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_7); // Blink On-board blue LED + osDelay((osKernelGetTickFreq() * BLINK_PERIOD_MS) / 1000U); + } + (void) args; +} + +osThreadId_t s_am; + +// see rl_net_ds.h +void netDHCP_Notify (uint32_t if_num, uint8_t option, const uint8_t *val, uint32_t len) { + if (option == NET_DHCP_OPTION_IP_ADDRESS) osThreadFlagsSet(s_am, 1<<0); + (void)if_num, (void)val, (void)len; +} + +__NO_RETURN static void app_main (void *args) { + uint8_t ipaddr[NET_ADDR_IP4_LEN]; + char ip[40]; + + netInitialize(); + MG_INFO(("Waiting for IP...")); + osThreadFlagsWait (1<<0, osFlagsWaitAny, osWaitForever); // wait for DHCP + osThreadFlagsClear(1<<0); + netIF_GetOption (NET_IF_CLASS_ETH, netIF_OptionIP4_Address, ipaddr, sizeof(ipaddr)); + netIP_ntoa (NET_ADDR_IP4, ipaddr, ip, sizeof(ip)); + MG_INFO(("READY, IP: %s", ip)); + + const osThreadAttr_t server_attr = { + .stack_size = 8192 // Create the server thread with a stack size of 8KB + }; + osThreadNew(server, NULL, &server_attr); + osThreadTerminate(osThreadGetId()); + for(;;); + (void)args; +} + +extern void mx_init(void); + +int main(void) { + mx_init(); // Setup clock and all peripherals configured in CubeMX + // Initialise random number generator + // Initialise ethernet pins + osKernelInitialize(); // Initialize CMSIS-RTOS + osThreadNew(blinker, NULL, NULL); // Create the blinker thread with a default stack size + s_am = osThreadNew(app_main, NULL, NULL); // Create the thread that will start networking, use a default stack size + osKernelStart(); // This blocks + return 0; +} + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/syscalls.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/syscalls.c new file mode 100644 index 00000000..79113968 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5-mdk/syscalls.c @@ -0,0 +1,10 @@ +#include +#include + +#include "main.h" + +int stdout_putchar (int ch) { + extern UART_HandleTypeDef huart3; + HAL_UART_Transmit(&huart3, (const uint8_t *)&ch, 1, 100); + return ch; +} diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/EventRecorderStub.scvd b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/EventRecorderStub.scvd new file mode 100644 index 00000000..0fb3ee58 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/README.md b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/README.md new file mode 100644 index 00000000..9f1fe6fc --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/README.md @@ -0,0 +1,7 @@ +# RTX5 Web device dashboard on NUCLEO-F746ZG, built on Keil MDK + +- Open this example with Keil uVision +- Build it +- Run/Debug it + +Mongoose configuration is in mongoose_custom.h, inside Network_Library diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/RTE/CMSIS/RTX_Config.c b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/RTE/CMSIS/RTX_Config.c new file mode 100644 index 00000000..938a5658 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/RTE/CMSIS/RTX_Config.h b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/RTE/CMSIS/RTX_Config.h new file mode 100644 index 00000000..eea24592 --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,580 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.2 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 65536 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 0 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc new file mode 100644 index 00000000..e5b26add --- /dev/null +++ b/extra/cmsis-pack/Boards/ST/NUCLEO-F746ZG/nucleo-f746zg-keil-rtx5/RTE/Device/STM32F746ZGTx/FrameworkCubeMX.gpdsc @@ -0,0 +1,64 @@ + + + + + Keil + FrameworkCubeMX + STM32CubeMX generated pack description + project-path + + + - Generated: 23/05/2023 17:07:03 + + + + + STM32CubeMX Environment +