Add OTA to the device dashboard. Implement for H5

examples/stm32/nucleo-h563zi-make-baremetal-builtin/Makefile

@@ -12,8 +12,7 @@ SOURCES += cmsis_h5/Source/Templates/gcc/startup_stm32h563xx.s # ST startup file
 SOURCES += mongoose.c net.c packed_fs.c
 CFLAGS += -DMG_ENABLE_TCPIP=1 -DMG_ARCH=MG_ARCH_NEWLIB -DMG_ENABLE_CUSTOM_MILLIS=1
 CFLAGS += -DMG_ENABLE_CUSTOM_RANDOM=1 -DMG_ENABLE_PACKED_FS=1 
-CFLAGS += -DMG_ENABLE_DRIVER_STM32H=1 $(CFLAGS_EXTRA)
-CFLAGS += $(CFLAGS_EXTRA)
+CFLAGS += -DMG_ENABLE_DRIVER_STM32H=1 -DMG_OTA=MG_OTA_STM32H5 $(CFLAGS_EXTRA)
 
 # Example specific build options. See README.md
 CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\"

examples/stm32/nucleo-h563zi-make-baremetal-builtin/hal.h

@@ -39,8 +39,8 @@ enum {
 };
 // Make sure your chip package uses the internal LDO, otherwise set PLL1_N = 200
 enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 250, PLL1_P = 2 };
-#define FLASH_LATENCY 0x25  // WRHIGHFREQ LATENCY
-#define CPU_FREQUENCY ((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / (BIT(HPRE - 7))) * 1000000)
+#define CPU_FREQUENCY \
+  ((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / (BIT(HPRE - 7))) * 1000000)
 #define AHB_FREQUENCY CPU_FREQUENCY
 #define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(PPRE2 - 3)))
 #define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(PPRE1 - 3)))
@@ -137,8 +137,8 @@ static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
 
 static inline void rng_init(void) {
   RCC->CCIPR5 |= RCC_CCIPR5_RNGSEL_0;  // RNG clock source pll1_q_ck
-  RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;  // Enable RNG clock
-  RNG->CR |= RNG_CR_RNGEN;            // Enable RNG
+  RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;   // Enable RNG clock
+  RNG->CR |= RNG_CR_RNGEN;             // Enable RNG
 }
 static inline uint32_t rng_read(void) {
   while ((RNG->SR & RNG_SR_DRDY) == 0) spin(1);

examples/stm32/nucleo-h563zi-make-baremetal-builtin/link.ld

@@ -3,7 +3,7 @@ MEMORY {
   flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k
   sram(rwx) : ORIGIN = 0x20000000, LENGTH = 640k 
 }
-_estack     = ORIGIN(sram) + LENGTH(sram);    /* stack points to end of SRAM */
+_estack = ORIGIN(sram) + LENGTH(sram);    /* End of RAM. stack points here */
 
 SECTIONS {
   .vectors  : { KEEP(*(.isr_vector)) }  > flash
@@ -11,19 +11,20 @@ SECTIONS {
   .rodata   : { *(.rodata*) }           > flash
 
   .data : {
-    _sdata = .;   /* for init_ram() */
+    _sdata = .;
     *(.first_data)
+    *(.ram)
     *(.data SORT(.data.*))
-    _edata = .;  /* for init_ram() */
+    _edata = .;
   } > sram AT > flash
   _sidata = LOADADDR(.data);
 
   .bss : {
-    _sbss = .;              /* for init_ram() */
+    _sbss = .;
     *(.bss SORT(.bss.*) COMMON)
-    _ebss = .;              /* for init_ram() */
+    _ebss = .;
   } > sram
 
   . = ALIGN(8);
-  _end = .;     /* for cmsis_gcc.h and init_ram() */
+  _end = .;
 }

examples/stm32/nucleo-h563zi-make-baremetal-builtin/main.c

@@ -35,7 +35,6 @@ static void timer_fn(void *arg) {
 int main(void) {
   gpio_output(LED);               // Setup green LED
   uart_init(UART_DEBUG, 115200);  // Initialise debug printf
-  ethernet_init();                // Initialise ethernet pins
 
   MG_INFO(("Starting, CPU freq %g MHz", (double) SystemCoreClock / 1000000));
   struct mg_mgr mgr;        // Initialise
@@ -43,6 +42,7 @@ int main(void) {
   mg_log_set(MG_LL_DEBUG);  // Set log level
 
   // Initialise Mongoose network stack
+  ethernet_init();  // Initialise ethernet pins
   struct mg_tcpip_driver_stm32h_data driver_data = {.mdc_cr = 4};
   struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(),
                             // Uncomment below for static configuration:

examples/stm32/nucleo-h563zi-make-baremetal-builtin/sysinit.c

@@ -13,6 +13,11 @@ void SystemInit(void) {  // Called automatically by startup code
   SCB->CPACR |= ((3UL << 20U) | (3UL << 22U));  // Enable FPU
   asm("DSB");
   asm("ISB");
+
+  // Set flash latency. RM0481, section 7.11.1, section 7.3.4 table 37
+  SETBITS(FLASH->ACR, (FLASH_ACR_WRHIGHFREQ_Msk | FLASH_ACR_LATENCY_Msk),
+          FLASH_ACR_LATENCY_5WS | FLASH_ACR_WRHIGHFREQ_1);
+
   if (ldo_is_on()) {
     PWR->VOSCR = PWR_VOSCR_VOS_0 | PWR_VOSCR_VOS_1;  // Select VOS0
   } else {
@@ -21,7 +26,6 @@ void SystemInit(void) {  // Called automatically by startup code
   uint32_t f = PWR->VOSCR;  // fake read to wait for bus clocking
   while ((PWR->VOSSR & PWR_VOSSR_ACTVOSRDY) == 0) spin(1);
   (void) f;
-  FLASH->ACR |= FLASH_LATENCY;
   RCC->CR = RCC_CR_HSION;                          // Clear HSI clock divisor
   while ((RCC->CR & RCC_CR_HSIRDY) == 0) spin(1);  // Wait until done
   RCC->CFGR2 = (PPRE3 << 12) | (PPRE2 << 8) | (PPRE1 << 4) | (HPRE << 0);