From 3270f1252b474361c104faa2d9350022faffe49b Mon Sep 17 00:00:00 2001 From: "Sergio R. Caprile" Date: Fri, 2 Sep 2022 11:18:11 -0300 Subject: [PATCH] Enable FPU --- examples/stm32/nucleo-f429zi-baremetal/Makefile | 2 +- examples/stm32/nucleo-f429zi-baremetal/mcu.h | 4 +++- examples/stm32/nucleo-f746zg-baremetal/Makefile | 2 +- examples/stm32/nucleo-f746zg-baremetal/mcu.h | 4 +++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/examples/stm32/nucleo-f429zi-baremetal/Makefile b/examples/stm32/nucleo-f429zi-baremetal/Makefile index 4f68bddc..25baa026 100644 --- a/examples/stm32/nucleo-f429zi-baremetal/Makefile +++ b/examples/stm32/nucleo-f429zi-baremetal/Makefile @@ -8,7 +8,7 @@ CFLAGS ?= -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion \ -g3 -Os -ffunction-sections -fdata-sections -I. -I$(ROOT) \ -DMG_ARCH=MG_ARCH_NEWLIB -DMIP_DEBUG=1 -DMG_ENABLE_PACKED_FS=1 \ -DMG_ENABLE_CUSTOM_MILLIS=1 -DxMG_ENABLE_LINES=1 -DMG_ENABLE_MIP=1 \ - -mcpu=cortex-m4 -mthumb -mfloat-abi=soft $(EXTRA_CFLAGS) + -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 $(EXTRA_CFLAGS) LDFLAGS ?= -Tlink.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map SOURCES = boot.c main.c syscalls.c \ $(ROOT)/mongoose.c \ diff --git a/examples/stm32/nucleo-f429zi-baremetal/mcu.h b/examples/stm32/nucleo-f429zi-baremetal/mcu.h index 28af5ecd..7fd919c6 100644 --- a/examples/stm32/nucleo-f429zi-baremetal/mcu.h +++ b/examples/stm32/nucleo-f429zi-baremetal/mcu.h @@ -203,8 +203,10 @@ static inline void clock_init(void) { // Set clock frequency while ((PWR->CSR & BIT(16)) == 0) spin(1); // Wait until done PWR->CR |= BIT(17); // Enable overdrive switching while ((PWR->CSR & BIT(17)) == 0) spin(1); // Wait until done - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU #endif + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU + asm ("DSB"); + asm ("ISB"); FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch, Icache, Dcache RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P diff --git a/examples/stm32/nucleo-f746zg-baremetal/Makefile b/examples/stm32/nucleo-f746zg-baremetal/Makefile index ee2f73c2..087f5da6 100644 --- a/examples/stm32/nucleo-f746zg-baremetal/Makefile +++ b/examples/stm32/nucleo-f746zg-baremetal/Makefile @@ -8,7 +8,7 @@ CFLAGS ?= -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion \ -g3 -Os -ffunction-sections -fdata-sections -I. -I$(ROOT) \ -DMG_ARCH=MG_ARCH_NEWLIB -DMIP_DEBUG=1 -DMG_ENABLE_PACKED_FS=1 \ -DMG_ENABLE_CUSTOM_MILLIS=1 -DxMG_ENABLE_LINES=1 -DMG_ENABLE_MIP=1 \ - -mcpu=cortex-m7 -mthumb -mfloat-abi=soft $(EXTRA_CFLAGS) + -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 $(EXTRA_CFLAGS) LDFLAGS ?= -Tlink.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map SOURCES = boot.c main.c syscalls.c \ $(ROOT)/mongoose.c \ diff --git a/examples/stm32/nucleo-f746zg-baremetal/mcu.h b/examples/stm32/nucleo-f746zg-baremetal/mcu.h index 056497dd..b7891ad7 100644 --- a/examples/stm32/nucleo-f746zg-baremetal/mcu.h +++ b/examples/stm32/nucleo-f746zg-baremetal/mcu.h @@ -203,8 +203,10 @@ static inline void clock_init(void) { // Set clock frequency while ((PWR->CSR1 & BIT(16)) == 0) spin(1); // Wait until done PWR->CR1 |= BIT(17); // Enable overdrive switching while ((PWR->CSR1 & BIT(17)) == 0) spin(1); // Wait until done - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU #endif + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU + asm ("DSB"); + asm ("ISB"); FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P