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Rename mongoose_custom as mongoose_config
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@@ -15559,11 +15559,12 @@ struct mg_tcpip_driver mg_tcpip_driver_imxrt = {mg_tcpip_driver_imxrt_init,
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#endif
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enum { // ID1 ID2
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MG_PHY_KSZ8x = 0x22, // 0022 1561 - KSZ8081RNB
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MG_PHY_DP83x = 0x2000, // 2000 a140 - TI DP83825I
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MG_PHY_LAN87x = 0x7, // 0007 c0fx - LAN8720
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MG_PHY_RTL8201 = 0x1C // 001c c816 - RTL8201
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enum { // ID1 ID2
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MG_PHY_KSZ8x = 0x22, // 0022 1561 - KSZ8081RNB
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MG_PHY_DP83x = 0x2000, // 2000 a140 - TI DP83825I
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MG_PHY_DP83867 = 0xa231, // 2000 a231 - TI DP83867I
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MG_PHY_LAN87x = 0x7, // 0007 c0fx - LAN8720
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MG_PHY_RTL8201 = 0x1C // 001c c816 - RTL8201
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};
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enum {
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@@ -15572,6 +15573,7 @@ enum {
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MG_PHY_REG_ID1 = 2,
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MG_PHY_REG_ID2 = 3,
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MG_PHY_DP83x_REG_PHYSTS = 16,
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MG_PHY_DP83867_REG_PHYSTS = 17,
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MG_PHY_DP83x_REG_RCSR = 23,
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MG_PHY_DP83x_REG_LEDCR = 24,
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MG_PHY_KSZ8x_REG_PC1R = 30,
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@@ -15584,7 +15586,12 @@ enum {
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static const char *mg_phy_id_to_str(uint16_t id1, uint16_t id2) {
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switch (id1) {
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case MG_PHY_DP83x:
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return "DP83x";
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switch (id2) {
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case MG_PHY_DP83867:
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return "DP83867";
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default:
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return "DP83x";
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}
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case MG_PHY_KSZ8x:
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return "KSZ8x";
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case MG_PHY_LAN87x:
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@@ -15609,9 +15616,9 @@ void mg_phy_init(struct mg_phy *phy, uint8_t phy_addr, uint8_t config) {
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if (config & MG_PHY_CLOCKS_MAC) {
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// Use PHY crystal oscillator (preserve defaults)
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// nothing to do
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} else { // MAC clocks PHY, PHY has no xtal
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} else { // MAC clocks PHY, PHY has no xtal
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// Enable 50 MHz external ref clock at XI (preserve defaults)
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if (id1 == MG_PHY_DP83x) {
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if (id1 == MG_PHY_DP83x && id2 != MG_PHY_DP83867) {
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phy->write_reg(phy_addr, MG_PHY_DP83x_REG_RCSR, MG_BIT(7) | MG_BIT(0));
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} else if (id1 == MG_PHY_KSZ8x) {
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phy->write_reg(phy_addr, MG_PHY_KSZ8x_REG_PC2R,
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@@ -15644,9 +15651,18 @@ bool mg_phy_up(struct mg_phy *phy, uint8_t phy_addr, bool *full_duplex,
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if (up && full_duplex != NULL && speed != NULL) {
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uint16_t id1 = phy->read_reg(phy_addr, MG_PHY_REG_ID1);
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if (id1 == MG_PHY_DP83x) {
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uint16_t physts = phy->read_reg(phy_addr, MG_PHY_DP83x_REG_PHYSTS);
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*full_duplex = physts & MG_BIT(2);
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*speed = (physts & MG_BIT(1)) ? MG_PHY_SPEED_10M : MG_PHY_SPEED_100M;
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uint16_t id2 = phy->read_reg(phy_addr, MG_PHY_REG_ID2);
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if (id2 == MG_PHY_DP83867) {
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uint16_t physts = phy->read_reg(phy_addr, MG_PHY_DP83867_REG_PHYSTS);
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*full_duplex = physts & MG_BIT(13);
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*speed = (physts & MG_BIT(15)) ? MG_PHY_SPEED_1000M
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: (physts & MG_BIT(14)) ? MG_PHY_SPEED_100M
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: MG_PHY_SPEED_10M;
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} else {
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uint16_t physts = phy->read_reg(phy_addr, MG_PHY_DP83x_REG_PHYSTS);
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*full_duplex = physts & MG_BIT(2);
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*speed = (physts & MG_BIT(1)) ? MG_PHY_SPEED_10M : MG_PHY_SPEED_100M;
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}
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} else if (id1 == MG_PHY_KSZ8x) {
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uint16_t pc1r = phy->read_reg(phy_addr, MG_PHY_KSZ8x_REG_PC1R);
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*full_duplex = pc1r & MG_BIT(2);
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