stm32 -> stm32f

src/drivers/stm32f.c

@@ -1,7 +1,7 @@
-#include "tcpip.h"
+#include "net_builtin.h"
 
-#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_STM32) && MG_ENABLE_DRIVER_STM32
-struct stm32_eth {
+#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_STM32F) && MG_ENABLE_DRIVER_STM32F
+struct stm32f_eth {
   volatile uint32_t MACCR, MACFFR, MACHTHR, MACHTLR, MACMIIAR, MACMIIDR, MACFCR,
       MACVLANTR, RESERVED0[2], MACRWUFFR, MACPMTCSR, RESERVED1, MACDBGR, MACSR,
       MACIMR, MACA0HR, MACA0LR, MACA1HR, MACA1LR, MACA2HR, MACA2LR, MACA3HR,
@@ -15,7 +15,7 @@ struct stm32_eth {
       DMACHRBAR;
 };
 #undef ETH
-#define ETH ((struct stm32_eth *) (uintptr_t) 0x40028000)
+#define ETH ((struct stm32f_eth *) (uintptr_t) 0x40028000)
 
 #define ETH_PKT_SIZE 1540  // Max frame size
 #define ETH_DESC_CNT 4     // Descriptors count
@@ -101,9 +101,9 @@ static int guess_mdc_cr(void) {
   return result;
 }
 
-static bool mg_tcpip_driver_stm32_init(struct mg_tcpip_if *ifp) {
-  struct mg_tcpip_driver_stm32_data *d =
-      (struct mg_tcpip_driver_stm32_data *) ifp->driver_data;
+static bool mg_tcpip_driver_stm32f_init(struct mg_tcpip_if *ifp) {
+  struct mg_tcpip_driver_stm32f_data *d =
+      (struct mg_tcpip_driver_stm32f_data *) ifp->driver_data;
   s_ifp = ifp;
 
   // Init RX descriptors
@@ -154,7 +154,7 @@ static bool mg_tcpip_driver_stm32_init(struct mg_tcpip_if *ifp) {
   return true;
 }
 
-static size_t mg_tcpip_driver_stm32_tx(const void *buf, size_t len,
+static size_t mg_tcpip_driver_stm32f_tx(const void *buf, size_t len,
                                        struct mg_tcpip_if *ifp) {
   if (len > sizeof(s_txbuf[s_txno])) {
     MG_ERROR(("Frame too big, %ld", (long) len));
@@ -177,7 +177,7 @@ static size_t mg_tcpip_driver_stm32_tx(const void *buf, size_t len,
   return len;
 }
 
-static bool mg_tcpip_driver_stm32_up(struct mg_tcpip_if *ifp) {
+static bool mg_tcpip_driver_stm32f_up(struct mg_tcpip_if *ifp) {
   uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR);
   bool up = bsr & MG_BIT(2) ? 1 : 0;
   if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) {  // link state just went up
@@ -222,7 +222,7 @@ void ETH_IRQHandler(void) {
   ETH->DMARPDR = 0;          // and resume RX
 }
 
-struct mg_tcpip_driver mg_tcpip_driver_stm32 = {mg_tcpip_driver_stm32_init,
-                                                mg_tcpip_driver_stm32_tx, NULL,
-                                                mg_tcpip_driver_stm32_up};
+struct mg_tcpip_driver mg_tcpip_driver_stm32f = {mg_tcpip_driver_stm32f_init,
+                                                mg_tcpip_driver_stm32f_tx, NULL,
+                                                mg_tcpip_driver_stm32f_up};
 #endif

src/drivers/stm32f.h

@@ -1,6 +1,6 @@
 #pragma once
 
-struct mg_tcpip_driver_stm32_data {
+struct mg_tcpip_driver_stm32f_data {
   // MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz
   //    HCLK range    DIVIDER    mdc_cr VALUE
   //    -------------------------------------

src/drivers/stm32h.c

@@ -1,4 +1,4 @@
-#include "tcpip.h"
+#include "net_builtin.h"
 
 #if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_STM32H) && \
     MG_ENABLE_DRIVER_STM32H
@@ -152,7 +152,7 @@ static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
   // Init RX descriptors
   for (int i = 0; i < ETH_DESC_CNT; i++) {
     s_rxdesc[i][0] = (uint32_t) (uintptr_t) s_rxbuf[i];  // Point to data buffer
-    s_rxdesc[i][3] = MG_BIT(31) | MG_BIT(30) | MG_BIT(24);        // OWN, IOC, BUF1V
+    s_rxdesc[i][3] = MG_BIT(31) | MG_BIT(30) | MG_BIT(24);  // OWN, IOC, BUF1V
   }
 
   // Init TX descriptors
@@ -169,9 +169,9 @@ static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
 
   // NOTE(scaprile): We do not use timing facilities so the DMA engine does not
   // re-write buffer address
-  ETH->DMAMR = 0 << 16;     // use interrupt mode 0 (58.8.1) (reset value)
+  ETH->DMAMR = 0 << 16;        // use interrupt mode 0 (58.8.1) (reset value)
   ETH->DMASBMR |= MG_BIT(12);  // AAL NOTE(scaprile): is this actually needed
-  ETH->MACIER = 0;        // Do not enable additional irq sources (reset value)
+  ETH->MACIER = 0;  // Do not enable additional irq sources (reset value)
   ETH->MACTFCR = MG_BIT(7);  // Disable zero-quanta pause
   // ETH->MACPFR = MG_BIT(31);  // Receive all
   eth_write_phy(PHY_ADDR, PHY_BCR, MG_BIT(15));  // Reset PHY
@@ -217,10 +217,10 @@ static size_t mg_tcpip_driver_stm32h_tx(const void *buf, size_t len,
     for (int i = 0; i < ETH_DESC_CNT; i++) MG_ERROR(("%08X", s_txdesc[i][3]));
     len = 0;  // All descriptors are busy, fail
   } else {
-    memcpy(s_txbuf[s_txno], buf, len);        // Copy data
-    s_txdesc[s_txno][2] = (uint32_t) len;     // Set data len
+    memcpy(s_txbuf[s_txno], buf, len);              // Copy data
+    s_txdesc[s_txno][2] = (uint32_t) len;           // Set data len
     s_txdesc[s_txno][3] = MG_BIT(28) | MG_BIT(29);  // FD, LD
-    s_txdesc[s_txno][3] |= MG_BIT(31);           // Set OWN bit - let DMA take over
+    s_txdesc[s_txno][3] |= MG_BIT(31);  // Set OWN bit - let DMA take over
     if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
   }
   ETH->DMACSR |= MG_BIT(2) | MG_BIT(1);  // Clear any prior TBU, TPS
@@ -250,8 +250,8 @@ static bool mg_tcpip_driver_stm32h_up(struct mg_tcpip_if *ifp) {
 void ETH_IRQHandler(void);
 static uint32_t s_rxno;
 void ETH_IRQHandler(void) {
-  if (ETH->DMACSR & MG_BIT(6)) {            // Frame received, loop
-    ETH->DMACSR = MG_BIT(15) | MG_BIT(6);      // Clear flag
+  if (ETH->DMACSR & MG_BIT(6)) {           // Frame received, loop
+    ETH->DMACSR = MG_BIT(15) | MG_BIT(6);  // Clear flag
     for (uint32_t i = 0; i < 10; i++) {  // read as they arrive but not forever
       if (s_rxdesc[s_rxno][3] & MG_BIT(31)) break;  // exit when done
       if (((s_rxdesc[s_rxno][3] & (MG_BIT(28) | MG_BIT(29))) ==
@@ -262,11 +262,13 @@ void ETH_IRQHandler(void) {
         // ETH->DMACSR));
         mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp);
       }
-      s_rxdesc[s_rxno][3] = MG_BIT(31) | MG_BIT(30) | MG_BIT(24);  // OWN, IOC, BUF1V
+      s_rxdesc[s_rxno][3] =
+          MG_BIT(31) | MG_BIT(30) | MG_BIT(24);  // OWN, IOC, BUF1V
       if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
     }
   }
-  ETH->DMACSR = MG_BIT(7) | MG_BIT(8);  // Clear possible RBU RPS while processing
+  ETH->DMACSR =
+      MG_BIT(7) | MG_BIT(8);  // Clear possible RBU RPS while processing
   ETH->DMACRDTPR =
       (uint32_t) (uintptr_t) &s_rxdesc[ETH_DESC_CNT - 1];  // and resume RX
 }