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Merge pull request #2360 from cesanta/h7

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Fix sysinit in H7
This commit is contained in:
Sergio R. Caprile authored and GitHub committed 2023-08-23 14:37:21 -03:00
2 parents 48516b43c5 80b7be0568
commit 41448278cf
2 files changed
+12 -12
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examples/stm32/nucleo-h743zi-make-baremetal-builtin/sysinit.c
+6 -6
View File
@@ -28,14 +28,14 @@ void SystemInit(void) { // Called automatically by startup code
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
asm("DSB"); asm("DSB");
asm("ISB"); asm("ISB");
PWR->CR3 |= BIT(1); // select LDO (reset value) PWR->CR3 |= BIT(1); // select LDO (reset value)
while ((PWR->CSR1 && BIT(13)) == 0) spin(1); // ACTVOSRDY while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
PWR->D3CR |= BIT(15) | BIT(14); // Select VOS1 PWR->D3CR |= BIT(15) | BIT(14); // Select VOS1
uint32_t f = PWR->D3CR; // fake read to wait for bus clocking uint32_t f = PWR->D3CR; // fake read to wait for bus clocking
while ((PWR->CSR1 && BIT(13)) == 0) spin(1); // ACTVOSRDY while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
SYSCFG->PWRCR |= BIT(0); // ODEN SYSCFG->PWRCR |= BIT(0); // ODEN
f = SYSCFG->PWRCR; f = SYSCFG->PWRCR;
while ((PWR->CSR1 && BIT(13)) == 0) spin(1); // ACTVOSRDY while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
(void) f; (void) f;
SETBITS( SETBITS(
RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0), RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0),
examples/stm32/nucleo-h743zi-make-freertos-builtin/sysinit.c
+6 -6
View File
@@ -28,14 +28,14 @@ void SystemInit(void) { // Called automatically by startup code
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
asm("DSB"); asm("DSB");
asm("ISB"); asm("ISB");
PWR->CR3 |= BIT(1); // select LDO (reset value) PWR->CR3 |= BIT(1); // select LDO (reset value)
while ((PWR->CSR1 && BIT(13)) == 0) spin(1); // ACTVOSRDY while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
PWR->D3CR |= BIT(15) | BIT(14); // Select VOS1 PWR->D3CR |= BIT(15) | BIT(14); // Select VOS1
uint32_t f = PWR->D3CR; // fake read to wait for bus clocking uint32_t f = PWR->D3CR; // fake read to wait for bus clocking
while ((PWR->CSR1 && BIT(13)) == 0) spin(1); // ACTVOSRDY while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
SYSCFG->PWRCR |= BIT(0); // ODEN SYSCFG->PWRCR |= BIT(0); // ODEN
f = SYSCFG->PWRCR; f = SYSCFG->PWRCR;
while ((PWR->CSR1 && BIT(13)) == 0) spin(1); // ACTVOSRDY while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
(void) f; (void) f;
SETBITS( SETBITS(
RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0), RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0),