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Merge pull request #3575 from cesanta/bsd
Add BSD sockets API on top of net_builtin
This commit is contained in:
14 files changed
+2104
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@@ -0,0 +1,39 @@
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#pragma once
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#include "hal.h"
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#define configUSE_PREEMPTION 1
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#define configCPU_CLOCK_HZ SYS_FREQUENCY
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#define configTICK_RATE_HZ 1000
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#define configMAX_PRIORITIES 5
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#define configUSE_16_BIT_TICKS 0
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#define configUSE_TICK_HOOK 0
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#define configUSE_IDLE_HOOK 0
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#define configUSE_TIMERS 0
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#define configUSE_CO_ROUTINES 0
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#define configUSE_MALLOC_FAILED_HOOK 0
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#define configMINIMAL_STACK_SIZE 128
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#define configTOTAL_HEAP_SIZE (1024 * 64)
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#define INCLUDE_vTaskDelay 1
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#define INCLUDE_vTaskDelete 1
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#define INCLUDE_xTaskGetSchedulerState 1
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#ifdef __NVIC_PRIO_BITS
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#define configPRIO_BITS __NVIC_PRIO_BITS
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#else
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#define configPRIO_BITS 4
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#endif
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#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 15
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#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
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#define configKERNEL_INTERRUPT_PRIORITY \
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(configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
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#define configMAX_SYSCALL_INTERRUPT_PRIORITY \
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(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
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#define configASSERT(expr) \
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if (!(expr)) printf("FAILURE %s:%d: %s\n", __FILE__, __LINE__, #expr)
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#define vPortSVCHandler SVC_Handler
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#define xPortPendSVHandler PendSV_Handler
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//#define xPortSysTickHandler SysTick_Handler
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@@ -0,0 +1,59 @@
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# Copyright (c) 2026 Cesanta Software Limited
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# Environment setup: https://mongoose.ws/docs/getting-started/build-environment/
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CFLAGS = -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion
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CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
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CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
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CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_h7/Include -Imongoose
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CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA)
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LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nosys.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
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SOURCES = main.c hal.c
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SOURCES += cmsis_h7/Source/Templates/gcc/startup_stm32h723xx.s
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SOURCES += mongoose/mongoose.c
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# FreeRTOS. H7 has a Cortex-M7 r1p0 core, FreeRTOS recommends using CM4F port for non-r0p1 CM7 micros
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SOURCES += FreeRTOS-Kernel/tasks.c FreeRTOS-Kernel/list.c FreeRTOS-Kernel/queue.c
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SOURCES += FreeRTOS-Kernel/portable/MemMang/heap_4.c
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SOURCES += FreeRTOS-Kernel/portable/GCC/ARM_CM4F/port.c
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CFLAGS += -IFreeRTOS-Kernel/include
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CFLAGS += -IFreeRTOS-Kernel/portable/GCC/ARM_CM4F -Wno-conversion
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all build example: firmware.bin
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mongoose/mongoose.c mongoose/mongoose.h:
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cp ../../../../mongoose.[ch] mongoose/
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firmware.elf: cmsis_core cmsis_h7 FreeRTOS-Kernel hal.h link.ld Makefile $(SOURCES) mongoose/mongoose.h
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arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(CFLAGS_EXTRA) $(LDFLAGS) -o $@
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firmware.bin: firmware.elf
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arm-none-eabi-objcopy -O binary $< $@
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@echo
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@echo "To flash, run 'make flash', or use STM32CubeProgrammer"
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flash: firmware.bin
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STM32_Programmer_CLI -c port=swd -w firmware.elf -hardRst
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cmsis_core:
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git clone -q -c advice.detachedHead=false --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
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cmsis_h7:
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git clone -q -c advice.detachedHead=false --depth 1 -b v1.10.6 https://github.com/STMicroelectronics/cmsis_device_h7 $@
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FreeRTOS-Kernel:
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git clone --depth 1 -b V11.3.0 https://github.com/FreeRTOS/FreeRTOS-Kernel $@
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clean:
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rm -rf firmware.* cmsis_* mongoose/mongoose.*
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# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
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DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/10
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update: firmware.bin
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
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test update: CFLAGS_EXTRA = -DUART_DEBUG=USART1
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test: update
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt
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grep 'READY, IP:' /tmp/output.txt # Check for network init
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@@ -0,0 +1,125 @@
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// Copyright (c) 2026 Cesanta Software Limited
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// All rights reserved
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#include "hal.h"
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bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now) {
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uint64_t diff = now - *t; // Wrap-safe elapsed time since last expiry
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if (period == 0) return false; // Avoid division by zero
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if (diff < period) return false; // Period has not elapsed yet
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*t += (diff / period) * period; // Preserve cadence, skip missed periods
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return true;
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}
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static volatile uint64_t s_ticks; // Milliseconds since boot
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void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
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s_ticks++;
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}
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uint64_t hal_get_tick(void) {
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return s_ticks;
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};
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uint32_t SystemCoreClock = 160000000;
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void SystemInit(void) { // Called automatically by startup code
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hal_system_init(); // Enable FPU
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hal_clock_init();
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SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
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}
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void ExitRun0Mode(void) {
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}
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struct stat;
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__attribute__((weak)) int _fstat(int fd, struct stat *st) {
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(void) fd, (void) st;
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return -1;
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}
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extern unsigned char _end[]; // End of data section, start of heap. See link.ld
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static unsigned char *s_current_heap_end = _end;
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size_t hal_ram_used(void) {
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return (size_t) (s_current_heap_end - _end);
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}
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size_t hal_ram_free(void) {
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unsigned char endofstack;
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return (size_t) (&endofstack - s_current_heap_end);
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}
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void *_sbrk(int incr) {
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unsigned char *prev_heap;
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unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
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prev_heap = s_current_heap_end;
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// Check how much space we got from the heap end to the stack end
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if (s_current_heap_end + incr > heap_end) return (void *) -1;
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s_current_heap_end += incr;
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return prev_heap;
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}
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__attribute__((weak)) int _open(const char *path) {
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(void) path;
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return -1;
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}
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__attribute__((weak)) int _close(int fd) {
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(void) fd;
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return -1;
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}
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__attribute__((weak)) int _isatty(int fd) {
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(void) fd;
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return 1;
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}
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__attribute__((weak)) int _lseek(int fd, int ptr, int dir) {
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(void) fd, (void) ptr, (void) dir;
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return 0;
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}
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__attribute__((weak)) void _exit(int status) {
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(void) status;
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for (;;) asm volatile("BKPT #0");
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}
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__attribute__((weak)) void _kill(int pid, int sig) {
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(void) pid, (void) sig;
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}
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__attribute__((weak)) int _getpid(void) {
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return -1;
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}
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__attribute__((weak)) int _write(int fd, char *ptr, int len) {
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(void) fd, (void) ptr, (void) len;
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return -1;
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}
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__attribute__((weak)) int _read(int fd, char *ptr, int len) {
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(void) fd, (void) ptr, (void) len;
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return -1;
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}
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__attribute__((weak)) int _link(const char *a, const char *b) {
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(void) a, (void) b;
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return -1;
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}
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__attribute__((weak)) int _unlink(const char *a) {
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(void) a;
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return -1;
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}
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__attribute__((weak)) int _stat(const char *path, struct stat *st) {
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(void) path, (void) st;
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return -1;
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}
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__attribute__((weak)) int mkdir(const char *path, int mode) {
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(void) path, (void) mode;
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return -1;
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}
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__attribute__((weak)) void _init(void) {
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}
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@@ -0,0 +1,219 @@
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// Copyright (c) 2022-2026 Cesanta Software Limited
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// Datasheet: RM0468, devboard manual: UM2407
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// https://www.st.com/resource/en/reference_manual/rm0468-stm32h723733-stm32h725735-and-stm32h730-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
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// https://www.st.com/resource/en/user_manual/um2407-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf
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// Alternate functions: https://www.st.com/resource/en/datasheet/stm32h723.pdf
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#pragma once
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#include <stm32h723xx.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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extern bool hal_timer_expired(volatile uint64_t *t, uint64_t prd, uint64_t now);
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extern uint64_t hal_get_tick(void);
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extern size_t hal_ram_free(void);
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extern size_t hal_ram_used(void);
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extern uint32_t SystemCoreClock;
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#define BIT(x) (1UL << (x))
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#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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#define HAL_ETH_PINS PIN('A', 1), PIN('A', 2), PIN('A', 7), \
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PIN('B', 13), PIN('C', 1), PIN('C', 4), \
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PIN('C', 5), PIN('G', 11), PIN('G', 13)
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// System clock (2.1, Figure 1; 8.5, Figure 45; 8.5.5, Figure 47; 8.5.6, Figure
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// 49; 8.5.8 Table 56; datasheet) CPU_FREQUENCY <= 550 MHz; hclk = CPU_FREQUENCY
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// / HAL_HPRE ; hclk <= 275 MHz; APB clocks <= 137.5 MHz. D1 domain bus matrix (and
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// so flash) runs at hclk frequency. Configure flash latency (WS) in accordance
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// to hclk freq (4.3.8, Table 16) The Ethernet controller is in D2 domain and
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// runs at hclk frequency
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enum {
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HAL_D1CPRE = 1, // actual divisor value
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HAL_HPRE = 2, // actual divisor value
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HAL_D1PPRE = 4, // register values, divisor value = BIT(value - 3) = / 2
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HAL_D2PPRE1 = 4,
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HAL_D2PPRE2 = 4,
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HAL_D3PPRE = 4
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};
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// PLL1_P: odd division factors are not allowed (8.7.12) (except for '1')
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enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 225, PLL1_P = 1 };
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#define HAL_FLASH_LATENCY 0x33 // WRHIGHFREQ LATENCY
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#define SYS_FREQUENCY ((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / HAL_D1CPRE) * 1000000)
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#define AHB_FREQUENCY (SYS_FREQUENCY / HAL_HPRE)
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#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(HAL_D2PPRE2 - 3)))
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#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(HAL_D2PPRE1 - 3)))
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static inline void hal_spin(volatile uint32_t n) {
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while (n--) (void) 0;
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}
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enum { HAL_GPIO_MODE_INPUT, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_MODE_AF, HAL_GPIO_MODE_ANALOG };
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enum { HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_OTYPE_OPEN_DRAIN };
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enum { HAL_GPIO_SPEED_LOW, HAL_GPIO_SPEED_MEDIUM, HAL_GPIO_SPEED_HIGH, HAL_GPIO_SPEED_INSANE };
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enum { HAL_GPIO_PULL_NONE, HAL_GPIO_PULL_UP, HAL_GPIO_PULL_DOWN };
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#define HAL_GPIO(N) ((GPIO_TypeDef *) (0x40000000 + 0x18020000UL + 0x400 * (N)))
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static GPIO_TypeDef *hal_gpio_bank(uint16_t pin) {
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return HAL_GPIO(PINBANK(pin));
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}
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static inline void hal_gpio_toggle(uint16_t pin) {
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GPIO_TypeDef *gpio = hal_gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
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}
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static inline int hal_gpio_read(uint16_t pin) {
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return hal_gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
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}
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static inline void hal_gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = hal_gpio_bank(pin);
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gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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GPIO_TypeDef *gpio = hal_gpio_bank(pin);
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uint8_t n = (uint8_t) (PINNO(pin));
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RCC->AHB4ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
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CLRSET(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
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CLRSET(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
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CLRSET(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
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CLRSET(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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CLRSET(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
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}
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static inline void hal_gpio_input(uint16_t pin) {
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hal_gpio_init(pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH,
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HAL_GPIO_PULL_NONE, 0);
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}
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static inline void hal_gpio_output(uint16_t pin) {
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hal_gpio_init(pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH,
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HAL_GPIO_PULL_NONE, 0);
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}
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// D2 Kernel clock (8.7.21) USART1 defaults to pclk2 (APB2), while USART2,3
|
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// default to pclk1 (APB1). Even if using other kernel clocks, the APBx clocks
|
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// must be enabled for CPU access, as the kernel clock drives the BRR, not the
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// APB bus interface
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static inline void hal_uart_init(USART_TypeDef *uart, uint16_t tx,
|
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uint16_t rx, unsigned long baud) {
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uint8_t af = 7; // Alternate function
|
||||
uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
|
||||
|
||||
if (uart == USART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
|
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if (uart == USART2) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(17);
|
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if (uart == USART3) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(18);
|
||||
|
||||
#if 0 // CONSTANT BAUD RATE FOR REMOTE DEBUGGING WHILE SETTING THE PLL
|
||||
CLRSET(RCC->D2CCIP2R, 7 << 3, 3 << 3); // use HSI for UART1
|
||||
freq = 64000000;
|
||||
#endif
|
||||
|
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hal_gpio_init(tx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af);
|
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hal_gpio_init(rx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af);
|
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uart->CR1 = 0; // Disable this UART
|
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uart->BRR = freq / baud; // Set baud rate
|
||||
uart->CR1 = BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
|
||||
}
|
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static inline void hal_uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
|
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uart->TDR = byte;
|
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while ((uart->ISR & BIT(7)) == 0) hal_spin(1);
|
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}
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static inline void hal_uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) hal_uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int hal_uart_read_ready(USART_TypeDef *uart) {
|
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return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
|
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}
|
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static inline uint8_t hal_uart_read_byte(USART_TypeDef *uart) {
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return (uint8_t) (uart->RDR & 255);
|
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}
|
||||
|
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// RNG clock (rng_clk) defaults to HSI48 and is characterized at this frequency.
|
||||
// Enable at SystemInit. (STM32CubeMX) It won't work with a 275MHz (AHB)
|
||||
static inline void hal_rng_init(void) {
|
||||
RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; // Enable RNG AHB clock (hal_rng_hclk)
|
||||
// 39.6.2 Table 320 init
|
||||
RNG->CR = RNG_CR_CONDRST | (0x0F << RNG_CR_RNG_CONFIG1_Pos) |
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||||
(0 << RNG_CR_RNG_CONFIG2_Pos) | (0xD << RNG_CR_RNG_CONFIG3_Pos);
|
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RNG->HTCR = 0x17590abc;
|
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RNG->HTCR = 0xaa74;
|
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RNG->CR &= ~RNG_CR_CONDRST ;
|
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while(RNG->CR & RNG_CR_CONDRST) hal_spin(1); // 39.7.1
|
||||
RNG->CR |= RNG_CR_RNGEN; // Enable RNG
|
||||
}
|
||||
|
||||
static inline uint32_t hal_rng_read(void) {
|
||||
while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
|
||||
return RNG->DR;
|
||||
}
|
||||
|
||||
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
|
||||
static inline void hal_ethernet_init(void) {
|
||||
// Initialise Ethernet. Enable MAC GPIO pins, see
|
||||
// https://www.st.com/resource/en/user_manual/um2407-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf
|
||||
uint16_t pins[] = {HAL_ETH_PINS};
|
||||
for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
|
||||
hal_gpio_init(pins[i], HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_INSANE,
|
||||
HAL_GPIO_PULL_NONE, 11); // 11 is the Ethernet function
|
||||
}
|
||||
NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
|
||||
CLRSET(SYSCFG->PMCR, 7 << 21, 4 << 21); // Use RMII (12.3.1)
|
||||
RCC->AHB1ENR |= BIT(15) | BIT(16) | BIT(17); // Enable Ethernet clocks
|
||||
}
|
||||
|
||||
static inline unsigned int hal_div2prescval(unsigned int div) {
|
||||
// 0 --> /1; 8 --> /2 ... 11 --> /16; 12 --> /64 ... 15 --> /512
|
||||
if (div == 1) return 0;
|
||||
if (div > 16) div /= 2;
|
||||
unsigned int val = 7;
|
||||
while (div >>= 1) ++val;
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned int hal_pllrge(unsigned int f) {
|
||||
unsigned int val = 0;
|
||||
while (f >>= 1) ++val;
|
||||
return val - 1;
|
||||
}
|
||||
|
||||
static inline void hal_clock_init(void) {
|
||||
PWR->CR3 |= BIT(1); // select LDO (reset value)
|
||||
while ((PWR->CSR1 & BIT(13)) == 0) hal_spin(1); // ACTVOSRDY
|
||||
PWR->D3CR &= ~(BIT(15) | BIT(14)); // Select VOS0
|
||||
while ((PWR->D3CR & BIT(13)) == 0) hal_spin(1); // VOSRDY
|
||||
CLRSET(
|
||||
RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0),
|
||||
(hal_div2prescval(HAL_D1CPRE) << 8) | (HAL_D1PPRE << 4) | (hal_div2prescval(HAL_HPRE) << 0));
|
||||
RCC->D2CFGR = (HAL_D2PPRE2 << 8) | (HAL_D2PPRE1 << 4);
|
||||
RCC->D3CFGR = (HAL_D3PPRE << 4);
|
||||
CLRSET(RCC->PLLCFGR, 3 << 2,
|
||||
hal_pllrge(PLL1_HSI / PLL1_M)
|
||||
<< 2); // keep reset config (DIVP1EN, !PLL1VCOSEL), PLL1RGE
|
||||
CLRSET(RCC->PLL1DIVR, (0x7F << 9) | (0x1FF << 0),
|
||||
((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0)); // Set PLL1_P PLL1_N
|
||||
CLRSET(RCC->PLLCKSELR, 0x3F << 4,
|
||||
PLL1_M << 4); // Set PLL1_M (source defaults to HSI)
|
||||
RCC->CR |= BIT(24) | BIT(12); // Enable PLL1 and HSI48 (for RNG)
|
||||
while ((RCC->CR & BIT(25)) == 0) hal_spin(1); // Wait until done
|
||||
RCC->CFGR |= (3 << 0); // Set clock source to PLL1
|
||||
while ((RCC->CFGR & (7 << 3)) != (3 << 3)) hal_spin(1); // Wait until done
|
||||
FLASH->ACR = HAL_FLASH_LATENCY; // default is larger
|
||||
RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; // Enable SYSCFG
|
||||
while ((RCC->CR & BIT(13)) == 0) hal_spin(1); // Make sure HSI48 is ready
|
||||
SystemCoreClock = SYS_FREQUENCY; // Update SystemCoreClock global var
|
||||
SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
|
||||
}
|
||||
|
||||
static inline void hal_system_init(void) {
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
@@ -0,0 +1,28 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash(rx) : ORIGIN = 0x08000000, LENGTH = 1024k
|
||||
|
||||
dtcmram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
ram_d1 (rwx) : ORIGIN = 0x24000000, LENGTH = 320K
|
||||
ram_d2 (rwx) : ORIGIN = 0x30000000, LENGTH = 32K
|
||||
ram_d3 (rwx) : ORIGIN = 0x38000000, LENGTH = 16K
|
||||
itcmram (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||
}
|
||||
_estack = ORIGIN(ram_d1) + LENGTH(ram_d1);
|
||||
|
||||
SECTIONS {
|
||||
.vectors : { KEEP(*(.isr_vector)) } > flash
|
||||
.text : { *(.text* .text.*) } > flash
|
||||
.rodata : { *(.rodata*) } > flash
|
||||
|
||||
/* Note the .iram section, for functions copied to RAM. Required for MG_IRAM OTA support */
|
||||
.data : { _sdata = .; *(.first_data) *(.iram .iram* .iram.*) *(.data SORT(.data.*)) _edata = .; } > ram_d1 AT > flash
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : { _sbss = .; *(.bss SORT(.bss.*) COMMON) _ebss = .; } > ram_d1
|
||||
|
||||
.eth_ram : { *(.eth_ram .eth_ram*) } > ram_d1 AT > flash
|
||||
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
}
|
||||
@@ -0,0 +1,142 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// Two FreeRTOS tasks sharing one Mongoose event manager via the BSD socket
|
||||
// shim (MG_ENABLE_BSD_SOCKETS). task1 owns the manager and drives the
|
||||
// network; task2 accepts connections and spawns per-connection echo_tasks
|
||||
// that speak standard BSD sockets.
|
||||
|
||||
#include "hal.h"
|
||||
#include "mongoose.h"
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG USART3
|
||||
#define UART_DEBUG_TX_PIN PIN('D', 8)
|
||||
#define UART_DEBUG_RX_PIN PIN('D', 9)
|
||||
#else
|
||||
#define UART_DEBUG_TX_PIN PIN('A', 9)
|
||||
#define UART_DEBUG_RX_PIN PIN('A', 10)
|
||||
#endif
|
||||
|
||||
#define LED1 PIN('B', 0)
|
||||
#define LED2 PIN('E', 1)
|
||||
#define LED3 PIN('B', 14)
|
||||
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
if (fd == 1) hal_uart_write_buf(UART_DEBUG, ptr, (size_t) len);
|
||||
return len;
|
||||
}
|
||||
|
||||
static void blink_task(void) {
|
||||
static uint64_t t = 0;
|
||||
if (hal_timer_expired(&t, 500, hal_get_tick())) hal_gpio_toggle(LED1);
|
||||
}
|
||||
|
||||
uint64_t mg_millis(void) { return hal_get_tick(); }
|
||||
|
||||
bool mg_random(void *buf, size_t len) {
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = hal_rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) {
|
||||
if (ev == MG_EV_HTTP_MSG) {
|
||||
struct mg_http_message *hm = (struct mg_http_message *) ev_data;
|
||||
if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) {
|
||||
mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), hal_get_tick());
|
||||
} else {
|
||||
mg_http_reply(c, 200, "", "Hi from Mongoose, tick %llu\n", hal_get_tick());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// task1: network owner. Runs the Mongoose event loop (mg_bsd_poll drives both
|
||||
// the TCP/IP stack and the BSD command queue) and blinks the LED.
|
||||
static void task1(void *args) {
|
||||
static struct mg_mgr mgr;
|
||||
mg_mgr_init(&mgr);
|
||||
mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL);
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
mg_bsd_poll(&mgr);
|
||||
blink_task();
|
||||
}
|
||||
(void) args;
|
||||
}
|
||||
|
||||
// client_task: connects to mongoose.ws:80, fetches "/", logs response length.
|
||||
// Spawned when the echo server receives a message starting with "42".
|
||||
static void client_task(void *args) {
|
||||
struct hostent *h = gethostbyname("mongoose.ws");
|
||||
if (!h) { MG_ERROR(("DNS failed")); vTaskDelete(NULL); return; }
|
||||
int fd = socket(AF_INET, SOCK_STREAM, 0);
|
||||
struct sockaddr_in sa = {.sin_family = AF_INET, .sin_port = htons(80)};
|
||||
memcpy(&sa.sin_addr, h->h_addr, 4);
|
||||
if (connect(fd, (struct sockaddr *) &sa, sizeof(sa)) < 0) {
|
||||
MG_ERROR(("connect failed")); close(fd); vTaskDelete(NULL); return;
|
||||
}
|
||||
const char *req = "GET / HTTP/1.0\r\nHost: mongoose.ws\r\n\r\n";
|
||||
send(fd, req, strlen(req), 0);
|
||||
size_t total = 0;
|
||||
char buf[512];
|
||||
ssize_t n;
|
||||
while ((n = recv(fd, buf, sizeof(buf), 0)) > 0) total += (size_t) n;
|
||||
MG_INFO(("mongoose.ws response: %lu bytes", (unsigned long) total));
|
||||
close(fd);
|
||||
vTaskDelete(NULL);
|
||||
(void) args;
|
||||
}
|
||||
|
||||
// echo_task: one per accepted connection. Echoes data back.
|
||||
// If a message starts with "42", also spawns a client_task to fetch mongoose.ws.
|
||||
static void echo_task(void *args) {
|
||||
int fd = (int) (uintptr_t) args;
|
||||
char buf[512];
|
||||
ssize_t n;
|
||||
while ((n = recv(fd, buf, sizeof(buf), 0)) > 0) {
|
||||
if (n >= 2 && buf[0] == '4' && buf[1] == '2')
|
||||
xTaskCreate(client_task, "client", 1024, NULL, configMAX_PRIORITIES - 1, NULL);
|
||||
send(fd, buf, (size_t) n, 0);
|
||||
}
|
||||
close(fd);
|
||||
vTaskDelete(NULL);
|
||||
}
|
||||
|
||||
// task2: accept loop. Waits for incoming connections on port 1234 and spawns
|
||||
// an echo_task for each one, allowing concurrent clients.
|
||||
static void task2(void *args) {
|
||||
mg_bsd_init();
|
||||
int lfd = socket(AF_INET, SOCK_STREAM, 0);
|
||||
struct sockaddr_in sa = {.sin_family = AF_INET, .sin_port = htons(1234), .sin_addr = {INADDR_ANY}};
|
||||
bind(lfd, (struct sockaddr *) &sa, sizeof(sa));
|
||||
listen(lfd, 5);
|
||||
MG_INFO(("BSD echo server on :1234"));
|
||||
for (;;) {
|
||||
int fd = accept(lfd, NULL, NULL);
|
||||
if (fd < 0) continue;
|
||||
xTaskCreate(echo_task, "echo", 512, (void *) (uintptr_t) fd,
|
||||
configMAX_PRIORITIES - 1, NULL);
|
||||
}
|
||||
(void) args;
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
hal_clock_init();
|
||||
hal_uart_init(UART_DEBUG, UART_DEBUG_TX_PIN, UART_DEBUG_RX_PIN, 115200);
|
||||
hal_rng_init();
|
||||
hal_ethernet_init();
|
||||
hal_gpio_output(LED1);
|
||||
hal_gpio_output(LED2);
|
||||
hal_gpio_output(LED3);
|
||||
MG_INFO(("CPU clock: %lu MHz", SystemCoreClock / 1000000));
|
||||
|
||||
// task2 at higher priority than task1 so that when task1 pushes data into
|
||||
// recv_q, task2 preempts immediately, echoes, and yields before MG_EV_CLOSE.
|
||||
xTaskCreate(task1, "task1", 2048, NULL, configMAX_PRIORITIES - 2, NULL);
|
||||
xTaskCreate(task2, "task2", 256, NULL, configMAX_PRIORITIES - 1, NULL);
|
||||
vTaskStartScheduler();
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,37 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/docs/getting-started/build-options/
|
||||
#define MG_ARCH MG_ARCH_ARMGCC
|
||||
#define MG_TLS MG_TLS_BUILTIN
|
||||
#define MG_OTA MG_OTA_STM32H7
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_FREERTOS 1
|
||||
#define MG_ENABLE_BSD_SOCKETS 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_DRIVER_STM32H 1
|
||||
#define MG_ENABLE_PACKED_FS 1
|
||||
#define MG_ETH_RAM __attribute__((section(".eth_ram")))
|
||||
|
||||
// #define MG_DRIVER_MDC_CR 4 // RMII MDC clock divider, from 0 to 5
|
||||
// #define MG_TCPIP_PHY_ADDR 0 // PHY address
|
||||
|
||||
// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
|
||||
// By default, those are set to zero, meaning that DHCP is used
|
||||
//
|
||||
// #define MG_TCPIP_IP MG_IPV4(192, 168, 0, 10) // IP
|
||||
// #define MG_TCPIP_GW MG_IPV4(192, 168, 0, 1) // Gateway
|
||||
// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0) // Netmask
|
||||
|
||||
// Construct MAC address from the MCU unique ID
|
||||
#define MGUID ((uint32_t *) 0x1ff1e800) // Unique 96-bit chip ID
|
||||
#define MG_SET_MAC_ADDRESS(mac) \
|
||||
do { \
|
||||
mac[0] = 2; \
|
||||
mac[1] = MGUID[0] & 255; \
|
||||
mac[2] = (MGUID[0] >> 10) & 255; \
|
||||
mac[3] = (MGUID[0] >> 19) & 255; \
|
||||
mac[4] = MGUID[1] & 255; \
|
||||
mac[5] = MGUID[2] & 255; \
|
||||
} while (0)
|
||||
Reference in new issue
Block a user