mirror of
https://github.com/cesanta/mongoose.git
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@@ -0,0 +1,43 @@
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# Environment setup: https://mongoose.ws/documentation/tutorials/tools/
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CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
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||||
CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
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CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
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CFLAGS += -Wno-cast-function-type
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CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/Include
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CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA) -DCORE_CM7
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LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nosys.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
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# Wi-Fi chip firmware stuff
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CFLAGS += -Imbed/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD # nvram header includes a text file
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CFLAGS += -DMG_HAL_DISABLE_ETHERNET
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SOURCES = main.c hal.c mongoose.c
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SOURCES += cmsis_mcu/Source/Templates/gcc/startup_stm32h747xx.s
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all build: firmware.bin
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firmware.bin: firmware.elf
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arm-none-eabi-objcopy -O binary $< $@
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arm-none-eabi-size --format=berkeley $<
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firmware.elf: cmsis_core cmsis_mcu mbed $(SOURCES) $(wildcard *.h) link.ld Makefile
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arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
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flash: firmware.bin
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STM32_Programmer_CLI -c port=swd -w $< 0x8040000 -hardRst
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cmsis_core: # ARM CMSIS core headers
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git clone --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
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cmsis_mcu: # Keil CMSIS headers and drivers for STM32F7 series (CMSIS-pack)
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git clone --depth 1 -b v1.10.4 https://github.com/STMicroelectronics/cmsis_device_h7 $@
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# Wi-Fi chip firmware
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mbed:
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git clone --depth 1 --no-checkout -b extrapatches-6.17.0 https://github.com/arduino/mbed-os $@ && cd $@ && git sparse-checkout set targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/resources && git checkout
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touch wiced_resource.h
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clean:
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rm -rf firmware.* cmsis_core cmsis_mcu mbed
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@@ -0,0 +1,3 @@
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# Arduino Portenta H7
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Use Mongoose bare metal on the Portenta H7, with only CMSIS and no other overhead
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@@ -0,0 +1,243 @@
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// Copyright (c) 2024 Cesanta Software Limited
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// All rights reserved
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#include "hal.h"
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#define MG_HAL_SYSTICK_NONE 1
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#define MG_HAL_SYSTICK_FREERTOS 2
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#ifndef MG_HAL_SYSTICK
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#define MG_HAL_SYSTICK 0
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#endif
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#if MG_HAL_SYSTICK == MG_HAL_SYSTICK_FREERTOS
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#include <FreeRTOS.h>
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#include <task.h>
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extern void xPortSysTickHandler(void);
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void SysTick_Handler(void) {
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if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
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xPortSysTickHandler();
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}
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#elif MG_HAL_SYSTICK != MG_HAL_SYSTICK_NONE
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static volatile uint64_t s_ticks; // Milliseconds since boot
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void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
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s_ticks++;
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}
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#endif
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#ifndef MG_HAL_DISABLE_RANDOM
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#ifdef MG_HAL_ENABLE_PRNG
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static void rng_init(void);
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static uint32_t rng_read(void);
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#endif
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bool mg_random(void *buf, size_t len) { // Use on-board RNG or custom PRNG
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for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
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uint32_t r = rng_read();
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memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
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}
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return true; // TODO(): change rng_read() sig: check chip RNG, return false
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}
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#endif
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#ifndef MG_HAL_DISABLE_MILLIS
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uint64_t mg_millis(void) { // Return number of milliseconds since boot
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// handle architectures with non-atomic 64-bit access, see #3041
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uint64_t ticks = s_ticks; // first read
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if (ticks == s_ticks) return ticks; // second read, same value => OK
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return s_ticks; // changed while reading, read again
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}
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#endif
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#ifndef MG_HAL_DISABLE_SYSTEM_INIT
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uint32_t SystemCoreClock;
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void SystemInit(void) { // Called automatically by startup code
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system_init();
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}
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#endif
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#ifdef MG_HAL_ARCH_ARMCGT
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#include <lowlev.h>
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int _write(int fd, const char *ptr, unsigned int len) {
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(void) fd, (void) ptr, (void) len;
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if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
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return len;
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}
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#endif
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|
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void hal_init(void) {
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#ifndef MG_HAL_DISABLE_CLOCK
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clock_init(); // Set system clock to SYS_FREQUENCY
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SystemCoreClock = SYS_FREQUENCY; // Update SystemCoreClock global var
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#endif
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#if MG_HAL_SYSTICK != MG_HAL_SYSTICK_NONE
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SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
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#endif
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#ifndef MG_HAL_DISABLE_RANDOM
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rng_init(); // Initialise random number generator
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#endif
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#ifndef MG_HAL_DISABLE_UART
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uart_init(UART_DEBUG, 115200); // Initialise UART
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#ifdef MG_HAL_ARCH_ARMCGT
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_stream[1].dfd = 1;
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_stream[1].dev->WRITE = _write; // redirect stream to _write syscall
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#endif
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#endif
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leds_init();
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#ifndef MG_HAL_DISABLE_ETHERNET
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ethernet_init(); // Initialise Ethernet pins
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#endif
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}
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#ifdef MG_HAL_ENABLE_GENMAC
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void hal_genmac(unsigned char *mac) {
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ethernet_genmac(mac);
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}
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#endif
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#ifdef MG_HAL_ENABLE_PRNG
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static uint32_t s_hal_rng_seed;
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static void rng_init(void) {
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s_hal_rng_seed = entropy_init();
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}
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static uint32_t rng_read() {
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uint32_t seed = s_hal_rng_seed;
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uint32_t ent;
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if (entropy_get(&ent)) {
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// Factor both previous seed and current ent value into a new seed
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ent *= 0x85ebca6b;
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ent ^= (ent << 16);
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ent ^= (ent >> 5);
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seed ^= ent;
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seed *= 0x5bd1e995;
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seed ^= seed << 13;
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seed ^= seed >> 17;
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seed ^= seed << 5;
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seed += ent;
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seed ^= seed >> 16;
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} else {
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// apply complex bit permutations / arithmetical ops for better randomness
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seed ^= seed >> 3;
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seed *= 2654435761U;
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seed ^= seed << 13;
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seed *= 0x85ebca6b;
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seed ^= seed >> 16;
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seed *= 0xc2b2ae35;
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seed ^= seed >> 13;
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}
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s_hal_rng_seed = seed;
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return seed;
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}
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#endif
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#if defined(__ARMCC_VERSION)
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// Keil specific - implement IO printf redirection
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int fputc(int c, FILE *stream) {
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if (stream == stdout || stream == stderr) uart_write_byte(UART_DEBUG, c);
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return c;
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}
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#elif defined(__GNUC__) && !defined(MG_HAL_DISABLE_NEWLIB)
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// ARM GCC specific. ARM GCC is shipped with Newlib C library.
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// Implement newlib syscalls:
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// _sbrk() for malloc
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// _write() for printf redirection
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// the rest are just stubs
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#include <sys/stat.h> // For _fstat()
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int _fstat(int fd, struct stat *st) {
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(void) fd, (void) st;
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return -1;
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}
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#ifndef MG_HAL_SBRK_NONE
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extern unsigned char _end[]; // End of data section, start of heap. See link.ld
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static unsigned char *s_current_heap_end = _end;
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size_t hal_ram_used(void) {
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return (size_t) (s_current_heap_end - _end);
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}
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size_t hal_ram_free(void) {
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unsigned char endofstack;
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return (size_t) (&endofstack - s_current_heap_end);
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}
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void *_sbrk(int incr) {
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unsigned char *prev_heap;
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#ifndef MG_HAL_SBRK_SIMPLEST
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unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
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#endif
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prev_heap = s_current_heap_end;
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#ifndef MG_HAL_SBRK_SIMPLEST
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// Check how much space we got from the heap end to the stack end
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if (s_current_heap_end + incr > heap_end) return (void *) -1;
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#endif
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s_current_heap_end += incr;
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return prev_heap;
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}
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#endif
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|
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int _open(const char *path) {
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(void) path;
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return -1;
|
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}
|
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int _close(int fd) {
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(void) fd;
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return -1;
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}
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int _isatty(int fd) {
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(void) fd;
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return 1;
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}
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int _lseek(int fd, int ptr, int dir) {
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||||
(void) fd, (void) ptr, (void) dir;
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return 0;
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}
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void _exit(int status) {
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(void) status;
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for (;;) asm volatile("BKPT #0");
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}
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|
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void _kill(int pid, int sig) {
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(void) pid, (void) sig;
|
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}
|
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|
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int _getpid(void) {
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return -1;
|
||||
}
|
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|
||||
int _write(int fd, char *ptr, int len) {
|
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(void) fd, (void) ptr, (void) len;
|
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if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
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return -1;
|
||||
}
|
||||
|
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int _read(int fd, char *ptr, int len) {
|
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(void) fd, (void) ptr, (void) len;
|
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return -1;
|
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}
|
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int _link(const char *a, const char *b) {
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(void) a, (void) b;
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return -1;
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}
|
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|
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int _unlink(const char *a) {
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(void) a;
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return -1;
|
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}
|
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int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _init(void) {
|
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}
|
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#endif // __GNUC__
|
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@@ -0,0 +1,446 @@
|
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// Copyright (c) 2022-2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// RM0399
|
||||
// https://www.st.com/resource/en/reference_manual/rm0399-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
|
||||
// https://www.st.com/resource/en/datasheet/stm32h747xi.pdf
|
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// https://docs.arduino.cc/hardware/portenta-h7/
|
||||
|
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#pragma once
|
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|
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#define LED1 PIN('K', 5) // On-board LED pin (red)
|
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#define LED2 PIN('K', 6) // On-board LED pin (green)
|
||||
#define LED3 PIN('K', 7) // On-board LED pin (blue)
|
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#define LED LED2 // Use green LED for blinking
|
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|
||||
#ifndef UART_DEBUG
|
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#define UART_DEBUG USART1
|
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#endif
|
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|
||||
#include <stm32h747xx.h>
|
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|
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#include <stdbool.h>
|
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#include <stdint.h>
|
||||
#include <stdio.h>
|
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#include <string.h>
|
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|
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#define BIT(x) (1UL << (x))
|
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#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
|
||||
#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
|
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#define PINNO(pin) (pin & 255)
|
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#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
void hal_init(void);
|
||||
size_t hal_ram_free(void);
|
||||
size_t hal_ram_used(void);
|
||||
|
||||
// System clock (2.1, Fig 1; 8.5, Fig 45; 8.5.5, Fig 47; 8.5.6, Fig 49)
|
||||
// - This board defaults to work with an SMPS regulator, so:
|
||||
// - SYS_FREQUENCY <= 400 MHz; hclk = SYS_FREQUENCY / HPRE ; hclk <= 200 MHz;
|
||||
// APB clocks <= 100 MHz.
|
||||
// - D1 domain bus matrix (and so flash) runs at hclk frequency. Configure flash
|
||||
// latency (WS) in accordance to hclk freq (4.3.8, Table 17)
|
||||
// - The Ethernet controller is in D2 domain and runs at hclk frequency
|
||||
enum {
|
||||
D1CPRE = 1, // actual divisor value
|
||||
HPRE = 2, // actual divisor value
|
||||
D1PPRE = 4, // register values, divisor value = BIT(value - 3) = / 2
|
||||
D2PPRE1 = 4,
|
||||
D2PPRE2 = 4,
|
||||
D3PPRE = 4
|
||||
};
|
||||
// PLL1_P: odd division factors are not allowed (8.7.13) (according to Cube, '1'
|
||||
// is also an "odd division factor").
|
||||
// Make sure your chip is revision 'V', otherwise set PLL1_N = 400
|
||||
enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 400, PLL1_P = 2 , PLL1_Q = 4 };
|
||||
#define SYS_FREQUENCY ((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / D1CPRE) * 1000000)
|
||||
// #define SYS_FREQUENCY ((PLL1_HSI / D1CPRE) * 1000000)
|
||||
// #define SYS_FREQUENCY 64000000
|
||||
#define AHB_FREQUENCY (SYS_FREQUENCY / HPRE)
|
||||
#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(D2PPRE2 - 3)))
|
||||
#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(D2PPRE1 - 3)))
|
||||
#define PLL1_Q_FREQUENCY ((PLL1_HSI * PLL1_N / PLL1_M / PLL1_Q) * 1000000)
|
||||
|
||||
static inline void spin(volatile uint32_t n) {
|
||||
while (n--) (void) 0;
|
||||
}
|
||||
|
||||
enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
|
||||
enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
|
||||
enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
|
||||
enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
|
||||
|
||||
#define GPIO(N) ((GPIO_TypeDef *) (0x40000000 + 0x18020000UL + 0x400 * (N)))
|
||||
|
||||
static GPIO_TypeDef *gpio_bank(uint16_t pin) {
|
||||
return GPIO(PINBANK(pin));
|
||||
}
|
||||
static inline void gpio_toggle(uint16_t pin) {
|
||||
GPIO_TypeDef *gpio = gpio_bank(pin);
|
||||
uint32_t mask = BIT(PINNO(pin));
|
||||
gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
|
||||
}
|
||||
static inline int gpio_read(uint16_t pin) {
|
||||
return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
|
||||
}
|
||||
static inline void gpio_write(uint16_t pin, bool val) {
|
||||
GPIO_TypeDef *gpio = gpio_bank(pin);
|
||||
gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
|
||||
}
|
||||
static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
uint8_t speed, uint8_t pull, uint8_t af) {
|
||||
GPIO_TypeDef *gpio = gpio_bank(pin);
|
||||
uint8_t n = (uint8_t) (PINNO(pin));
|
||||
RCC->AHB4ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
|
||||
CLRSET(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
|
||||
CLRSET(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
|
||||
CLRSET(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
|
||||
CLRSET(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
|
||||
((uint32_t) af) << ((n & 7) * 4));
|
||||
CLRSET(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
|
||||
}
|
||||
static inline void gpio_input(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_NONE, 0);
|
||||
}
|
||||
static inline void gpio_output(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
|
||||
GPIO_PULL_NONE, 0);
|
||||
}
|
||||
|
||||
static inline void leds_init(void) {
|
||||
gpio_output(LED1); // Initialise LED1
|
||||
gpio_output(LED2); // Initialise LED2
|
||||
gpio_output(LED3); // Initialise LED3
|
||||
gpio_write(LED1, true); // OFF
|
||||
gpio_write(LED2, true);
|
||||
gpio_write(LED3, true);
|
||||
}
|
||||
|
||||
// D2 Kernel clock (8.7.21) USART1 defaults to pclk2 (APB2), while USART2,3
|
||||
// default to pclk1 (APB1). Even if using other kernel clocks, the APBx clocks
|
||||
// must be enabled for CPU access, as the kernel clock drives the BRR, not the
|
||||
// APB bus interface
|
||||
static inline void uart_init(USART_TypeDef *uart, unsigned long baud) {
|
||||
uint8_t af = 7; // Alternate function
|
||||
uint16_t rx = 0, tx = 0; // pins
|
||||
uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
|
||||
|
||||
if (uart == USART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
|
||||
if (uart == USART2) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(17);
|
||||
if (uart == USART3) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(18);
|
||||
|
||||
if (uart == USART1) tx = PIN('A', 9), rx = PIN('A', 10);
|
||||
if (uart == USART2) tx = PIN('A', 2), rx = PIN('A', 3);
|
||||
if (uart == USART3) tx = PIN('D', 8), rx = PIN('D', 9);
|
||||
|
||||
#if 1 // CONSTANT BAUD RATE FOR DEBUGGING
|
||||
CLRSET(RCC->D2CCIP2R, 7 << 3, 3 << 3); // use HSI for UART1
|
||||
freq = 64000000;
|
||||
#endif
|
||||
|
||||
gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
|
||||
gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
|
||||
uart->CR1 = 0; // Disable this UART
|
||||
uart->BRR = freq / baud; // Set baud rate
|
||||
uart->CR1 = BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
|
||||
}
|
||||
static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
|
||||
uart->TDR = byte;
|
||||
while ((uart->ISR & BIT(7)) == 0) spin(1);
|
||||
}
|
||||
static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int uart_read_ready(USART_TypeDef *uart) {
|
||||
return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
|
||||
}
|
||||
static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
|
||||
return (uint8_t) (uart->RDR & 255);
|
||||
}
|
||||
|
||||
static inline void rng_init(void) {
|
||||
RCC->D2CCIP2R |= RCC_D2CCIP2R_RNGSEL_0; // RNG clock source pll1_q_ck
|
||||
RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; // Enable RNG clock
|
||||
RNG->CR = RNG_CR_RNGEN; // Enable RNG
|
||||
}
|
||||
|
||||
static inline uint32_t rng_read(void) {
|
||||
while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
|
||||
return RNG->DR;
|
||||
}
|
||||
|
||||
// NO Hw pull-ups on PHY RXD0,1,DV; set them to enable autonegotiation
|
||||
static inline void ethernet_init(void) {
|
||||
// Initialise Ethernet. Enable MAC GPIO pins, see schematics
|
||||
uint16_t pins1[] = {PIN('A', 7), PIN('C', 4), PIN('C', 5)};
|
||||
for (size_t i = 0; i < sizeof(pins1) / sizeof(pins1[0]); i++) {
|
||||
gpio_init(pins1[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
|
||||
GPIO_PULL_UP, 11); // 11 is the Ethernet function
|
||||
}
|
||||
uint16_t pins2[] = {PIN('A', 1), PIN('A', 2), PIN('C', 1),
|
||||
PIN('G', 11), PIN('G', 12), PIN('G', 13)};
|
||||
for (size_t i = 0; i < sizeof(pins2) / sizeof(pins2[0]); i++) {
|
||||
gpio_init(pins2[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
|
||||
GPIO_PULL_NONE, 11); // 11 is the Ethernet function
|
||||
}
|
||||
NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
|
||||
CLRSET(SYSCFG->PMCR, 7 << 21, 4 << 21); // Use RMII (13.3.1)
|
||||
RCC->AHB1ENR |= BIT(15) | BIT(16) | BIT(17); // Enable Ethernet clocks
|
||||
}
|
||||
|
||||
static inline char chiprev(void) {
|
||||
uint16_t rev = (uint16_t) (((uint32_t) DBGMCU->IDCODE) >> 16);
|
||||
if (rev == 0x1003) return 'Y';
|
||||
if (rev == 0x2003) return 'V';
|
||||
return '?';
|
||||
}
|
||||
|
||||
static inline unsigned int div2prescval(unsigned int div) {
|
||||
// 0 --> /1; 8 --> /2 ... 11 --> /16; 12 --> /64 ... 15 --> /512
|
||||
if (div == 1) return 0;
|
||||
if (div > 16) div /= 2;
|
||||
unsigned int val = 7;
|
||||
while (div >>= 1) ++val;
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned int pllrge(unsigned int f) {
|
||||
unsigned int val = 0;
|
||||
while (f >>= 1) ++val;
|
||||
return val - 1;
|
||||
}
|
||||
|
||||
static inline void clock_init(void) {
|
||||
// Set flash latency. RM section 4.9.1, section 4.3.8 table 16
|
||||
CLRSET(FLASH->ACR, (FLASH_ACR_WRHIGHFREQ_Msk | FLASH_ACR_LATENCY_Msk),
|
||||
FLASH_ACR_LATENCY_2WS | FLASH_ACR_WRHIGHFREQ_1);
|
||||
CLRSET(PWR->CR3, BIT(1), BIT(2)); // select SMPS
|
||||
while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
|
||||
PWR->D3CR |= BIT(15) | BIT(14); // Select VOS1
|
||||
uint32_t f = PWR->D3CR; // fake read to wait for bus clocking
|
||||
while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
|
||||
#if 0
|
||||
SYSCFG->PWRCR |= BIT(0); // ODEN for LDO to go 480MHz
|
||||
f = SYSCFG->PWRCR;
|
||||
while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
|
||||
#endif
|
||||
(void) f;
|
||||
RCC->CFGR &= ~(3 << 0); // Set clock source to HSI (bootloader...)
|
||||
RCC->CR &= ~BIT(24); // Disable PLL1
|
||||
CLRSET(
|
||||
RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0),
|
||||
(div2prescval(D1CPRE) << 8) | (D1PPRE << 4) | (div2prescval(HPRE) << 0));
|
||||
RCC->D2CFGR = (D2PPRE2 << 8) | (D2PPRE1 << 4);
|
||||
RCC->D3CFGR = (D3PPRE << 4);
|
||||
// DIVQ1EN DIVP1EN PLL1RGE !PLL1VCOSEL !PLL1FRACEN
|
||||
CLRSET(RCC->PLLCFGR, (3 << 2) | BIT(1) | BIT(0),
|
||||
BIT(17) | BIT(16) | pllrge(PLL1_HSI / PLL1_M) << 2);
|
||||
CLRSET(RCC->PLL1DIVR, (0x7F << 16) | (0x7F << 9) | (0x1FF << 0),
|
||||
((PLL1_Q - 1) << 16) | ((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0));
|
||||
CLRSET(RCC->PLLCKSELR, (0x3F << 4) | (3 << 0), PLL1_M << 4); // PLL1: HSI/M
|
||||
RCC->CR |= BIT(24); // Enable PLL1
|
||||
while ((RCC->CR & BIT(25)) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR |= (3 << 0); // Set clock source to PLL1
|
||||
while ((RCC->CFGR & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
|
||||
RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; // Enable SYSCFG
|
||||
}
|
||||
|
||||
static inline void system_init(void) { // Called automatically by startup code
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
SCB_DisableDCache(); // The bootloader enables caches, disable them
|
||||
SCB_DisableICache();
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
#define PWRPIN PIN('J', 1)
|
||||
|
||||
// - 58.4 Table 473
|
||||
// - 58.5.8 AHB bw >= 3x SDMMC bus bw; Table 492; SD HS => AHB >= ~20MHz
|
||||
// - SDIO 2.0 section 3.1
|
||||
static inline void sdmmc_set_ds(void) { // NO FLOW CONTROL ??? REALLY ??? *******************************
|
||||
CLRSET(SDMMC1->CLKCR, (1 << 17) | 0x3ff, (1 << 14) | ((PLL1_Q_FREQUENCY / (2 * 25000000)) & 0x3ff)); // 4-bit bus, 25MHz
|
||||
}
|
||||
static inline void sdmmc_set_hs(void) { // mbed enables flow control... AIROC does not
|
||||
CLRSET(SDMMC1->CLKCR, 0x3ff, (1 << 17) | (1 << 14) | ((PLL1_Q_FREQUENCY / (2 * 50000000)) & 0x3ff)); // hw flow control, 4-bit bus, 50MHz
|
||||
}
|
||||
static inline void sdmmc_init(void) {
|
||||
RCC->AHB3RSTR |= BIT(16); // Reset SDIO block
|
||||
RCC->AHB3RSTR &= ~BIT(16);
|
||||
RCC->D1CCIPR &= ~BIT(16); // 9.7.18, use PLL1Q
|
||||
RCC->AHB3ENR |= BIT(16); // Enable SDIO clock
|
||||
// Initialise SDIO pins, see schematics
|
||||
uint16_t pins[] = {PIN('C', 8), PIN('C', 9), PIN('C', 10),
|
||||
PIN('C', 11), PIN('C', 12), PIN('D', 2)};
|
||||
for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
|
||||
// Portenta H7 doesn't pull-up the SDIO bus
|
||||
gpio_init(pins[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
|
||||
GPIO_PULL_UP, 12); // 12 is the SDMMC1 (SDIO) function
|
||||
}
|
||||
gpio_input(PIN('J', 5)); // wake, ignored
|
||||
// 1-bit bus, rising edge, clock always on, no flow control, 400KHz
|
||||
SDMMC1->CLKCR = (PLL1_Q_FREQUENCY / (2 * 400000)) & 0x3ff;
|
||||
SDMMC1->POWER |= 3 << 0; // SDMMC_POWER_PWRCTRL
|
||||
SDMMC1->DCTRL = BIT(10); // Read Wait control by stopping SDMMCCLK
|
||||
// wait 74 clocks (~200us) before accessing the "card"
|
||||
}
|
||||
|
||||
static inline bool sdmmc_transact(uint8_t cmd, uint32_t arg, uint32_t *resp) {
|
||||
unsigned int wresp = (resp != NULL) ? 1 : 0; // 58.10.4: 2-bit; cmds used
|
||||
uint32_t cmdr = BIT(12) | (wresp << 8) | ((cmd & 0x3f) << 0); // CPSMEN
|
||||
SDMMC1->ARG = arg;
|
||||
CLRSET(SDMMC1->CMD, 0x00011f3f /* CMDSUSPEND CPSMEN WAITPEND WAITINT WAITRESP CMD */, cmdr);
|
||||
if (wresp == 0) {
|
||||
while ((SDMMC1->STA & SDMMC_STA_CMDSENT) == 0) spin(1);
|
||||
SDMMC1->ICR = 0x002000C5; // BUSYD0END CMDSENT CMDREND CTIMEOUT CCRCFAIL
|
||||
return true;
|
||||
}
|
||||
//while ((SDMMC1->STA & 0x00200045 /*BUSYD0END CMDREND CTIMEOUT CCRCFAIL*/) == 0 || SDMMC1->STA & SDMMC_STA_CPSMACT) spin(1);
|
||||
while (SDMMC1->STA & SDMMC_STA_CPSMACT) spin(1);
|
||||
bool res = (SDMMC1->STA & 0x00200005 /*BUSYD0END CTIMEOUT CCRCFAIL*/) == 0;
|
||||
SDMMC1->ICR = 0x002000C5; // BUSYD0END CMDSENT CMDREND CTIMEOUT CCRCFAIL
|
||||
*resp = SDMMC1->RESP1;
|
||||
if (!res || SDMMC1->RESPCMD != cmd) return false;
|
||||
return true;
|
||||
}
|
||||
|
||||
static inline unsigned int _log2(uint16_t x) {
|
||||
unsigned int i = 0;
|
||||
while (x != 0) x = ((uint16_t)x) >> 1, ++i;
|
||||
return i - 1;
|
||||
}
|
||||
|
||||
static inline bool sdmmc_transfer(bool write, uint32_t arg, uint16_t blksz, uint32_t *data, uint32_t length, uint32_t *resp) {
|
||||
uint32_t cmdr = BIT(12) | (1 << 8) | (53 << 0); // CPSMEN WRESP CMD=53
|
||||
bool bmode = (blksz != 0);
|
||||
uint8_t dblksz = bmode ? (uint8_t)_log2(blksz) : 0;
|
||||
uint32_t dctrlr = (dblksz << 4) | (bmode ? (0 << 2) : (1 << 2)) | (write ? 0 : BIT(1)); // DBLOCKSIZE=f(blksz) DTMODE=f(bmode) DTDIR=!write !DTEN
|
||||
SDMMC1->DCTRL = SDMMC_DCTRL_RWMOD;
|
||||
SDMMC1->IDMACTRL = SDMMC_IDMA_IDMAEN; // single buffer
|
||||
SDMMC1->IDMABASE0 = (uint32_t)data;
|
||||
SDMMC1->DTIMER = (uint32_t) 50000000; // 58.10.7, set for 1 sec @50MHz (2 secs @25MHz)
|
||||
SDMMC1->DLEN = length; // 58.10.8 call with a multiple of blksz (we do)
|
||||
CLRSET(SDMMC1->DCTRL, 0xff /* DBLOCKSIZE DTMODE DTDIR DTEN */, dctrlr);
|
||||
SDMMC1->CMD = SDMMC_CMD_CMDTRANS; // CPSM will perform a data transfer
|
||||
SDMMC1->ARG = arg;
|
||||
SDMMC1->CMD |= cmdr; // other flags cleared above
|
||||
while ((SDMMC1->STA & 0x0020003f) == 0 && SDMMC1->STA & SDMMC_STA_DPSMACT)
|
||||
spin(1); // incorrect "card" usage will stall here
|
||||
bool res = (SDMMC1->STA & 0x0020003f /* BUSYD0END RXOVERR TXUNDERR DTIMEOUT CTIMEOUT DCRCFAIL CCRCFAIL */) == 0;
|
||||
SDMMC1->CMD = 0;
|
||||
SDMMC1->DLEN = 0;
|
||||
SDMMC1->IDMACTRL = 0;
|
||||
SDMMC1->ICR = (uint32_t) ~0; // clear all flags
|
||||
*resp = SDMMC1->RESP1;
|
||||
SDMMC1->DCTRL = SDMMC_DCTRL_RWMOD;
|
||||
if (!res || SDMMC1->RESPCMD != 53) return false;
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
// Bit-banged SPI, pin wiring does not allow using a hw SPI peripheral
|
||||
#define CYWSPI NULL
|
||||
#define BBSPI_SPIN 1
|
||||
|
||||
static inline void spi_init(void *spi, uint8_t div) {
|
||||
// Initialise bit-banged SPI, see: schematics; CYW DS 4.1.1 Table 5, 13.7
|
||||
// Table 22
|
||||
gpio_input(PIN('C', 8)); // DO -> MISO
|
||||
gpio_input(PIN('C', 9)); // IRQ -> ignore
|
||||
gpio_output(PIN('C', 10)); // D2 <-- strap for SPI mode
|
||||
gpio_output(PIN('C', 11)); // CS
|
||||
gpio_output(PIN('C', 12)); // SCLK
|
||||
gpio_output(PIN('D', 2)); // DI -> MOSI
|
||||
// select SPI mode at power-on/reset time (not WL_REG_ON, actual POR)
|
||||
// "Sampling occurs a few milliseconds after an internal POR
|
||||
// or deassertion of the external POR
|
||||
gpio_write(PIN('C', 10), 0);
|
||||
gpio_write(PIN('D', 2), 0); // idle values
|
||||
gpio_write(PIN('C', 12), 0);
|
||||
gpio_write(PIN('C', 11), 0); // no power at startup
|
||||
(void) spi;
|
||||
(void) div;
|
||||
}
|
||||
|
||||
static inline void spi_write_byte(void *spi, uint8_t byte) {
|
||||
unsigned int n = 8;
|
||||
while (n--) {
|
||||
gpio_write(PIN('D', 2), byte & 0x80);
|
||||
spin(BBSPI_SPIN);
|
||||
gpio_write(PIN('C', 12), 1);
|
||||
byte <<= 1;
|
||||
spin(BBSPI_SPIN);
|
||||
gpio_write(PIN('C', 12), 0);
|
||||
}
|
||||
gpio_write(PIN('D', 2), 0);
|
||||
(void) spi;
|
||||
}
|
||||
|
||||
static inline uint8_t spi_read_byte(void *spi) {
|
||||
uint8_t byte = 0;
|
||||
unsigned int n = 8;
|
||||
while (n--) {
|
||||
byte <<= 1;
|
||||
spin(BBSPI_SPIN);
|
||||
byte |= gpio_read(PIN('C', 8)) ? 1 : 0;
|
||||
gpio_write(PIN('C', 12), 1);
|
||||
spin(BBSPI_SPIN);
|
||||
gpio_write(PIN('C', 12), 0);
|
||||
}
|
||||
(void) spi;
|
||||
return byte;
|
||||
}
|
||||
|
||||
static inline void spi_select(void *spi, bool s) {
|
||||
gpio_write(PIN('C', 11), !s);
|
||||
(void) spi;
|
||||
}
|
||||
|
||||
// Current bootloader sets all outputs in the PMIC, no need to use I2C.
|
||||
// The bootloader inits I2C1 and chips in there, but we change MCU clock
|
||||
// DS 4 Table 12, schematic PB6,7
|
||||
static inline void i2c_init(I2C_TypeDef *i2c) {
|
||||
CLRSET(RCC->D2CCIP2R, 3 << 12, 2 << 12); // use HSI for I2C1 (64MHz)
|
||||
RCC->APB1LENR |= BIT(21); // enable I2C clock
|
||||
gpio_init(PIN('B', 6), GPIO_MODE_AF, GPIO_OTYPE_OPEN_DRAIN, GPIO_SPEED_INSANE,
|
||||
GPIO_PULL_NONE, 4);
|
||||
gpio_init(PIN('B', 7), GPIO_MODE_AF, GPIO_OTYPE_OPEN_DRAIN, GPIO_SPEED_INSANE,
|
||||
GPIO_PULL_NONE, 4);
|
||||
i2c->CR1 = 0; // disable before any config change
|
||||
i2c->CR1 = BIT(12); // 50.7 disable filters
|
||||
i2c->TIMINGR = 10U << 28 | 3 << 20 | 2 << 16 | 3 << 8 | 9 << 0; // < 400KHz
|
||||
i2c->CR1 |= BIT(0); // enable after fully configured
|
||||
}
|
||||
|
||||
static inline void i2c_write_reg(I2C_TypeDef *i2c, uint8_t addr, uint8_t reg,
|
||||
uint8_t byte) {
|
||||
i2c->CR2 = BIT(25) | 2 << 16 |
|
||||
addr << 1; // write byte to reg in chip at addr, AUTOEND
|
||||
i2c->CR2 |= BIT(13); // START
|
||||
while ((i2c->ISR & BIT(0)) == 0) spin(1); // TXE
|
||||
i2c->TXDR = reg;
|
||||
while ((i2c->ISR & BIT(0)) == 0) spin(1); // TXE
|
||||
i2c->TXDR = byte;
|
||||
while ((i2c->ISR & BIT(5)) == 0) spin(1); // STOPF
|
||||
i2c->ICR |= BIT(5); // STOPCF, clear STOPF
|
||||
}
|
||||
|
||||
static inline uint8_t i2c_read_reg(I2C_TypeDef *i2c, uint8_t addr,
|
||||
uint8_t reg) {
|
||||
i2c->CR2 = 1 << 16 | addr << 1; // write reg addr to chip at addr
|
||||
i2c->CR2 |= BIT(13); // START
|
||||
while ((i2c->ISR & BIT(0)) == 0) spin(1); // TXE
|
||||
i2c->TXDR = reg;
|
||||
while ((i2c->ISR & BIT(6)) == 0) spin(1); // TC
|
||||
i2c->CR2 = BIT(13) | BIT(10) | 1 << 16 | addr << 1; // read 1 byte, AUTOEND
|
||||
i2c->CR2 |= BIT(25); // START
|
||||
while ((i2c->ISR & BIT(2)) == 0) spin(1); // RXNE
|
||||
uint8_t byte = (uint8_t) i2c->RXDR;
|
||||
while ((i2c->ISR & BIT(5)) == 0) spin(1); // STOPF
|
||||
i2c->ICR |= BIT(5); // STOPCF, clear STOPF
|
||||
return byte;
|
||||
}
|
||||
@@ -0,0 +1,33 @@
|
||||
/* DTCMRAM (rwx) : ORIGIN = 0x20000400, LENGTH = 128k - 1k */ /* bootloader starts at 0x20000000 */
|
||||
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash(rx) : ORIGIN = 0x08040000, LENGTH = 2048k - 0x40000 /* bootloader starts at 0x08000000 */
|
||||
sram(rwx) : ORIGIN = 0x24000000, LENGTH = 512k
|
||||
}
|
||||
_estack = ORIGIN(sram) + LENGTH(sram); /* stack points to end of SRAM */
|
||||
|
||||
SECTIONS {
|
||||
.vectors : { KEEP(*(.isr_vector)) } > flash
|
||||
.text : { *(.text* .text.*) } > flash
|
||||
.rodata : { *(.rodata*) } > flash
|
||||
|
||||
.data : {
|
||||
_sdata = .;
|
||||
*(.first_data)
|
||||
*(.data SORT(.data.*))
|
||||
*(.iram .iram* .iram.*)
|
||||
_edata = .;
|
||||
} > sram AT > flash
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : {
|
||||
_sbss = .;
|
||||
*(.bss SORT(.bss.*) COMMON)
|
||||
_ebss = .;
|
||||
} > sram
|
||||
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,176 @@
|
||||
// Copyright (c) 2025 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "mongoose.h"
|
||||
#include "hal.h"
|
||||
|
||||
|
||||
#define WIFI_SSID "YOUR_WIFI_NETWORK_NAME" // SET THIS!
|
||||
#define WIFI_PASS "YOUR_WIFI_PASSWORD" // SET THIS!
|
||||
|
||||
|
||||
static void hwspecific_sdio_init(void) {
|
||||
gpio_output(PWRPIN);
|
||||
gpio_write(PWRPIN, 0);
|
||||
mg_delayms(100);
|
||||
sdmmc_init();
|
||||
mg_delayms(1);
|
||||
gpio_write(PWRPIN, 1);
|
||||
mg_delayms(50);
|
||||
}
|
||||
|
||||
void hwspecific_sdio_config(void *sdio, uint8_t cfg) {
|
||||
(void) sdio;
|
||||
if (cfg == 0) return sdmmc_set_ds();
|
||||
if (cfg == 1) return sdmmc_set_hs();
|
||||
}
|
||||
bool hwspecific_sdio_txn(void *sdio, uint8_t cmd, uint32_t arg, uint32_t *resp) {
|
||||
(void) sdio;
|
||||
return sdmmc_transact(cmd, arg, resp);
|
||||
}
|
||||
bool hwspecific_sdio_xfr(void *sdio, bool write, uint32_t arg, uint16_t blksz, uint32_t *data, uint32_t len, uint32_t *resp){
|
||||
(void) sdio;
|
||||
return sdmmc_transfer(write, arg, blksz, data, len, resp);
|
||||
}
|
||||
|
||||
static const struct mg_tcpip_sdio sdio = {NULL, hwspecific_sdio_config, hwspecific_sdio_txn, hwspecific_sdio_xfr};
|
||||
|
||||
// clang-format off
|
||||
typedef enum {RESOURCE_IN_MEMORY,RESOURCE_IN_EXTERNAL_STORAGE} resource_location_t;
|
||||
typedef struct {resource_location_t l;unsigned long sz;union{struct {unsigned long o;const char *f;}fs;struct {const char *m;}mem;}val;} resource_hnd_t;
|
||||
#include "mbed/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_bin.c"
|
||||
#include "mbed/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/resources/firmware/COMPONENT_4343W_FS/4343WA1_clm_blob.c"
|
||||
#include "mbed/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/resources/nvram/wifi_nvram_image.h"
|
||||
// clang-format on
|
||||
static const struct mg_tcpip_driver_cyw_firmware fw = {
|
||||
(const uint8_t *)wifi_firmware_image_data, (size_t)sizeof(wifi_firmware_image_data),
|
||||
(const uint8_t *)wifi_nvram_image, (size_t)sizeof(wifi_nvram_image),
|
||||
(const uint8_t *)wifi_firmware_clm_blob_image_data, (size_t)sizeof(wifi_firmware_clm_blob_image_data)};
|
||||
|
||||
// mif user states
|
||||
enum {AP, SCANNING, STOPPING_AP, CONNECTING, READY};
|
||||
static unsigned int state;
|
||||
static uint32_t s_ip, s_mask;
|
||||
|
||||
|
||||
static void mif_fn(struct mg_tcpip_if *ifp, int ev, void *ev_data) {
|
||||
// TODO(): should we include this inside ifp ? add an fn_data ?
|
||||
if (ev == MG_TCPIP_EV_ST_CHG) {
|
||||
MG_INFO(("State change: %u", *(uint8_t *) ev_data));
|
||||
}
|
||||
switch(state) {
|
||||
case AP: // we are in AP mode, wait for a user connection to trigger a scan or a connection to a network
|
||||
if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_UP) {
|
||||
MG_INFO(("Access Point started"));
|
||||
s_ip = ifp->ip, ifp->ip = MG_IPV4(192, 168, 169, 1);
|
||||
s_mask = ifp->mask, ifp->mask = MG_IPV4(255, 255, 255, 0);
|
||||
ifp->enable_dhcp_client = false;
|
||||
ifp->enable_dhcp_server = true;
|
||||
} else if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_READY) {
|
||||
MG_INFO(("Access Point READY !"));
|
||||
|
||||
// simulate user request to scan for networks
|
||||
bool res = mg_wifi_scan();
|
||||
MG_INFO(("Starting scan: %s", res ? "OK":"FAIL"));
|
||||
if (res) state = SCANNING;
|
||||
}
|
||||
break;
|
||||
case SCANNING:
|
||||
if (ev == MG_TCPIP_EV_WIFI_SCAN_RESULT) {
|
||||
struct mg_wifi_scan_bss_data *bss = (struct mg_wifi_scan_bss_data *) ev_data;
|
||||
MG_INFO(("BSS: %.*s (%u) (%M) %d dBm %u", bss->SSID.len, bss->SSID.buf, bss->channel, mg_print_mac, bss->BSSID, (int) bss->RSSI, bss->security));
|
||||
} else if (ev == MG_TCPIP_EV_WIFI_SCAN_END) {
|
||||
// struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
|
||||
MG_INFO(("Wi-Fi scan finished"));
|
||||
|
||||
// simulate user selection of a network (1/2: stop AP)
|
||||
bool res = mg_wifi_ap_stop();
|
||||
MG_INFO(("Manually stopping AP: %s", res ? "OK":"FAIL"));
|
||||
if (res) state = STOPPING_AP;
|
||||
// else we have a hw/fw problem
|
||||
}
|
||||
break;
|
||||
case STOPPING_AP:
|
||||
if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_DOWN) {
|
||||
struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
|
||||
d->apmode = false;
|
||||
|
||||
// simulate user selection of a network (2/2: actual connect)
|
||||
bool res = mg_wifi_connect(d->ssid, d->pass);
|
||||
MG_INFO(("Manually connecting: %s", res ? "OK":"FAIL"));
|
||||
if (res) {
|
||||
state = CONNECTING;
|
||||
ifp->ip = s_ip;
|
||||
ifp->mask = s_mask;
|
||||
if (ifp->ip == 0) ifp->enable_dhcp_client = true;
|
||||
ifp->enable_dhcp_server = false;
|
||||
} // else manually start AP as below
|
||||
}
|
||||
break;
|
||||
case CONNECTING:
|
||||
if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_READY) {
|
||||
MG_INFO(("READY!"));
|
||||
state = READY;
|
||||
|
||||
// simulate user code disconnection and go back to AP mode (1/2: disconnect)
|
||||
bool res = mg_wifi_disconnect();
|
||||
MG_INFO(("Manually disconnecting: %s", res ? "OK":"FAIL"));
|
||||
} else if (ev == MG_TCPIP_EV_WIFI_CONNECT_ERR) {
|
||||
MG_ERROR(("Wi-Fi connect failed"));
|
||||
// manually start AP as below
|
||||
}
|
||||
break;
|
||||
case READY:
|
||||
// go back to AP mode after a disconnection (simulation 2/2), you could retry
|
||||
if (ev == MG_TCPIP_EV_ST_CHG && *(uint8_t *) ev_data == MG_TCPIP_STATE_DOWN) {
|
||||
struct mg_tcpip_driver_cyw_data *d = (struct mg_tcpip_driver_cyw_data *) ifp->driver_data;
|
||||
bool res = mg_wifi_ap_start(d->apssid, d->appass, d->apchannel);
|
||||
MG_INFO(("Disconnected"));
|
||||
MG_INFO(("Manually starting AP: %s", res ? "OK":"FAIL"));
|
||||
if (res) {
|
||||
state = AP;
|
||||
d->apmode = true;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static struct mg_tcpip_driver_cyw_data d = {
|
||||
(void *)&sdio, (struct mg_tcpip_driver_cyw_firmware *)&fw, WIFI_SSID, WIFI_PASS, "mongoose", "mongoose", 0, 0, 10, true, false};
|
||||
|
||||
int main(void) {
|
||||
hal_init();
|
||||
|
||||
hwspecific_sdio_init();
|
||||
|
||||
state = d.apmode ? AP : CONNECTING;
|
||||
|
||||
struct mg_mgr mgr; // Initialise Mongoose event manager
|
||||
mg_mgr_init(&mgr); // and attach it to the interface
|
||||
mg_log_set(MG_LL_DEBUG); // Set log level
|
||||
|
||||
// Initialise Mongoose network stack
|
||||
// Either set use_dhcp or enter a static config.
|
||||
// For static configuration, specify IP/mask/GW in network byte order
|
||||
struct mg_tcpip_if mif = {
|
||||
.ip = 0,
|
||||
.driver = (struct mg_tcpip_driver *)&mg_tcpip_driver_cyw,
|
||||
.driver_data = (struct mg_tcpip_driver_cyw_data*)&d,
|
||||
.fn = mif_fn,
|
||||
// .recv_queue.size = 8192
|
||||
};
|
||||
|
||||
mg_tcpip_init(&mgr, &mif);
|
||||
MG_INFO(("Init done, starting main loop"));
|
||||
|
||||
MG_INFO(("Initialising application..."));
|
||||
|
||||
MG_INFO(("Starting event loop"));
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1 @@
|
||||
../../../mongoose.c
|
||||
@@ -0,0 +1 @@
|
||||
../../../mongoose.h
|
||||
@@ -0,0 +1,13 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_NEWLIB
|
||||
#define MG_TLS MG_TLS_BUILTIN
|
||||
#define MG_OTA MG_OTA_STM32H7_DUAL_CORE
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_PACKED_FS 1
|
||||
#define MG_ENABLE_DRIVER_CYW_SDIO 1
|
||||
#define MG_ENABLE_TCPIP_DRIVER_INIT 0
|
||||
Reference in new issue
Block a user