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Add MG_OTA_{ROLLBACK,STATE_SET,STATE_GET}

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cpq committed 2026-05-31 11:02:38 +01:00
1 parent a6452f5311
commit 67f249c58a
16 files changed
+345 -131
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tutorials/stm32/nucleo-h563zi/minimal/Makefile
+1 -1
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@@ -12,7 +12,7 @@ SOURCES = main.c hal.c
SOURCES += cmsis_h5/Source/Templates/gcc/startup_stm32h563xx.s
SOURCES += mongoose/mongoose.c
all build example: firmware.bin
all build example: firmware.signed.bin
mongoose/mongoose.c mongoose/mongoose.h:
cp ../../../../mongoose.[ch] mongoose/
tutorials/stm32/nucleo-h563zi/minimal/hal.h
+22 -6
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@@ -126,7 +126,7 @@ static inline bool hal_uart_init(USART_TypeDef *uart, uint16_t tx_pin,
}
static inline void hal_uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
uart->TDR = byte;
while ((uart->ISR & BIT(7)) == 0) spin(1);
while ((uart->ISR & USART_ISR_TXE_TXFNF) == 0) (void) 0;
}
static inline void hal_uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
while (len-- > 0) hal_uart_write_byte(uart, *(uint8_t *) buf++);
@@ -144,7 +144,7 @@ static inline void hal_rng_init(void) {
RNG->CR |= RNG_CR_RNGEN; // Enable RNG
}
static inline uint32_t hal_rng_read(void) {
while ((RNG->SR & RNG_SR_DRDY) == 0) spin(1);
while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
return RNG->DR;
}
@@ -181,7 +181,23 @@ static inline void hal_system_init(void) {
__ISB();
}
// Enable TAMP/RTC APB clock, backup domain write access, and RTC/TAMP kernel
// clock (LSI). Idempotent: skips RTC init if already enabled after a reset.
// Must be called before accessing TAMP backup registers or IWDG.
static inline void hal_backup_domain_init(void) {
RCC->APB3ENR |= RCC_APB3ENR_RTCAPBEN; // enable TAMP/RTC APB clock
PWR->DBPCR |= PWR_DBPCR_DBP; // enable backup domain write access
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { // init only once (not warm reset)
RCC->BDCR |= RCC_BDCR_LSION; // enable LSI
while ((RCC->BDCR & RCC_BDCR_LSIRDY) == 0) (void) 0; // wait ready
RCC->BDCR |= (2U << RCC_BDCR_RTCSEL_Pos); // LSI as clock source
RCC->BDCR |= RCC_BDCR_RTCEN; // enable RTC/TAMP clock
}
}
static inline void hal_clock_init(void) {
hal_backup_domain_init();
// Set flash latency. RM0481, section 7.11.1, section 7.3.4 table 37
CLRSET(FLASH->ACR, (FLASH_ACR_WRHIGHFREQ_Msk | FLASH_ACR_LATENCY_Msk),
FLASH_ACR_LATENCY_5WS | FLASH_ACR_WRHIGHFREQ_1);
@@ -192,10 +208,10 @@ static inline void hal_clock_init(void) {
PWR->VOSCR = PWR_VOSCR_VOS_1; // Select VOS1
}
uint32_t f = PWR->VOSCR; // fake read to wait for bus clocking
while ((PWR->VOSSR & PWR_VOSSR_ACTVOSRDY) == 0) spin(1);
while ((PWR->VOSSR & PWR_VOSSR_ACTVOSRDY) == 0) (void) 0;
(void) f;
RCC->CR = RCC_CR_HSION; // Clear HSI clock divisor
while ((RCC->CR & RCC_CR_HSIRDY) == 0) spin(1); // Wait until done
while ((RCC->CR & RCC_CR_HSIRDY) == 0) (void) 0; // Wait until done
RCC->CFGR2 = (HAL_PPRE3 << 12) | (HAL_PPRE2 << 8) | (HAL_PPRE1 << 4) | (HAL_HPRE << 0);
RCC->PLL1DIVR =
((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0); // Set PLL1_P PLL1_N
@@ -204,9 +220,9 @@ static inline void hal_clock_init(void) {
RCC->PLL1CFGR =
RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1PEN | (PLL1_M << 8) | (1 << 0);
RCC->CR |= RCC_CR_PLL1ON; // Enable PLL1
while ((RCC->CR & RCC_CR_PLL1RDY) == 0) spin(1); // Wait until done
while ((RCC->CR & RCC_CR_PLL1RDY) == 0) (void) 0; // Wait until done
RCC->CFGR1 |= (3 << 0); // Set clock source to PLL1
while ((RCC->CFGR1 & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
while ((RCC->CFGR1 & (7 << 3)) != (3 << 3)) (void) 0; // Wait until done
SystemCoreClock = SYS_FREQUENCY;
}
tutorials/stm32/nucleo-h563zi/minimal/main.c
+25 -2
View File
@@ -43,17 +43,36 @@ bool mg_random(void *buf, size_t len) {
}
static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) {
if (ev == MG_EV_HTTP_MSG) { // New HTTP request received
if (ev == MG_EV_HTTP_HDRS) {
struct mg_http_message *hm = (struct mg_http_message *) ev_data;
// Start OTA on headers so body chunks stream directly to flash (no RAM buffer)
if (mg_match(hm->uri, mg_str("/api/ota/update"), NULL)) {
mg_http_start_ota(c, hm, NULL);
}
} else if (ev == MG_EV_HTTP_MSG) {
struct mg_http_message *hm = (struct mg_http_message *) ev_data;
if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) {
mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), hal_get_tick());
} else if (mg_match(hm->uri, mg_str("/api/ota/commit"), NULL)) {
c->data[0] = 1;
mg_http_reply(c, 200, "", "ok\n");
} else if (mg_match(hm->uri, mg_str("/api/ota/rollback"), NULL)) {
c->data[0] = 2;
mg_http_reply(c, 200, "", "ok\n");
} else {
mg_http_reply(c, 200, "", "Hi from Mongoose, tick %llu\n", hal_get_tick());
}
} else if (ev == MG_EV_CLOSE && c->data[0] == 1) {
MG_OTA_STATE_SET(MG_OTA_CONFIRMED);
NVIC_SystemReset();
} else if (ev == MG_EV_CLOSE && c->data[0] == 2) {
MG_OTA_STATE_SET(MG_OTA_CONFIRMED);
MG_OTA_ROLLBACK();
}
}
int main(void) {
hal_clock_init();
hal_uart_init(UART_DEBUG, UART_DEBUG_TX_PIN, UART_DEBUG_RX_PIN, 115200);
hal_rng_init();
hal_gpio_output(LED_1);
@@ -62,7 +81,11 @@ int main(void) {
hal_ethernet_init();
// Start a minimal web server
MG_INFO(("Initialised. CPU clock: %lu MHz", SystemCoreClock / 1000000));
// Max delay 131 seconds
MG_OTA_BOOT_CHECK(30);
struct mg_mgr mgr;
mg_mgr_init(&mgr);
mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL);
tutorials/stm32/nucleo-h563zi/minimal/mongoose/mongoose_config.h
+31 -21
View File
@@ -1,4 +1,5 @@
#pragma once
#include "hal.h"
// See https://mongoose.ws/documentation/#build-options
#define MG_ARCH MG_ARCH_ARMGCC
@@ -12,16 +13,34 @@
#define MG_ENABLE_PACKED_FS 1
#define MG_ENABLE_DRIVER_STM32H 1
#define MG_OTA_PUBLIC_KEY { \
0x19, 0x7f, 0xed, 0x81, 0x8b, 0xb7, 0xb2, 0xa5, \
0xde, 0xe0, 0xde, 0x04, 0x83, 0x60, 0xc8, 0x69, \
0x61, 0x39, 0x30, 0x1f, 0xc1, 0x52, 0x11, 0x4b, \
0xb7, 0xa4, 0xd7, 0x52, 0x03, 0x36, 0xc6, 0xc1, \
0xbf, 0x22, 0x75, 0x04, 0x49, 0xf8, 0x46, 0x47, \
0xec, 0x20, 0xd6, 0x8d, 0x48, 0x29, 0x7d, 0x63, \
0xb3, 0xf7, 0x1f, 0x58, 0x44, 0x82, 0xcc, 0x7a, \
0x4b, 0x5e, 0x68, 0x98, 0x24, 0x1f, 0x86, 0xf4, \
}
#define MG_OTA_PUBLIC_KEY \
{ \
0x19, 0x7f, 0xed, 0x81, 0x8b, 0xb7, 0xb2, 0xa5, 0xde, 0xe0, 0xde, \
0x04, 0x83, 0x60, 0xc8, 0x69, 0x61, 0x39, 0x30, 0x1f, 0xc1, 0x52, \
0x11, 0x4b, 0xb7, 0xa4, 0xd7, 0x52, 0x03, 0x36, 0xc6, 0xc1, 0xbf, \
0x22, 0x75, 0x04, 0x49, 0xf8, 0x46, 0x47, 0xec, 0x20, 0xd6, 0x8d, \
0x48, 0x29, 0x7d, 0x63, 0xb3, 0xf7, 0x1f, 0x58, 0x44, 0x82, 0xcc, \
0x7a, 0x4b, 0x5e, 0x68, 0x98, 0x24, 0x1f, 0x86, 0xf4, \
}
// OTA rollback timer via IWDG. PR=8 → /1024 on H563 (RM0481 §52.4.2).
// Max timeout: 4095 * 1024 / 32000 = 131 s. PVU/RVU must clear before
// writing RLR/starting, otherwise the write is ignored (RM0481 §52.4.3).
#define MG_OTA_ROLLBACK_TIMER_START(seconds) \
do { \
IWDG->KR = 0x5555U; /* unlock */ \
IWDG->PR = 8U; /* /1024 */ \
while (IWDG->SR & IWDG_SR_PVU) (void) 0; /* wait PVU */ \
IWDG->RLR = (uint32_t) ((seconds) * 32000 / 1024); \
while (IWDG->SR & IWDG_SR_RVU) (void) 0; /* wait RVU */ \
IWDG->KR = 0xCCCCU; /* start */ \
IWDG->KR = 0xAAAAU; /* reload RLR */ \
} while (0)
// OTA state in TAMP backup register 0 (survives all resets, clears on POR).
// Requires hal_backup_domain_init() (called from hal_clock_init) to have run.
#define MG_OTA_STATE_GET() (TAMP->BKP0R)
#define MG_OTA_STATE_SET(v) (TAMP->BKP0R = (uint32_t) (v))
// #define MG_DRIVER_MDC_CR 4 // RMII MDC clock divider, from 0 to 4
// #define MG_TCPIP_PHY_ADDR 0 // PHY address
@@ -33,17 +52,8 @@
// #define MG_TCPIP_GW MG_IPV4(192, 168, 0, 1)
// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0)
// Set custom MAC address. By default, it is randomly generated
// Using a build-time constant:
// #define MG_SET_MAC_ADDRESS(mac) do { mac[0] = 2; mac[1] = 3; mac[2] = 4; mac[3] = 5; mac[4] = 6; mac[5] = 7; } while (0)
//
// Using custom function:
// extern void my_function(unsigned char *mac);
// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)
// Construct MAC address from the MCU unique ID. It is defined in the
// ST CMSIS header as UID_BASE
#define MGUID ((uint32_t *) 0x08fff800) // Unique 96-bit chip ID
// Construct MAC address from the MCU unique ID
#define MGUID ((uint32_t *) UID_BASE)
#define MG_SET_MAC_ADDRESS(mac) \
do { \
mac[0] = 2; \