mirror of
https://github.com/cesanta/mongoose.git
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Add L2 PPP and PPPoE
This commit is contained in:
Sergio R. Caprile committed
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ae5a2263ac
commit
70650fedcf
23 files changed
+2019
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@@ -106,14 +106,14 @@ void setup() {
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mg_log_set(MG_LL_DEBUG); // Set debug log level
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mg_log_set_fn([](char c, void *) { Serial.print(c); }, NULL); // Log serial
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mif.driver = &mg_tcpip_driver_ppp; // Initialise built-in TCP/IP stack
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mif.driver_data = &driver_data; // with the cellular driver
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mif.driver = &mg_tcpip_driver_atcmd; // Initialise built-in TCP/IP stack
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mif.l2type = MG_TCPIP_L2_PPP; // with the cellular driver
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mif.driver_data = &driver_data;
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driver_data.script = script;
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driver_data.reset = [](void *) { digitalWrite(RST_PIN, LOW); delay(1); digitalWrite(RST_PIN, HIGH); },
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driver_data.tx = [](void *, uint8_t c) { ModemSerial.write(c); },
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driver_data.rx = [](void *) { return ModemSerial.available() ? ModemSerial.read() : -1; },
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mg_tcpip_init(&mgr, &mif);
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mif.enable_dhcp_client = false;
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}
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void loop() {
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@@ -0,0 +1,37 @@
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CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
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CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
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CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
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CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_f7/Include
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CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 $(CFLAGS_EXTRA)
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LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
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SOURCES = main.c syscalls.c sysinit.c
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SOURCES += cmsis_f7/Source/Templates/gcc/startup_stm32f746xx.s # ST startup file. Compiler-dependent!
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# Mongoose options are defined in mongoose_config.h
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SOURCES += mongoose.c
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ifeq ($(OS),Windows_NT)
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RM = cmd /C del /Q /F /S
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else
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RM = rm -rf
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endif
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all build example: firmware.bin
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firmware.bin: firmware.elf
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arm-none-eabi-objcopy -O binary $< $@
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firmware.elf: cmsis_core cmsis_f7 $(SOURCES) hal.h link.ld
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arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
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flash: firmware.bin
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st-flash --reset write $< 0x8000000
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cmsis_core: # ARM CMSIS core headers
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git clone --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
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cmsis_f7: # ST CMSIS headers for STM32F7 series
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git clone --depth 1 -b v1.2.8 https://github.com/STMicroelectronics/cmsis_device_f7 $@
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clean:
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$(RM) firmware.* cmsis_core cmsis_f7
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@@ -0,0 +1,87 @@
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# PPPoE on NUCLEO-F746ZG
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This example shows a device with a very simple web server (the NUCLEO board) that connects to a PPPoE server. The device web server can then be accessed from the computer running the web server. For more complete scenarios, proper server setting and routing would be needed, thing a network admin will do.
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## Configure and start your PPPoE server
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This is just a test example in Linux, we use _pppoe-server_ for this, as it is easy to configure and serves our purpose. For production scenarios, ask your network admin.
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```sh
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$ cat /etc/ppp/pppoe-server-options
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# PPP options for the PPPoE server
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# LIC: GPL
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#require-pap
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#login
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lcp-echo-interval 10
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lcp-echo-failure 2
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$ sudo pppoe-server -F -I yourethernetinterface
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```
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## Flash your NUCLEO
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```sh
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$ make
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$ make flash
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```
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## Check and test
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```sh
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$ ifconfig ppp0
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ppp0: flags=4305<UP,POINTOPOINT,RUNNING,NOARP,MULTICAST> mtu 1492
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inet 10.0.0.1 netmask 255.255.255.255 destination 10.67.15.1
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ppp txqueuelen 3 (Point-to-Point Protocol)
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RX packets 3 bytes 36 (36.0 B)
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RX errors 0 dropped 0 overruns 0 frame 0
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TX packets 28 bytes 7003 (6.8 KiB)
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TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
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$ route
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Kernel IP routing table
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Destination Gateway Genmask Flags Metric Ref Use Iface
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default _gateway 0.0.0.0 UG 0 0 0 virbr0
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10.67.15.1 0.0.0.0 255.255.255.255 UH 0 0 0 ppp0
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$ curl http://10.67.15.1/
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hi
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$
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```
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```sh
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$ minicom -D /dev/ttyACM0
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```
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```text
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0 3 mongoose.c:5306:mg_mgr_init MG_IO_SIZE: 512, TLS: builtin
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6 2 main.c:48:main Init TCP/IP stack ...
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b 3 mongoose.c:27645:guess_mdc_cr HCLK: 216000000, CR: 4
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11 2 mongoose.c:25494:mg_phy_init PHY ID: 0x07 0xc131 (LAN87x)
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18 3 mongoose.c:5223:mg_listen 1 0 tcp://0.0.0.0:80
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1d 2 main.c:57:main Init done, starting main loop ...
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7e7 3 mongoose.c:27757:mg_tcpip_driv Link is 100M full-duplex
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7ec 3 mongoose.c:4035:mg_l2_pppoe_po Sent PADI
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7f1 1 mongoose.c:7220:mg_tcpip_poll Network is down
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7f6 3 mongoose.c:4083:mg_l2_pppoe_rx Sent PADR
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7fa 3 mongoose.c:4088:mg_l2_pppoe_rx PPPoE session 0x0001 started
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bcf 3 mongoose.c:27757:mg_tcpip_driv Link is 100M full-duplex
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bd4 1 mongoose.c:7220:mg_tcpip_poll Network is down
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c0d 3 mongoose.c:3821:ppp_handle_lcp LCP config request of 14 bytes, rejecting...
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c15 3 mongoose.c:3815:ppp_handle_lcp LCP config request of 4 bytes, acknowledging...
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c1e 3 mongoose.c:3836:ppp_handle_lcp LCP echo request of 8 bytes, replying...
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c26 3 mongoose.c:3943:ppp_rx unknown 40-byte PPP frame with proto 0x80fd:
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0000 80 fd 01 01 00 0f 1a 04 78 00 18 04 78 00 15 03 ........x...x...
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0010 2f 00 00 00 00 00 /.....
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c3a 3 mongoose.c:3874:ppp_handle_ipc IPCP ack, GW IP: 10.0.0.1
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c40 3 mongoose.c:3897:ppp_handle_ipc IPCP ack, IP: 10.67.15.1
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fb7 2 mongoose.c:5712:onstatechange READY, IP: 10.67.15.1
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fbc 2 mongoose.c:5713:onstatechange GW: 10.0.0.1
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fc1 2 mongoose.c:5715:onstatechange MAC: 02:35:42:56:22:2e
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33d3 3 mongoose.c:3836:ppp_handle_lcp LCP echo request of 8 bytes, replying...
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5b8b 3 mongoose.c:3836:ppp_handle_lcp LCP echo request of 8 bytes, replying...
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8348 3 mongoose.c:3836:ppp_handle_lcp LCP echo request of 8 bytes, replying...
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aafa 3 mongoose.c:3836:ppp_handle_lcp LCP echo request of 8 bytes, replying...
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d2b7 3 mongoose.c:3836:ppp_handle_lcp LCP echo request of 8 bytes, replying...
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fa74 3 mongoose.c:3836:ppp_handle_lcp LCP echo request of 8 bytes, replying...
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12196 3 mongoose.c:6583:accept_conn 2 accepted 10.0.0.1:50846
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1219d 3 mongoose.c:5159:mg_close_conn 2 0 closed
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```
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@@ -0,0 +1,175 @@
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// Copyright (c) 2022 Cesanta Software Limited
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// All rights reserved
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// https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
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#pragma once
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#include <stm32f746xx.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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#define LED1 PIN('B', 0) // On-board LED pin (green)
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#define LED2 PIN('B', 7) // On-board LED pin (blue)
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#define LED3 PIN('B', 14) // On-board LED pin (red)
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#define LED LED2 // Use blue LED for blinking
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/* System clock
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5.3.3: APB1 clock <= 54MHz; APB2 clock <= 108MHz
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3.3.2, Table 5: configure flash latency (WS) in accordance to clock freq
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38.4: The AHB clock frequency must be at least 25 MHz when the Ethernet
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controller is used */
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enum { APB1_PRE = 5 /* AHB clock / 4 */, APB2_PRE = 4 /* AHB clock / 2 */ };
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enum { PLL_HSI = 16, PLL_M = 8, PLL_N = 216, PLL_P = 2, PLL_Q = 9 };
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#define FLASH_LATENCY 7
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#define SYS_FREQUENCY ((PLL_HSI * PLL_N / PLL_M / PLL_P) * 1000000) // Core 216 MHz, USB 48 MHz
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#define APB2_FREQUENCY (SYS_FREQUENCY / (BIT(APB2_PRE - 3)))
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#define APB1_FREQUENCY (SYS_FREQUENCY / (BIT(APB1_PRE - 3)))
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static inline void spin(volatile uint32_t count) {
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while (count--) (void) 0;
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}
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
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enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
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#define GPIO(N) ((GPIO_TypeDef *) (0x40020000 + 0x400 * (N)))
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static GPIO_TypeDef *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
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static inline void gpio_toggle(uint16_t pin) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
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}
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static inline int gpio_read(uint16_t pin) {
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return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
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}
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static inline void gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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GPIO_TypeDef *gpio = gpio_bank(pin);
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uint8_t n = (uint8_t) (PINNO(pin));
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RCC->AHB1ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
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SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
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SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
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SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
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SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
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}
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static inline void gpio_input(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void gpio_output(uint16_t pin) {
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gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
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GPIO_PULL_NONE, 0);
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}
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static inline void irq_exti_attach(uint16_t pin) {
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uint8_t bank = (uint8_t) (PINBANK(pin)), n = (uint8_t) (PINNO(pin));
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SYSCFG->EXTICR[n / 4] &= ~(15UL << ((n % 4) * 4));
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SYSCFG->EXTICR[n / 4] |= (uint32_t) (bank << ((n % 4) * 4));
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EXTI->IMR |= BIT(n);
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EXTI->RTSR |= BIT(n);
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EXTI->FTSR |= BIT(n);
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int irqvec = n < 5 ? 6 + n : n < 10 ? 23 : 40; // IRQ vector index, 10.1.2
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NVIC_SetPriority(irqvec, 3);
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NVIC_EnableIRQ(irqvec);
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}
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#ifndef UART_DEBUG
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#define UART_DEBUG USART3
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#endif
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static inline void uart_init(USART_TypeDef *uart, unsigned long baud) {
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// https://www.st.com/resource/en/datasheet/stm32f746zg.pdf
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uint8_t af = 7; // Alternate function
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uint16_t rx = 0, tx = 0; // pins
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uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
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if (uart == USART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
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if (uart == USART2) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(17);
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if (uart == USART3) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(18);
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if (uart == USART1) tx = PIN('A', 9), rx = PIN('A', 10);
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if (uart == USART2) tx = PIN('A', 2), rx = PIN('A', 3);
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if (uart == USART3) tx = PIN('D', 8), rx = PIN('D', 9);
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gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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uart->CR1 = 0; // Disable this UART
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uart->BRR = freq / baud; // Set baud rate
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uart->CR1 |= BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
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}
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static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
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uart->TDR = byte;
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while ((uart->ISR & BIT(7)) == 0) spin(1);
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}
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static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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static inline int uart_read_ready(USART_TypeDef *uart) {
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return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
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}
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static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
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return (uint8_t) (uart->RDR & 255);
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}
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static inline void rng_init(void) {
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RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;
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RNG->CR |= RNG_CR_RNGEN;
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}
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static inline uint32_t rng_read(void) {
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while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
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return RNG->DR;
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}
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// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
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static inline void ethernet_init(void) {
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// Initialise Ethernet. Enable MAC GPIO pins, see
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// https://www.farnell.com/datasheets/2014265.pdf section 6.10
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uint16_t pins[] = {
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PIN('A', 1), /* ETH_REF_CLK */ \
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PIN('A', 2), /* ETH_MDIO */ \
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PIN('A', 7), /* ETH_CRS_DV */ \
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PIN('B', 13), /* ETH_TXD1 */ \
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PIN('C', 1), /* ETH_MDC */ \
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PIN('C', 4), /* ETH_RXD0 */ \
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PIN('C', 5), /* ETH_RXD1 */ \
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PIN('G', 11), /* ETH_TX_EN */ \
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PIN('G', 13) /* ETH_TXD0 */
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};
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for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
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gpio_init(pins[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
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GPIO_PULL_NONE, 11); // 11 is the Ethernet function
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}
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NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
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SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL; // Use RMII. Goes first!
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RCC->AHB1ENR |=
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RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | RCC_AHB1ENR_ETHMACRXEN;
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}
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#define UUID ((uint8_t *) UID_BASE) // Unique 96-bit chip ID. TRM 41.1
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// Helper macro for MAC generation
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#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
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{ \
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2, UUID[0] ^ UUID[1], UUID[2] ^ UUID[3], UUID[4] ^ UUID[5], \
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UUID[6] ^ UUID[7] ^ UUID[8], UUID[9] ^ UUID[10] ^ UUID[11] \
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}
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@@ -0,0 +1,29 @@
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ENTRY(Reset_Handler);
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MEMORY {
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flash(rx) : ORIGIN = 0x08000000, LENGTH = 1024k
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sram(rwx) : ORIGIN = 0x20000000, LENGTH = 320k
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}
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_estack = ORIGIN(sram) + LENGTH(sram); /* stack points to end of SRAM */
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SECTIONS {
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.vectors : { KEEP(*(.isr_vector)) } > flash
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.text : { *(.text* .text.*) } > flash
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.rodata : { *(.rodata*) } > flash
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.data : {
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_sdata = .; /* for init_ram() */
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*(.first_data)
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*(.data SORT(.data.*))
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_edata = .; /* for init_ram() */
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} > sram AT > flash
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_sidata = LOADADDR(.data);
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.bss : {
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_sbss = .; /* for init_ram() */
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*(.bss SORT(.bss.*) COMMON)
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_ebss = .; /* for init_ram() */
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} > sram
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. = ALIGN(8);
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_end = .; /* for cmsis_gcc.h and init_ram() */
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}
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@@ -0,0 +1,63 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
#include "mongoose.h"
|
||||
|
||||
static void blink_cb(void *arg) { // Blink periodically
|
||||
gpio_toggle(LED);
|
||||
(void) arg;
|
||||
}
|
||||
|
||||
static volatile uint64_t s_ticks; // Milliseconds since boot
|
||||
void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
|
||||
s_ticks++;
|
||||
}
|
||||
|
||||
uint64_t mg_millis(void) { // Let Mongoose use our uptime function
|
||||
return s_ticks; // Return number of milliseconds since boot
|
||||
}
|
||||
|
||||
bool mg_random(void *buf, size_t len) { // Use on-board RNG
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
static void fn(struct mg_connection *c, int ev, void *ev_data) {
|
||||
if (ev == MG_EV_HTTP_MSG) {
|
||||
struct mg_http_message *hm = (struct mg_http_message *) ev_data;
|
||||
(void) hm;
|
||||
mg_http_reply(c, 200, "", "hi\n");
|
||||
}
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
gpio_output(LED); // Setup blue LED
|
||||
uart_init(UART_DEBUG, 115200); // Initialise debug printf
|
||||
ethernet_init();
|
||||
|
||||
struct mg_mgr mgr; // Initialise
|
||||
mg_mgr_init(&mgr); // Mongoose event manager
|
||||
mg_log_set(MG_LL_DEBUG); // Set log level
|
||||
|
||||
|
||||
MG_INFO(("Init TCP/IP stack ..."));
|
||||
struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(),
|
||||
.driver = &mg_tcpip_driver_stm32f,
|
||||
.l2type = MG_TCPIP_L2_PPPoE,
|
||||
.recv_queue.size = 4096};
|
||||
mg_tcpip_init(&mgr, &mif);
|
||||
mg_timer_add(&mgr, 500, MG_TIMER_REPEAT, blink_cb, &mgr);
|
||||
mg_http_listen(&mgr, "tcp://0.0.0.0:80", fn, &mgr);
|
||||
|
||||
MG_INFO(("Init done, starting main loop ..."));
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1 @@
|
||||
../../../mongoose.c
|
||||
@@ -0,0 +1 @@
|
||||
../../../mongoose.h
|
||||
@@ -0,0 +1,13 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_ARMGCC
|
||||
#define MG_TLS MG_TLS_BUILTIN
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_DRIVER_STM32F 1
|
||||
#define MG_ENABLE_TCPIP_DRIVER_INIT 0
|
||||
|
||||
|
||||
@@ -0,0 +1,88 @@
|
||||
#include <sys/stat.h>
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
int _fstat(int fd, struct stat *st) {
|
||||
if (fd < 0) return -1;
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
extern char _end;
|
||||
static unsigned char *heap = NULL;
|
||||
unsigned char *prev_heap;
|
||||
unsigned char x = 0, *heap_end = (unsigned char *)((size_t) &x - 512);
|
||||
(void) x;
|
||||
if (heap == NULL) heap = (unsigned char *) &_end;
|
||||
prev_heap = heap;
|
||||
if (heap + incr > heap_end) return (void *) -1;
|
||||
heap += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int mkdir(const char *path, mode_t mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _init(void) {}
|
||||
@@ -0,0 +1,30 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// This file contains essentials required by the CMSIS:
|
||||
// uint32_t SystemCoreClock - holds the system core clock value
|
||||
// SystemInit() - initialises the system, e.g. sets up clocks
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
uint32_t SystemCoreClock = SYS_FREQUENCY;
|
||||
|
||||
void SystemInit(void) { // Called automatically by startup code
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
asm("DSB");
|
||||
asm("ISB");
|
||||
FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch
|
||||
RCC->PLLCFGR &= ~((BIT(17) - 1) | (0xF << 24)); // Clear PLL multipliers
|
||||
RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P
|
||||
RCC->PLLCFGR |= PLL_M | (PLL_N << 6) | (PLL_Q << 24); // Set PLL_M _N _Q
|
||||
RCC->CR |= BIT(24); // Enable PLL
|
||||
while ((RCC->CR & BIT(25)) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR = (APB1_PRE << 10) | (APB2_PRE << 13); // Set prescalers
|
||||
RCC->CFGR |= 2; // Set clock source to PLL
|
||||
while ((RCC->CFGR & 12) == 0) spin(1); // Wait until done
|
||||
|
||||
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; // Enable SYSCFG
|
||||
rng_init(); // Initialise random number generator
|
||||
SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
|
||||
|
||||
}
|
||||
Reference in new issue
Block a user