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Make tests work on public repo as well
PUBLISHED_FROM=78acb18d597b6f47f31da13087fa6685f21ce445
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Dmitry Frank authored and Cesanta Bot committed
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@@ -0,0 +1,168 @@
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/*
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* Copyright (c) 2014-2017 Cesanta Software Limited
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* All rights reserved
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "FreeRTOS.h"
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#include "common/platform.h"
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#include "mgos_core_dump.h"
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#include "mgos_hal.h"
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struct arm_exc_frame {
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uint32_t r0;
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uint32_t r1;
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uint32_t r2;
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uint32_t r3;
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uint32_t r12;
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uint32_t lr;
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uint32_t pc;
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uint32_t xpsr;
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#ifdef ARM_HAVE_FPU
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uint32_t s[16];
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uint32_t fpscr;
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uint32_t reserved;
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#endif
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} __attribute__((packed));
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struct arm_gdb_reg_file {
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uint32_t r[13];
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uint32_t sp;
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uint32_t lr;
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uint32_t pc;
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uint32_t cpsr;
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uint64_t d[16];
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uint32_t fpscr;
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} __attribute__((packed));
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#if ARM_HAVE_FPU
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static void save_s16_s31(uint32_t *dst) {
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__asm volatile(
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"\
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vmov r1, s16\n str r1, [%0, 0]\n\
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vmov r1, s17\n str r1, [%0, 4]\n\
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vmov r1, s18\n str r1, [%0, 8]\n\
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vmov r1, s19\n str r1, [%0, 12]\n\
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vmov r1, s20\n str r1, [%0, 16]\n\
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vmov r1, s21\n str r1, [%0, 20]\n\
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vmov r1, s22\n str r1, [%0, 24]\n\
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vmov r1, s23\n str r1, [%0, 28]\n\
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vmov r1, s24\n str r1, [%0, 32]\n\
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vmov r1, s25\n str r1, [%0, 36]\n\
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vmov r1, s26\n str r1, [%0, 40]\n\
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vmov r1, s27\n str r1, [%0, 44]\n\
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vmov r1, s28\n str r1, [%0, 48]\n\
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vmov r1, s29\n str r1, [%0, 52]\n\
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vmov r1, s30\n str r1, [%0, 56]\n\
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vmov r1, s31\n str r1, [%0, 60]\n\
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"
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:
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: "r"(dst)
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: "r1");
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}
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static void print_fpu_regs(const uint32_t *regs, int off, int n) {
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for (int i = 0, j = off; i < n; i++, j++) {
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if (j % 4 == 0) mgos_cd_putc('\n');
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mgos_cd_printf(" S%d: %s0x%08lx", j, (j < 10 ? " " : ""), regs[i]);
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}
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}
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#endif
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void arm_exc_handler_bottom(uint8_t isr_no, struct arm_exc_frame *ef,
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struct arm_gdb_reg_file *rf) {
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char buf[8];
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const char *name;
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portDISABLE_INTERRUPTS();
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switch (isr_no) {
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case 0:
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name = "ThreadMode";
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break;
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case 1:
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case 7:
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case 8:
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case 9:
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case 10:
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case 13:
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name = "Reserved";
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break;
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case 2:
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name = "NMI";
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break;
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case 3:
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name = "HardFault";
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break;
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case 4:
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name = "MemManage";
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break;
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case 5:
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name = "BusFault";
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break;
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case 6:
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name = "UsageFault";
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break;
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case 11:
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name = "SVCall";
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break;
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case 12:
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name = "ReservedDebug";
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break;
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case 14:
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name = "PendSV";
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break;
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case 15:
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name = "SysTick";
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break;
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default: {
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sprintf(buf, "IRQ%u", isr_no - 16);
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name = buf;
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}
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}
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mgos_cd_printf("\n\n--- Exception %u (%s) ---\n", isr_no, name);
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if (rf != NULL) {
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mgos_cd_printf(" R0: 0x%08lx R1: 0x%08lx R2: 0x%08lx R3: 0x%08lx\n",
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rf->r[0], rf->r[1], rf->r[2], rf->r[3]);
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mgos_cd_printf(" R4: 0x%08lx R5: 0x%08lx R6: 0x%08lx R7: 0x%08lx\n",
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rf->r[4], rf->r[5], rf->r[6], rf->r[7]);
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mgos_cd_printf(" R8: 0x%08lx R9: 0x%08lx R10: 0x%08lx R11: 0x%08lx\n",
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rf->r[8], rf->r[9], rf->r[10], rf->r[11]);
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mgos_cd_printf(" R12: 0x%08lx SP: 0x%08lx LR: 0x%08lx PC: 0x%08lx\n",
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rf->r[12], rf->sp, rf->lr, rf->pc);
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mgos_cd_printf(" PSR: 0x%08lx\n", rf->cpsr);
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}
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memset(rf->d, 0, sizeof(rf->d));
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#if ARM_HAVE_FPU
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rf->fpscr = ef->fpscr;
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memcpy((uint8_t *) rf->d, ef->s, sizeof(ef->s));
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print_fpu_regs((uint32_t *) rf->d, 0, ARRAY_SIZE(ef->s));
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save_s16_s31(ef->s);
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memcpy(((uint8_t *) rf->d) + sizeof(ef->s), ef->s, sizeof(ef->s));
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print_fpu_regs((uint32_t *) (((uint8_t *) rf->d) + sizeof(ef->s)), 16,
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ARRAY_SIZE(ef->s));
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mgos_cd_putc('\n');
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mgos_cd_printf("FPSCR: 0x%08lx\n", rf->fpscr);
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#else
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rf->fpscr = 0;
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#endif
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mgos_cd_emit_header();
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mgos_cd_emit_section(MGOS_CORE_DUMP_SECTION_REGS, rf, sizeof(*rf));
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mgos_cd_emit_section("SRAM", (void *) SRAM_BASE_ADDR, SRAM_SIZE);
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mgos_cd_emit_footer();
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#ifdef MGOS_HALT_ON_EXCEPTION
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mgos_cd_printf("Halting\n");
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while (1) {
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mgos_wdt_feed();
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}
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#else
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mgos_cd_printf("Rebooting\n");
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mgos_dev_system_restart();
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#endif
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}
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@@ -0,0 +1,69 @@
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/*
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* Copyright (c) 2014-2017 Cesanta Software Limited
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* All rights reserved
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*/
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.arch armv7e-m
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.syntax unified
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.thumb
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/* These are required to satisfy TI linker. */
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.eabi_attribute Tag_ABI_align_needed, 1
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.eabi_attribute Tag_ABI_align_preserved, 1
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.global arm_exc_handler_top
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.global arm_exc_handler_bottom
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/*
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* Determines the stack pointer, populates most of the GDB frame
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* and hands off to the C routine.
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*/
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.section .text.arm_exc_handler_top
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.type arm_exc_handler_top, %function
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.align 8
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arm_exc_handler_top:
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tst lr, #4
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ite eq
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mrseq r1, msp
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mrsne r1, psp
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// r1 -> arm_exc_frame prepared for us by the CPU
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#if ARM_HAVE_FPU
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add r0, r1, #104 // sizeof(arm_exc_frame)
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sub sp, #328 // sizeof(arm_gdb_reg_file)
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#else
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add r0, r1, #32 // sizeof(arm_exc_frame)
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sub sp, #328 // sizeof(arm_gdb_reg_file)
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#endif
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mov r2, sp
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// r0 -> original sp, r2 -> arm_gdb_reg_file to fill
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// r3 - scratch
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ldr r3, [r1, #0] // r0
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str r3, [r2, #0]
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ldr r3, [r1, #4] // r2
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str r3, [r2, #4]
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ldr r3, [r1, #8] // r1
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str r3, [r2, #8]
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ldr r3, [r1, #12] // r3
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str r3, [r2, #12]
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str r4, [r2, #16] // r4
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str r5, [r2, #20] // r5
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str r6, [r2, #24] // r6
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str r7, [r2, #28] // r7
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str r8, [r2, #32] // r8
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str r9, [r2, #36] // r9
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str r10, [r2, #40] // r10
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str r11, [r2, #44] // r11
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ldr r3, [r1, #16] // r12
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str r3, [r2, #48]
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str r0, [r2, #52] // sp
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ldr r3, [r1, #20] // lr
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str r3, [r2, #56]
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ldr r3, [r1, #24] // pc
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str r3, [r2, #60]
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ldr r3, [r1, #28] // xpsr
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str r3, [r2, #64]
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mrs r0, ipsr
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b arm_exc_handler_bottom
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.size arm_exc_handler_top, . - arm_exc_handler_top
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