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Revamp rp examples
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@@ -0,0 +1,18 @@
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cmake_minimum_required(VERSION 3.13)
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# If you will set board type here, do it BEFORE including the SDK
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# set(PICO_BOARD pico2)
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include(pico_sdk_import.cmake)
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project(firmware)
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pico_sdk_init()
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add_executable(firmware main.c driver_rp2040_rmii.c mongoose/mongoose.c)
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target_include_directories(firmware PRIVATE . mongoose)
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target_link_libraries(firmware hardware_pio hardware_dma pico_stdlib pico_rand)
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pico_add_extra_outputs(firmware) # create map/bin/hex file etc.
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pico_enable_stdio_usb(firmware 1) # Route stdio to USB
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# Prevent extreme optimization from breaking OTA
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target_compile_options(firmware PRIVATE -fno-tree-loop-distribute-patterns)
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@@ -0,0 +1,37 @@
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# Environment setup: https://mongoose.ws/docs/getting-started/build-environment/
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CWD ?= $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
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SDK_PATH ?= $(CWD)/pico-sdk
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RM = rm -rf
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MKBUILD = test -d build || mkdir build
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ifeq ($(OS),Windows_NT)
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RM = cmd /C del /Q /F /S
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MKBUILD = if not exist build mkdir build
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endif
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.PHONY: build
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all build example: build/firmware.uf2
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build/firmware.uf2: pico_sdk_import.cmake mongoose/mongoose.c mongoose/mongoose.h
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pico_sdk_import.cmake: $(SDK_PATH)
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cp $(SDK_PATH)/external/$@ $@
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mongoose/mongoose.c mongoose/mongoose.h:
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cp ../../../$(notdir $@) $@
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build/firmware.uf2: $(SDK_PATH) $(wildcard *.[ch]) CMakeLists.txt Makefile
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$(MKBUILD)
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cd build && PICO_SDK_PATH=$(SDK_PATH) cmake -G "Unix Makefiles" .. && make
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flash: build/firmware.uf2
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picotool load $< -f
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clean:
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$(RM) build pico_sdk_import.cmake mongoose/mongoose.c mongoose/mongoose.h $(SDK_PATH)
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$(SDK_PATH):
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git clone -c advice.detachedHead=false --quiet --depth 1 -b 2.1.1 https://github.com/raspberrypi/pico-sdk $@
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cd $@ && git submodule update --quiet --init
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@@ -0,0 +1,28 @@
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# RP2040 / RP2350 Mongoose example
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This example can be built for both RP2040 and RP2350 targets.
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## Set target board
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By default, it builds for RP2040 target. If you want to change the target
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board, edit `CMakeKists.txt` and set the board, for example:
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```cmake
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set(PICO_BOARD pico2_w)
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```
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## Edit WiFi credentials
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For WiFi examples, edit `wifi.c` and set WiFi network name and password.
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## Build and run
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Make sure you have `picotool` installed. Then run:
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```sh
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make build flash
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```
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Start serial console to see the debug output.
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See detailed documentation at https://mongoose.ws/docs/guides/rp-tcpip-stack/
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@@ -0,0 +1,337 @@
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// Copyright (c) 2022 Cesanta Software Limited
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// All rights reserved
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include "hardware/dma.h"
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#include "hardware/pio.h"
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#include "pico/stdlib.h"
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#include "driver_rp2040_rmii.h"
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#include "mongoose.h"
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#define RXSM 0
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#define TXSM 1
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#define SMITXSM 2
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#define SMIRXSM 0 // pio1
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static uint smi_wr_addr, smi_rd_addr;
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static int dma_rx;
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static int dma_tx;
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static dma_channel_config dmacfg_rx;
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static dma_channel_config dmacfg_tx;
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// Max frame size with VLAN tag + CRC and excluding preamble
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#define ETH_PKT_SIZE 1522
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static uint8_t s_rxbuf[2][ETH_PKT_SIZE]; // ping-pong buffer
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static uint8_t s_txbuf[ETH_PKT_SIZE];
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static struct mg_tcpip_if *s_ifp; // MIP interface
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#define rmii_tx_wrap_target 0
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#define rmii_tx_wrap 7
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static const uint16_t rmii_tx_program_instructions[] = {
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// .wrap_target
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0xe000, // 0: set pins, 0 side 0
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0x80a0, // 1: pull block side 0
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0xe03d, // 2: set x, 29 side 0
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0xf101, // 3: set pins, 1 side 1 [1]
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0x1144, // 4: jmp x--, 4 side 1 [1]
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0xf103, // 5: set pins, 3 side 1 [1]
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0x7002, // 6: out pins, 2 side 1
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0x10e6, // 7: jmp !osre, 6 side 1
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// .wrap
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};
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static const struct pio_program rmii_tx_program = {
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.instructions = rmii_tx_program_instructions,
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.length = 8,
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.origin = -1,
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};
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static inline pio_sm_config rmii_tx_program_get_default_config(uint addr) {
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pio_sm_config c = pio_get_default_sm_config();
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sm_config_set_wrap(&c, addr + rmii_tx_wrap_target, addr + rmii_tx_wrap);
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sm_config_set_sideset(&c, 1, false, false);
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return c;
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}
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static inline void rmii_tx_init(PIO pio, uint sm, uint addr, uint gpio) {
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pio_sm_config c = rmii_tx_program_get_default_config(addr);
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pio_gpio_init(pio, gpio);
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pio_gpio_init(pio, gpio + 1);
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pio_gpio_init(pio, gpio + 2);
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sm_config_set_out_pins(&c, gpio, 2);
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sm_config_set_set_pins(&c, gpio, 2);
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sm_config_set_sideset_pins(&c, gpio + 2);
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pio_sm_set_consecutive_pindirs(pio, sm, gpio, 3, true);
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sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
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sm_config_set_out_shift(&c, true, true, 8); // pull bytes, LSB first, auto
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sm_config_set_clkdiv(&c,
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5); // Run at 50/5 = 10MHz (2x 2-bit nibble data rate)
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pio_sm_init(pio, sm, addr, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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#define rmii_rx_wrap_target 0
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#define rmii_rx_wrap 10
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static const uint16_t rmii_rx_program_instructions[] = {
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// .wrap_target
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0x2122, // 0: wait 0 pin, 2 [1]
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0x21a2, // 1: wait 1 pin, 2 [1]
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0x21a0, // 2: wait 1 pin, 0 [1]
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0x2121, // 3: wait 0 pin, 1 [1]
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0x21a1, // 4: wait 1 pin, 1 [1]
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0x4002, // 5: in pins, 2
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0x00c5, // 6: jmp pin, 5
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0x4002, // 7: in pins, 2
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0x00c5, // 8: jmp pin, 5
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0xa0c3, // 9: mov isr, null
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0xc020, // 10: irq wait 0
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// .wrap
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};
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static const struct pio_program rmii_rx_program = {
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.instructions = rmii_rx_program_instructions,
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.length = 11,
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.origin = -1,
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};
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static inline pio_sm_config rmii_rx_program_get_default_config(uint addr) {
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pio_sm_config c = pio_get_default_sm_config();
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sm_config_set_wrap(&c, addr + rmii_rx_wrap_target, addr + rmii_rx_wrap);
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return c;
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}
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static inline void rmii_rx_init(PIO pio, uint sm, uint addr, uint gpio) {
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pio_sm_config c = rmii_rx_program_get_default_config(addr);
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pio_gpio_init(pio, gpio);
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pio_gpio_init(pio, gpio + 1);
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pio_gpio_init(pio, gpio + 2);
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sm_config_set_in_pins(&c, gpio);
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pio_sm_set_consecutive_pindirs(pio, sm, gpio, 3, false);
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sm_config_set_jmp_pin(&c, gpio + 2);
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sm_config_set_in_shift(&c, true, true, 8); // push bytes, LSB first, auto
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sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
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sm_config_set_clkdiv(&c,
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5); // Run at 50/5 = 10MHz (2x 2-bit nibble data rate)
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pio_sm_init(pio, sm, addr, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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#define smi_wr_wrap_target 0
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#define smi_wr_wrap 4
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static const uint16_t smi_wr_program_instructions[] = {
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// .wrap_target
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0xe03f, // 0: set x, 31 side 0
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0xe101, // 1: set pins, 1 side 0 [1]
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0x1141, // 2: jmp x--, 1 side 1 [1]
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0x6101, // 3: out pins, 1 side 0 [1]
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0x1103, // 4: jmp 3 side 1 [1]
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// .wrap
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};
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static const struct pio_program smi_wr_program = {
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.instructions = smi_wr_program_instructions,
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.length = 5,
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.origin = -1,
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};
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static inline pio_sm_config smi_wr_program_get_default_config(uint addr) {
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pio_sm_config c = pio_get_default_sm_config();
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sm_config_set_wrap(&c, addr + smi_wr_wrap_target, addr + smi_wr_wrap);
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sm_config_set_sideset(&c, 1, false, false);
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return c;
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}
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#define smi_rd_wrap_target 13
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#define smi_rd_wrap 13
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static const uint16_t smi_rd_program_instructions[] = {
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0xe03f, // 0: set x, 31 side 0
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0xe101, // 1: set pins, 1 side 0 [1]
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0x1141, // 2: jmp x--, 1 side 1 [1]
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0xf02d, // 3: set x, 13 side 1
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0x6101, // 4: out pins, 1 side 0 [1]
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0x1144, // 5: jmp x--, 4 side 1 [1]
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0xe180, // 6: set pindirs, 0 side 0 [1]
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0xf101, // 7: set pins, 1 side 1 [1]
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0xa142, // 8: nop side 0 [1]
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0xf12f, // 9: set x, 15 side 1 [1]
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0xa042, // 10: nop side 0
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0x4001, // 11: in pins, 1 side 0
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0x114a, // 12: jmp x--, 10 side 1 [1]
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// .wrap_target
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0xf081, // 13: set pindirs, 1 side 1
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// .wrap
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};
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static const struct pio_program smi_rd_program = {
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.instructions = smi_rd_program_instructions,
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.length = 14,
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.origin = -1,
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};
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static inline pio_sm_config smi_rd_program_get_default_config(uint addr) {
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pio_sm_config c = pio_get_default_sm_config();
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sm_config_set_wrap(&c, addr + smi_rd_wrap_target, addr + smi_rd_wrap);
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sm_config_set_sideset(&c, 1, false, false);
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return c;
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}
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static inline void smi_wr_init(PIO pio, uint sm, uint addr, uint gpio) {
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pio_gpio_init(pio, gpio);
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pio_gpio_init(pio, gpio + 1);
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pio_sm_config c = smi_wr_program_get_default_config(addr);
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sm_config_set_out_pins(&c, gpio, 1);
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sm_config_set_set_pins(&c, gpio, 1);
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sm_config_set_sideset_pins(&c, gpio + 1);
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pio_sm_set_consecutive_pindirs(pio, sm, gpio, 2, true);
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sm_config_set_out_shift(&c, false, true,
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16); // pull half-words, MSB first, auto
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sm_config_set_clkdiv(&c, 6); // Run at 50/6 = <10MHz (4x data rate)
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pio_sm_init(pio, sm, addr, &c);
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}
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static inline void smi_rd_init(PIO pio, uint sm, uint addr, uint gpio) {
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pio_gpio_init(pio, gpio);
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pio_gpio_init(pio, gpio + 1);
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pio_sm_config c = smi_rd_program_get_default_config(addr);
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sm_config_set_in_pins(&c, gpio);
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sm_config_set_out_pins(&c, gpio, 1);
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sm_config_set_set_pins(&c, gpio, 1);
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sm_config_set_sideset_pins(&c, gpio + 1);
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pio_sm_set_consecutive_pindirs(pio, sm, gpio, 2, true);
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sm_config_set_out_shift(&c, false, true,
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16); // pull half-words, MSB first, auto
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sm_config_set_in_shift(&c, false, true,
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16); // push half-words, MSB first, auto
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sm_config_set_clkdiv(&c, 6); // Run at 50/6 = <10MHz (4x data rate)
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pio_sm_init(pio, sm, addr, &c);
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}
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static void eth_write_phy(int addr, int reg, int val, uint8_t gpio) {
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uint16_t op = 0x5002 | (addr << 7) | (reg << 2); // b0101aaaaarrrrr10
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smi_wr_init(pio0, SMITXSM, smi_wr_addr, gpio);
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pio_sm_put(pio0, SMITXSM, op << 16);
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pio_sm_put(pio0, SMITXSM, (uint16_t) val << 16);
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pio_sm_set_enabled(pio0, SMITXSM, true);
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}
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static uint16_t eth_read_phy(uint addr, uint reg, uint8_t gpio) {
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uint16_t op = 0x6000 | (addr << 7) | (reg << 2); // b0110aaaaarrrrr00
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smi_rd_init(pio1, SMIRXSM, smi_rd_addr, gpio);
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pio_sm_put(pio1, SMIRXSM, op << 16);
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pio_sm_set_enabled(pio1, SMIRXSM, true);
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uint16_t val = (uint16_t) pio_sm_get_blocking(pio1, SMIRXSM);
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pio_sm_set_enabled(pio1, SMIRXSM, false);
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return val;
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}
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static void rx_irq(void);
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static bool mg_tcpip_driver_rp2040_rmii_init(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_rp2040_rmii_data *d =
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(struct mg_tcpip_driver_rp2040_rmii_data *) ifp->driver_data;
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uint rx_sm_addr, tx_sm_addr;
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s_ifp = ifp;
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rx_sm_addr = pio_add_program(pio0, &rmii_rx_program);
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tx_sm_addr = pio_add_program(pio0, &rmii_tx_program);
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smi_wr_addr = pio_add_program(pio0, &smi_wr_program);
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smi_rd_addr = pio_add_program(pio1, &smi_rd_program);
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dma_tx = dma_claim_unused_channel(true);
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dmacfg_tx = dma_channel_get_default_config(dma_tx);
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channel_config_set_read_increment(&dmacfg_tx, true); // read from memory
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channel_config_set_write_increment(&dmacfg_tx, false); // write to FIFO
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channel_config_set_dreq(&dmacfg_tx, pio_get_dreq(pio0, TXSM, true));
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channel_config_set_transfer_data_size(&dmacfg_tx,
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DMA_SIZE_8); // transfer bytes
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rmii_tx_init(pio0, TXSM, tx_sm_addr, d->tx0);
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eth_write_phy(d->phy_addr, 4, 0x61,
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d->mdio); // Auto Negotiation Advertisement Register: enable
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// only 10BASE-T full and half duplex (two-pair), use
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// IEEE 802.3 format
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sleep_us(31); // give some time for PIO to work (64 bits @2.5MHz = 25.6 us)
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eth_write_phy(d->phy_addr, 0, 0x1000,
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d->mdio); // Basic Control Register: enable Auto-Negotiation
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sleep_us(31);
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dma_rx = dma_claim_unused_channel(true);
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dmacfg_rx = dma_channel_get_default_config(dma_rx);
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channel_config_set_read_increment(&dmacfg_rx, false); // read from FIFO
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channel_config_set_write_increment(&dmacfg_rx,
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true); // write to memory, increment
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channel_config_set_dreq(&dmacfg_rx, pio_get_dreq(pio0, RXSM, false));
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channel_config_set_transfer_data_size(&dmacfg_rx,
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DMA_SIZE_8); // transfer bytes
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dma_channel_configure(dma_rx, &dmacfg_rx, s_rxbuf[0],
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((uint8_t *) &pio0->rxf[RXSM]) + 3, ETH_PKT_SIZE, true);
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pio_set_irq0_source_enabled(pio0, pis_interrupt0,
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true); // enable SM0 on PIO0_IRQ_0
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irq_set_exclusive_handler(7, rx_irq); // set handler for PIO0_IRQ_0
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irq_set_enabled(7, true); // enable it
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rmii_rx_init(pio0, RXSM, rx_sm_addr, d->rx0);
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return true;
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}
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static size_t mg_tcpip_driver_rp2040_rmii_tx(const void *buf, size_t len,
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struct mg_tcpip_if *ifp) {
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dma_channel_wait_for_finish_blocking(dma_tx);
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memset(s_txbuf, 0, 60); // pre-pad
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memcpy(s_txbuf, buf, len);
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if (len < 60) len = 60; // pad
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uint32_t crc = mg_crc32(0, s_txbuf, len); // host is little-endian
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memcpy(s_txbuf + len, (uint8_t *) &crc, 4);
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len += 4;
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sleep_us(10); // enforce IFG in case software has been lightning fast...
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dma_channel_configure(dma_tx, &dmacfg_tx, ((uint8_t *) &pio0->txf[TXSM]) + 3,
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s_txbuf, len, true);
|
||||
return len;
|
||||
}
|
||||
|
||||
static uint32_t s_rxno;
|
||||
|
||||
// The max amount of time we should keep the PIO state machine stopped is the
|
||||
// IFG time (10us) and that includes irq latency
|
||||
static void rx_irq(void) {
|
||||
dma_channel_hw_t *hw = dma_channel_hw_addr(dma_rx);
|
||||
uint32_t rxno =
|
||||
(s_rxno + 1) &
|
||||
1; // 2 buffers, switch to the available one as fast as possible
|
||||
size_t len = ETH_PKT_SIZE - hw->transfer_count;
|
||||
dma_channel_abort(dma_rx);
|
||||
dma_channel_set_write_addr(dma_rx, s_rxbuf[rxno], true); // restart DMA
|
||||
pio_interrupt_clear(pio0,
|
||||
0); // ACK PIO IRQ so the state machine resumes receiving
|
||||
// NOTE(scaprile) Here we could check addressing to avoid queuing frames not
|
||||
// for us. The max amount of time we can linger here is what it takes for the
|
||||
// other buffer to fill (<8us) and that includes irq chaining
|
||||
if (len >= 64 && len <= ETH_PKT_SIZE)
|
||||
mg_tcpip_qwrite(s_rxbuf[s_rxno], len, s_ifp);
|
||||
s_rxno = rxno;
|
||||
}
|
||||
|
||||
static bool mg_tcpip_driver_rp2040_rmii_poll(struct mg_tcpip_if *ifp, bool s1) {
|
||||
if (!s1) return false;
|
||||
struct mg_tcpip_driver_rp2040_rmii_data *d =
|
||||
(struct mg_tcpip_driver_rp2040_rmii_data *) ifp->driver_data;
|
||||
uint32_t bsr =
|
||||
eth_read_phy(d->phy_addr, 1, d->mdio); // Basic Status Register
|
||||
return (bsr & (1 << 2)) ? 1 : 0; // check Link Status flag
|
||||
}
|
||||
|
||||
struct mg_tcpip_driver mg_tcpip_driver_rp2040_rmii = {
|
||||
mg_tcpip_driver_rp2040_rmii_init,
|
||||
mg_tcpip_driver_rp2040_rmii_tx,
|
||||
NULL,
|
||||
mg_tcpip_driver_rp2040_rmii_poll,
|
||||
};
|
||||
@@ -0,0 +1,10 @@
|
||||
#pragma once
|
||||
|
||||
struct mg_tcpip_driver_rp2040_rmii_data {
|
||||
uint8_t rx0; // RX0, RX1, CRS_DV; consecutive GPIO pins
|
||||
uint8_t tx0; // TX0, TX1, TX-EN; consecutive GPIO pins
|
||||
uint8_t mdio; // MDIO, MDC; consecutive GPIO pins
|
||||
uint8_t phy_addr; // PHY address
|
||||
};
|
||||
|
||||
extern struct mg_tcpip_driver mg_tcpip_driver_rp2040_rmii;
|
||||
@@ -0,0 +1,67 @@
|
||||
// Copyright (c) 2022 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "pico/stdlib.h"
|
||||
#include "hardware/clocks.h"
|
||||
#include "driver_rp2040_rmii.h"
|
||||
#include "mongoose.h"
|
||||
|
||||
#define CLKREFPIN 20 // either 20 or 22
|
||||
|
||||
static void driver_init(struct mg_mgr *mgr) {
|
||||
MG_INFO(("Init TCP/IP"));
|
||||
// Initialise Mongoose network stack and specific driver
|
||||
// Set consecutive GPIOs for RMII (tx and rx) and SMI function groups
|
||||
struct mg_tcpip_driver_rp2040_rmii_data driver_data = {
|
||||
// see driver_rp2040_rmii.h
|
||||
.rx0 = 6, // 6, 7, 8 : RX0, RX1, CRS_DV
|
||||
.tx0 = 10, // 10, 11, 12 : TX0, TX1, TX-EN
|
||||
.mdio = 14, // 14, 15 : MDIO, MDC
|
||||
.phy_addr = 1 // check your hardware, LAN8722 is 0 or 1
|
||||
};
|
||||
// Specify MAC address, either set use_dhcp or enter a static config.
|
||||
// For static configuration, specify IP/mask/GW in network byte order
|
||||
struct mg_tcpip_if mif = {
|
||||
.mac = {2, 0, 1, 2, 3, 5},
|
||||
.ip = 0,
|
||||
.enable_mac_check = true,
|
||||
.enable_fcs_check = true,
|
||||
.driver = &mg_tcpip_driver_rp2040_rmii,
|
||||
.driver_data = &driver_data,
|
||||
};
|
||||
mg_tcpip_init(mgr, &mif);
|
||||
}
|
||||
|
||||
static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) {
|
||||
if (ev == MG_EV_HTTP_MSG) { // New HTTP request received
|
||||
struct mg_http_message *hm = (struct mg_http_message *) ev_data;
|
||||
uint64_t tick = to_ms_since_boot(get_absolute_time());
|
||||
if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) {
|
||||
mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), tick);
|
||||
} else {
|
||||
mg_http_reply(c, 200, "", "Hi from Mongoose, tick %llu\n", tick);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// In an RTOS environment, give this task 8 KB of stack space.
|
||||
static void run_mongoose(void) {
|
||||
struct mg_mgr mgr;
|
||||
mg_mgr_init(&mgr);
|
||||
driver_init(&mgr);
|
||||
mg_log_set(MG_LL_DEBUG); // Set log level
|
||||
MG_INFO(("Hardware initialised, starting firmware..."));
|
||||
mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL);
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 1);
|
||||
}
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
// use the RMII reference clock (50MHz) as our system clock
|
||||
clock_configure_gpin(clk_sys, CLKREFPIN, 50 * MHZ, 50 * MHZ);
|
||||
sleep_ms(100);
|
||||
stdio_init_all();
|
||||
run_mongoose();
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,4 @@
|
||||
#define MG_ARCH MG_ARCH_PICOSDK
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_TCPIP_DRIVER_INIT 0
|
||||
Reference in new issue
Block a user