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Enable FPU
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13fffbc5b6
commit
8596e1bef7
4 files changed
+28
-9
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@@ -27,6 +27,7 @@ static void sfn(struct mg_connection *c, int ev, void *ev_data, void *fn_data) {
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uint64_t t = *(uint64_t *) ev_data;
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MG_INFO(("%lu SNTP: %lld ms from epoch", c->id, t));
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s_boot_timestamp = (time_t) ((t - mg_millis()) / 1000);
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c->is_closing = 1;
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} else if (ev == MG_EV_CLOSE) {
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s_sntp_conn = NULL;
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}
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@@ -35,12 +36,14 @@ static void sfn(struct mg_connection *c, int ev, void *ev_data, void *fn_data) {
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static void sntp_cb(void *param) { // SNTP timer function. Sync up time
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struct mg_mgr *mgr = (struct mg_mgr *) param;
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if (s_sntp_conn == NULL) s_sntp_conn = mg_sntp_connect(mgr, NULL, sfn, NULL);
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if (s_boot_timestamp < 9999) mg_sntp_request(s_sntp_conn);
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return; // TODO(cpq): re-enable!
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if (s_sntp_conn == NULL && s_boot_timestamp == 0) {
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s_sntp_conn = mg_sntp_connect(mgr, NULL, sfn, NULL);
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}
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}
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static void blink_cb(void *arg) { // Blink periodically
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// MG_INFO(("ticks: %u", (unsigned) s_ticks));
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MG_INFO(("ticks: %u", (unsigned) s_ticks));
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gpio_toggle(LED2);
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(void) arg;
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}
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@@ -65,6 +65,17 @@ struct flash {
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};
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#define FLASH ((struct flash *) 0x40023c00)
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struct scb {
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volatile uint32_t CPUID, ICSR, VTOR, AIRCR, SCR, CCR, SHPR[3], SHCSR, CFSR,
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HFSR, DFSR, MMFAR, BFAR, AFSR, ID_PFR[2], ID_DFR, ID_AFR, ID_MFR[4],
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ID_ISAR[5], RESERVED0[1], CLIDR, CTR, CCSIDR, CSSELR, CPACR,
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RESERVED3[93], STIR, RESERVED4[15], MVFR0, MVFR1, MVFR2, RESERVED5[1],
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ICIALLU, RESERVED6[1], ICIMVAU, DCIMVAC, DCISW, DCCMVAU, DCCMVAC, DCCSW,
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DCCIMVAC, DCCISW, RESERVED7[6], ITCMCR, DTCMCR, AHBPCR, CACR, AHBSCR,
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RESERVED8[1], ABFSR;
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};
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#define SCB ((struct scb *) 0xe000e000)
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
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@@ -182,6 +193,7 @@ static inline void clock_init(void) { // Set clock to 216Mhz
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while ((PWR->CSR1 & BIT(16)) == 0) spin(1); // Wait until done
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PWR->CR1 |= BIT(17); // Enable overdrive switching
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while ((PWR->CSR1 & BIT(17)) == 0) spin(1); // Wait until done
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
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#endif
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FLASH->ACR |= 7 | BIT(8) | BIT(9); // Flash latency 7, prefetch
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RCC->PLLCFGR &= ~((BIT(15) - 1)); // PLL = HSI * N / M / P
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