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Unify naming: all network stacks are in src/net_...
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cpq committed
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@@ -0,0 +1,249 @@
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#include "tcpip.h"
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_TM4C) && MG_ENABLE_DRIVER_TM4C
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struct tm4c_emac {
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volatile uint32_t EMACCFG, EMACFRAMEFLTR, EMACHASHTBLH, EMACHASHTBLL,
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EMACMIIADDR, EMACMIIDATA, EMACFLOWCTL, EMACVLANTG, RESERVED0, EMACSTATUS,
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EMACRWUFF, EMACPMTCTLSTAT, RESERVED1[2], EMACRIS, EMACIM, EMACADDR0H,
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EMACADDR0L, EMACADDR1H, EMACADDR1L, EMACADDR2H, EMACADDR2L, EMACADDR3H,
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EMACADDR3L, RESERVED2[31], EMACWDOGTO, RESERVED3[8], EMACMMCCTRL,
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EMACMMCRXRIS, EMACMMCTXRIS, EMACMMCRXIM, EMACMMCTXIM, RESERVED4,
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EMACTXCNTGB, RESERVED5[12], EMACTXCNTSCOL, EMACTXCNTMCOL, RESERVED6[4],
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EMACTXOCTCNTG, RESERVED7[6], EMACRXCNTGB, RESERVED8[4], EMACRXCNTCRCERR,
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EMACRXCNTALGNERR, RESERVED9[10], EMACRXCNTGUNI, RESERVED10[239],
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EMACVLNINCREP, EMACVLANHASH, RESERVED11[93], EMACTIMSTCTRL, EMACSUBSECINC,
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EMACTIMSEC, EMACTIMNANO, EMACTIMSECU, EMACTIMNANOU, EMACTIMADD,
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EMACTARGSEC, EMACTARGNANO, EMACHWORDSEC, EMACTIMSTAT, EMACPPSCTRL,
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RESERVED12[12], EMACPPS0INTVL, EMACPPS0WIDTH, RESERVED13[294],
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EMACDMABUSMOD, EMACTXPOLLD, EMACRXPOLLD, EMACRXDLADDR, EMACTXDLADDR,
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EMACDMARIS, EMACDMAOPMODE, EMACDMAIM, EMACMFBOC, EMACRXINTWDT,
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RESERVED14[8], EMACHOSTXDESC, EMACHOSRXDESC, EMACHOSTXBA, EMACHOSRXBA,
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RESERVED15[218], EMACPP, EMACPC, EMACCC, RESERVED16, EMACEPHYRIS,
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EMACEPHYIM, EMACEPHYIMSC;
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};
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#undef EMAC
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#define EMAC ((struct tm4c_emac *) (uintptr_t) 0x400EC000)
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#undef BIT
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#define BIT(x) ((uint32_t) 1 << (x))
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#define ETH_PKT_SIZE 1540 // Max frame size
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#define ETH_DESC_CNT 4 // Descriptors count
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#define ETH_DS 4 // Descriptor size (words)
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static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
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static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
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static struct mg_tcpip_if *s_ifp; // MIP interface
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enum {
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EPHY_ADDR = 0,
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EPHYBMCR = 0,
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EPHYBMSR = 1,
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EPHYSTS = 16
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}; // PHY constants
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static inline void tm4cspin(volatile uint32_t count) {
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while (count--) (void) 0;
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}
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static uint32_t emac_read_phy(uint8_t addr, uint8_t reg) {
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EMAC->EMACMIIADDR &= (0xf << 2);
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EMAC->EMACMIIADDR |= ((uint32_t) addr << 11) | ((uint32_t) reg << 6);
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EMAC->EMACMIIADDR |= BIT(0);
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while (EMAC->EMACMIIADDR & BIT(0)) tm4cspin(1);
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return EMAC->EMACMIIDATA;
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}
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static void emac_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
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EMAC->EMACMIIDATA = val;
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EMAC->EMACMIIADDR &= (0xf << 2);
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EMAC->EMACMIIADDR |= ((uint32_t) addr << 11) | ((uint32_t) reg << 6) | BIT(1);
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EMAC->EMACMIIADDR |= BIT(0);
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while (EMAC->EMACMIIADDR & BIT(0)) tm4cspin(1);
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}
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static uint32_t get_sysclk(void) {
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struct sysctl {
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volatile uint32_t DONTCARE0[44], RSCLKCFG, DONTCARE1[43], PLLFREQ0,
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PLLFREQ1;
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} *sysctl = (struct sysctl *) 0x400FE000;
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uint32_t clk = 0, piosc = 16000000 /* 16 MHz */, mosc = 25000000 /* 25MHz */;
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if (sysctl->RSCLKCFG & (1 << 28)) { // USEPLL
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uint32_t fin, vco, mdiv, n, q, psysdiv;
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uint32_t pllsrc = (sysctl->RSCLKCFG & (0xf << 24)) >> 24;
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if (pllsrc == 0) {
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clk = piosc;
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} else if (pllsrc == 3) {
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clk = mosc;
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} else {
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MG_ERROR(("Unsupported clock source"));
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}
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q = (sysctl->PLLFREQ1 & (0x1f << 8)) >> 8;
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n = (sysctl->PLLFREQ1 & (0x1f << 0)) >> 0;
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fin = clk / ((q + 1) * (n + 1));
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mdiv = (sysctl->PLLFREQ0 & (0x3ff << 0)) >>
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0; // mint + (mfrac / 1024); MFRAC not supported
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psysdiv = (sysctl->RSCLKCFG & (0x3f << 0)) >> 0;
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vco = (uint32_t) ((uint64_t) fin * mdiv);
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return vco / (psysdiv + 1);
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}
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uint32_t oscsrc = (sysctl->RSCLKCFG & (0xf << 20)) >> 20;
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if (oscsrc == 0) {
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clk = piosc;
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} else if (oscsrc == 3) {
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clk = mosc;
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} else {
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MG_ERROR(("Unsupported clock source"));
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}
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uint32_t osysdiv = (sysctl->RSCLKCFG & (0xf << 16)) >> 16;
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return clk / (osysdiv + 1);
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}
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// Guess CR from SYSCLK. MDC clock is generated from SYSCLK (AHB); as per
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// 802.3, it must not exceed 2.5MHz (also 20.4.2.6) As the AHB clock can be
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// derived from the PIOSC (internal RC), and it can go above specs, the
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// datasheets specify a range of frequencies and activate one of a series of
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// dividers to keep the MDC clock safely below 2.5MHz. We guess a divider
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// setting based on SYSCLK with a +5% drift. If the user uses a different clock
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// from our defaults, needs to set the macros on top Valid for TM4C129x (20.7)
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// (4.5% worst case drift)
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// The PHY receives the main oscillator (MOSC) (20.3.1)
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static int guess_mdc_cr(void) {
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uint8_t crs[] = {2, 3, 0, 1}; // EMAC->MACMIIAR::CR values
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uint8_t div[] = {16, 26, 42, 62}; // Respective HCLK dividers
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uint32_t sysclk = get_sysclk(); // Guess system SYSCLK
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int result = -1; // Invalid CR value
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if (sysclk < 25000000) {
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MG_ERROR(("SYSCLK too low"));
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} else {
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for (int i = 0; i < 4; i++) {
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if (sysclk / div[i] <= 2375000UL /* 2.5MHz - 5% */) {
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result = crs[i];
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break;
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}
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}
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if (result < 0) MG_ERROR(("SYSCLK too high"));
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}
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MG_DEBUG(("SYSCLK: %u, CR: %d", sysclk, result));
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return result;
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}
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static bool mg_tcpip_driver_tm4c_init(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_tm4c_data *d =
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(struct mg_tcpip_driver_tm4c_data *) ifp->driver_data;
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s_ifp = ifp;
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// Init RX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_rxdesc[i][0] = BIT(31); // Own
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s_rxdesc[i][1] = sizeof(s_rxbuf[i]) | BIT(14); // 2nd address chained
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s_rxdesc[i][2] = (uint32_t) (uintptr_t) s_rxbuf[i]; // Point to data buffer
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s_rxdesc[i][3] =
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(uint32_t) (uintptr_t) s_rxdesc[(i + 1) % ETH_DESC_CNT]; // Chain
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// MG_DEBUG(("%d %p", i, s_rxdesc[i]));
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}
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// Init TX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_txdesc[i][2] = (uint32_t) (uintptr_t) s_txbuf[i]; // Buf pointer
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s_txdesc[i][3] =
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(uint32_t) (uintptr_t) s_txdesc[(i + 1) % ETH_DESC_CNT]; // Chain
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}
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EMAC->EMACDMABUSMOD |= BIT(0); // Software reset
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while ((EMAC->EMACDMABUSMOD & BIT(0)) != 0) tm4cspin(1); // Wait until done
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// Set MDC clock divider. If user told us the value, use it. Otherwise, guess
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int cr = (d == NULL || d->mdc_cr < 0) ? guess_mdc_cr() : d->mdc_cr;
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EMAC->EMACMIIADDR = ((uint32_t) cr & 0xf) << 2;
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// NOTE(cpq): we do not use extended descriptor bit 7, and do not use
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// hardware checksum. Therefore, descriptor size is 4, not 8
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// EMAC->EMACDMABUSMOD = BIT(13) | BIT(16) | BIT(22) | BIT(23) | BIT(25);
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EMAC->EMACIM = BIT(3) | BIT(9); // Mask timestamp & PMT IT
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EMAC->EMACFLOWCTL = BIT(7); // Disable zero-quanta pause
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// EMAC->EMACFRAMEFLTR = BIT(31); // Receive all
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// EMAC->EMACPC defaults to internal PHY (EPHY) in MMI mode
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emac_write_phy(EPHY_ADDR, EPHYBMCR, BIT(15)); // Reset internal PHY (EPHY)
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emac_write_phy(EPHY_ADDR, EPHYBMCR, BIT(12)); // Set autonegotiation
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EMAC->EMACRXDLADDR = (uint32_t) (uintptr_t) s_rxdesc; // RX descriptors
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EMAC->EMACTXDLADDR = (uint32_t) (uintptr_t) s_txdesc; // TX descriptors
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EMAC->EMACDMAIM = BIT(6) | BIT(16); // RIE, NIE
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EMAC->EMACCFG = BIT(2) | BIT(3) | BIT(11) | BIT(14); // RE, TE, Duplex, Fast
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EMAC->EMACDMAOPMODE =
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BIT(1) | BIT(13) | BIT(21) | BIT(25); // SR, ST, TSF, RSF
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EMAC->EMACADDR0H = ((uint32_t) ifp->mac[5] << 8U) | ifp->mac[4];
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EMAC->EMACADDR0L = (uint32_t) (ifp->mac[3] << 24) |
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((uint32_t) ifp->mac[2] << 16) |
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((uint32_t) ifp->mac[1] << 8) | ifp->mac[0];
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// NOTE(scaprile) There are 3 additional slots for filtering, disabled by
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// default. This also applies to the STM32 driver (at least for F7)
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return true;
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}
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static uint32_t s_txno;
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static size_t mg_tcpip_driver_tm4c_tx(const void *buf, size_t len,
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struct mg_tcpip_if *ifp) {
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if (len > sizeof(s_txbuf[s_txno])) {
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MG_ERROR(("Frame too big, %ld", (long) len));
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len = 0; // fail
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} else if ((s_txdesc[s_txno][0] & BIT(31))) {
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MG_ERROR(("No descriptors available"));
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// printf("D0 %lx SR %lx\n", (long) s_txdesc[0][0], (long)
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// EMAC->EMACDMARIS);
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len = 0; // fail
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} else {
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][1] = (uint32_t) len; // Set data len
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s_txdesc[s_txno][0] =
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BIT(20) | BIT(28) | BIT(29) | BIT(30); // Chain,FS,LS,IC
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s_txdesc[s_txno][0] |= BIT(31); // Set OWN bit - let DMA take over
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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EMAC->EMACDMARIS = BIT(2) | BIT(5); // Clear any prior TU/UNF
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EMAC->EMACTXPOLLD = 0; // and resume
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return len;
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(void) ifp;
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}
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static bool mg_tcpip_driver_tm4c_up(struct mg_tcpip_if *ifp) {
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uint32_t bmsr = emac_read_phy(EPHY_ADDR, EPHYBMSR);
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bool up = (bmsr & BIT(2)) ? 1 : 0;
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if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up
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uint32_t sts = emac_read_phy(EPHY_ADDR, EPHYSTS);
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uint32_t emaccfg = EMAC->EMACCFG | BIT(14) | BIT(11); // 100M, Full-duplex
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if (sts & BIT(1)) emaccfg &= ~BIT(14); // 10M
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if ((sts & BIT(2)) == 0) emaccfg &= ~BIT(11); // Half-duplex
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EMAC->EMACCFG = emaccfg; // IRQ handler does not fiddle with this register
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MG_DEBUG(("Link is %uM %s-duplex", emaccfg & BIT(14) ? 100 : 10,
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emaccfg & BIT(11) ? "full" : "half"));
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}
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return up;
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}
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void EMAC0_IRQHandler(void);
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static uint32_t s_rxno;
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void EMAC0_IRQHandler(void) {
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if (EMAC->EMACDMARIS & BIT(6)) { // Frame received, loop
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EMAC->EMACDMARIS = BIT(16) | BIT(6); // Clear flag
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for (uint32_t i = 0; i < 10; i++) { // read as they arrive but not forever
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if (s_rxdesc[s_rxno][0] & BIT(31)) break; // exit when done
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if (((s_rxdesc[s_rxno][0] & (BIT(8) | BIT(9))) == (BIT(8) | BIT(9))) &&
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!(s_rxdesc[s_rxno][0] & BIT(15))) { // skip partial/errored frames
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uint32_t len = ((s_rxdesc[s_rxno][0] >> 16) & (BIT(14) - 1));
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// printf("%lx %lu %lx %.8lx\n", s_rxno, len, s_rxdesc[s_rxno][0],
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// EMAC->EMACDMARIS);
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mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp);
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}
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s_rxdesc[s_rxno][0] = BIT(31);
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if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
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}
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}
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EMAC->EMACDMARIS = BIT(7); // Clear possible RU while processing
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EMAC->EMACRXPOLLD = 0; // and resume RX
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}
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struct mg_tcpip_driver mg_tcpip_driver_tm4c = {mg_tcpip_driver_tm4c_init,
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mg_tcpip_driver_tm4c_tx, NULL,
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mg_tcpip_driver_tm4c_up};
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#endif
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