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Add MIP - an experimental TCP/IP stack
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Sergey Lyubka committed
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# This is a collection of low-level drivers for the experimental
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# built-in TCP/IP stack
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// Copyright (c) 2022 Cesanta Software Limited
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// All rights reserved
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#include "mip_driver_stm32.h"
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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struct eth {
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uint32_t MACCR, MACFFR, MACHTHR, MACHTLR, MACMIIAR, MACMIIDR, MACFCR,
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MACVLANTR, RESERVED0[2], MACRWUFFR, MACPMTCSR, RESERVED1, MACDBGR, MACSR,
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MACIMR, MACA0HR, MACA0LR, MACA1HR, MACA1LR, MACA2HR, MACA2LR, MACA3HR,
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MACA3LR, RESERVED2[40], MMCCR, MMCRIR, MMCTIR, MMCRIMR, MMCTIMR,
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RESERVED3[14], MMCTGFSCCR, MMCTGFMSCCR, RESERVED4[5], MMCTGFCR,
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RESERVED5[10], MMCRFCECR, MMCRFAECR, RESERVED6[10], MMCRGUFCR,
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RESERVED7[334], PTPTSCR, PTPSSIR, PTPTSHR, PTPTSLR, PTPTSHUR, PTPTSLUR,
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PTPTSAR, PTPTTHR, PTPTTLR, RESERVED8, PTPTSSR, PTPPPSCR, RESERVED9[564],
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DMABMR, DMATPDR, DMARPDR, DMARDLAR, DMATDLAR, DMASR, DMAOMR, DMAIER,
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DMAMFBOCR, DMARSWTR, RESERVED10[8], DMACHTDR, DMACHRDR, DMACHTBAR,
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DMACHRBAR;
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};
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#define ETH ((struct eth *) 0x40028000)
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#define BIT(x) (1UL << (x))
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#define ETH_PKT_SIZE 1540 // Max frame size
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#define ETH_DESC_CNT 4 // Descriptors count
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#define ETH_DS 4 // Descriptor size (words)
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static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
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static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
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static void (*s_rx)(void *, size_t, void *); // Recv callback
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static void *s_rxdata; // Recv callback data
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static void *s_userdata; // Driver data
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enum { PHY_ADDR = 0, PHY_BCR = 0, PHY_BSR = 1 }; // PHY constants
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static inline void spin(volatile uint32_t count) {
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while (count--) asm("nop");
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}
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uint32_t eth_read_phy(uint8_t addr, uint8_t reg) {
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ETH->MACMIIAR &= (7 << 2);
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ETH->MACMIIAR |= ((uint32_t) addr << 11) | ((uint32_t) reg << 6);
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ETH->MACMIIAR |= BIT(0);
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while (ETH->MACMIIAR & BIT(0)) spin(1);
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return ETH->MACMIIDR;
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}
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void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
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ETH->MACMIIDR = val;
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ETH->MACMIIAR &= (7 << 2);
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ETH->MACMIIAR |= ((uint32_t) addr << 11) | ((uint32_t) reg << 6) | BIT(1);
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ETH->MACMIIAR |= BIT(0);
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while (ETH->MACMIIAR & BIT(0)) spin(1);
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}
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void mip_driver_stm32_init(void *userdata) {
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s_userdata = userdata;
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// Init RX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_rxdesc[i][0] = BIT(31); // Own
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s_rxdesc[i][1] = sizeof(s_rxbuf[i]) | BIT(14); // 2nd address chained
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s_rxdesc[i][2] = (uint32_t) s_rxbuf[i]; // Point to data buffer
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s_rxdesc[i][3] = (uint32_t) s_rxdesc[(i + 1) % ETH_DESC_CNT]; // Chain
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}
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// Init TX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_txdesc[i][2] = (uint32_t) s_txbuf[i]; // Buf pointer
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s_txdesc[i][3] = (uint32_t) s_txdesc[(i + 1) % ETH_DESC_CNT]; // Chain
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}
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ETH->DMABMR |= BIT(0); // Software reset
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while ((ETH->DMABMR & BIT(0)) != 0) spin(1); // Wait until done
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// NOTE(cpq): we do not use extended descriptor bit 7, and do not use
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// hardware checksum. Therefore, descriptor size is 4, not 8
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// ETH->DMABMR = BIT(13) | BIT(16) | BIT(22) | BIT(23) | BIT(25);
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ETH->MACIMR = BIT(3) | BIT(9); // Mask timestamp & PMT IT
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ETH->MACMIIAR = 4 << 2; // MDC clock 150-216 MHz, 38.8.1
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ETH->MACFCR = BIT(7); // Disable zero quarta pause
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ETH->MACFFR = BIT(31); // Receive all
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eth_write_phy(PHY_ADDR, PHY_BCR, BIT(15)); // Reset PHY
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eth_write_phy(PHY_ADDR, PHY_BCR, BIT(12)); // Set autonegotiation
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ETH->DMARDLAR = (uint32_t) s_rxdesc; // RX descriptors
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ETH->DMATDLAR = (uint32_t) s_txdesc; // RX descriptors
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ETH->DMAIER = BIT(6) | BIT(16); // RIE, NISE
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ETH->MACCR = BIT(2) | BIT(3) | BIT(11) | BIT(14); // RE, TE, Duplex, Fast
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ETH->DMAOMR = BIT(1) | BIT(13) | BIT(21) | BIT(25); // SR, ST, TSF, RSF
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}
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void mip_driver_stm32_setrx(void (*rx)(void *, size_t, void *), void *rxdata) {
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s_rx = rx;
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s_rxdata = rxdata;
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}
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static uint32_t s_txno;
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size_t mip_driver_stm32_tx(const void *buf, size_t len, void *userdata) {
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if (len > sizeof(s_txbuf[s_txno])) {
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printf("%s: frame too big, %ld\n", __func__, (long) len);
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len = 0; // Frame is too big
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} else if ((s_txdesc[s_txno][0] & BIT(31))) {
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printf("%s: no free descr\n", __func__);
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len = 0; // All descriptors are busy, fail
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} else {
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][1] = (uint32_t) len; // Set data len
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s_txdesc[s_txno][0] = BIT(20) | BIT(28) | BIT(29) | BIT(30); // Chain,FS,LS
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s_txdesc[s_txno][0] |= BIT(31); // Set OWN bit - let DMA take over
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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uint32_t sr = ETH->DMASR;
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if (sr & BIT(2)) ETH->DMASR = BIT(2), ETH->DMATPDR = 0; // Resume
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if (sr & BIT(5)) ETH->DMASR = BIT(5), ETH->DMATPDR = 0; // if busy
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if (len == 0) printf("E: D0 %lx, DMASR %lx\n", s_txdesc[0][0], sr);
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return len;
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(void) userdata;
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}
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bool mip_driver_stm32_status(void *userdata) {
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uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR);
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return bsr & BIT(2) ? 1 : 0;
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(void) userdata;
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}
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void ETH_IRQHandler(void) {
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volatile uint32_t sr = ETH->DMASR;
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if (sr & BIT(6)) { // Frame received, loop
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for (uint32_t i = 0; i < ETH_DESC_CNT; i++) {
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if (s_rxdesc[i][0] & BIT(31)) continue;
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uint32_t len = ((s_rxdesc[i][0] >> 16) & (BIT(14) - 1));
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// printf("%lx %lu %lx %lx\n", i, len, s_rxdesc[i][0], sr);
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if (s_rx != NULL) s_rx(s_rxbuf[i], len > 4 ? len - 4 : len, s_rxdata);
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s_rxdesc[i][0] = BIT(31);
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}
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}
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if (sr & BIT(7)) ETH->DMARPDR = 0; // Resume RX
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ETH->DMASR = sr & ~(BIT(2) | BIT(7)); // Clear status
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}
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// Copyright (c) 2022 Cesanta Software Limited
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// All rights reserved
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#pragma once
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#include <stdbool.h>
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#include <stddef.h>
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void mip_driver_stm32_init(void *userdata);
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bool mip_driver_stm32_status(void *);
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void mip_driver_stm32_setrx(void (*rx)(void *, size_t, void *), void *);
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size_t mip_driver_stm32_tx(const void *buf, size_t len, void *);
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@@ -0,0 +1,99 @@
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// Copyright (c) 2022 Cesanta Software Limited
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// All rights reserved
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//
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// This software is dual-licensed: you can redistribute it and/or modify
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// it under the terms of the GNU Affero General Public License version 3 as
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// published by the Free Software Foundation. For the terms of this
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// license, see http://www.fsf.org/licensing/licenses/agpl-3.0.html
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//
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// You are free to use this software under the terms of the GNU General
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// Public License, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// See the GNU General Public License for more details.
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//
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// Alternatively, you can license this software under a commercial
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// license, please contact us at https://cesanta.com/contact.html
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#pragma once
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struct w5500 {
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uint8_t mac[6]; // MAC address
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void *spi; // Opaque SPI bus descriptor
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uint8_t (*txn)(void *, uint8_t); // SPI transaction
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void (*begin)(void *); // SPI begin
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void (*end)(void *); // SPI end
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};
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enum { W5500_CR = 0, W5500_S0 = 1, W5500_TX0 = 2, W5500_RX0 = 3 };
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static inline void w5500_txn(struct w5500 *w, uint8_t block, uint16_t addr,
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bool wr, void *buf, size_t len) {
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uint8_t *p = buf, cmd[] = {(uint8_t) (addr >> 8), (uint8_t) (addr & 255),
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(uint8_t) ((block << 3) | (wr ? 4 : 0))};
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w->begin(w->spi);
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for (size_t i = 0; i < sizeof(cmd); i++) w->txn(w->spi, cmd[i]);
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for (size_t i = 0; i < len; i++) {
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uint8_t r = w->txn(w->spi, p[i]);
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if (!wr) p[i] = r;
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}
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w->end(w->spi);
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}
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// clang-format off
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static inline void w5500_wn(struct w5500 *w, uint8_t block, uint16_t addr, void *buf, size_t len) { w5500_txn(w, block, addr, true, buf, len); }
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static inline void w5500_w1(struct w5500 *w, uint8_t block, uint16_t addr, uint8_t val) { w5500_wn(w, block, addr, &val, 1); }
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static inline void w5500_w2(struct w5500 *w, uint8_t block, uint16_t addr, uint16_t val) { uint8_t buf[2] = {(uint8_t) (val >> 8), (uint8_t) (val & 255)}; w5500_wn(w, block, addr, buf, sizeof(buf)); }
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static inline void w5500_rn(struct w5500 *w, uint8_t block, uint16_t addr, void *buf, size_t len) { w5500_txn(w, block, addr, false, buf, len); }
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static inline uint8_t w5500_r1(struct w5500 *w, uint8_t block, uint16_t addr) { uint8_t r = 0; w5500_rn(w, block, addr, &r, 1); return r; }
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static inline uint16_t w5500_r2(struct w5500 *w, uint8_t block, uint16_t addr) { uint8_t buf[2] = {0, 0}; w5500_rn(w, block, addr, buf, sizeof(buf)); return (uint16_t) ((buf[0] << 8) | buf[1]); }
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// clang-format on
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static inline uint8_t w5500_status(struct w5500 *w) {
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return w5500_r1(w, W5500_CR, 0x2e);
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}
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static inline uint16_t w5500_rx(struct w5500 *w, uint8_t *buf, uint16_t len) {
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uint16_t r = 0, n = 0, n2; // Read recv len
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while ((n2 = w5500_r2(w, W5500_S0, 0x26)) > n) n = n2; // Until it is stable
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// printf("RSR: %d\n", (int) n);
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if (n > 0) {
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uint16_t ptr = w5500_r2(w, W5500_S0, 0x28); // Get read pointer
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n = w5500_r2(w, W5500_RX0, ptr); // Read frame length
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if (n <= len + 2) r = n - 2, w5500_rn(w, W5500_RX0, ptr + 2, buf, r);
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w5500_w2(w, W5500_S0, 0x28, ptr + n); // Advance read pointer
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w5500_w1(w, W5500_S0, 1, 0x40); // Sock0 CR -> RECV
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// printf(" RX_RD: tot=%u n=%u r=%u\n", n2, n, r);
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}
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return r;
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}
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static inline uint16_t w5500_tx(struct w5500 *w, void *buf, uint16_t len) {
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uint16_t n = 0;
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while (n < len) n = w5500_r2(w, W5500_S0, 0x20); // Wait for space
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uint16_t ptr = w5500_r2(w, W5500_S0, 0x24); // Get write pointer
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w5500_wn(w, W5500_TX0, ptr, buf, len); // Write data
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w5500_w2(w, W5500_S0, 0x24, ptr + len); // Advance write pointer
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w5500_w1(w, W5500_S0, 1, 0x20); // Sock0 CR -> SEND
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for (int i = 0; i < 40; i++) {
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uint8_t ir = w5500_r1(w, W5500_S0, 2); // Read S0 IR
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if (ir == 0) continue;
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// printf("IR %d, len=%d, free=%d, ptr %d\n", ir, (int) len, (int) n, ptr);
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w5500_w1(w, W5500_S0, 2, ir); // Write S0 IR: clear it!
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if (ir & 8) len = 0; // Timeout. Report error
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if (ir & (16 | 8)) break; // Stop on SEND_OK or timeout
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}
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return len;
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}
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static inline bool w5500_init(struct w5500 *w) {
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w->end(w->spi);
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w5500_w1(w, W5500_CR, 0, 0x80); // Reset chip: CR -> 0x80
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w5500_w1(w, W5500_CR, 0x2e, 0); // CR PHYCFGR -> reset
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w5500_w1(w, W5500_CR, 0x2e, 0xf8); // CR PHYCFGR -> set
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// w5500_wn(w, W5500_CR, 9, w->mac, 6); // Set source MAC
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w5500_w1(w, W5500_S0, 0x1e, 16); // Sock0 RX buf size
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w5500_w1(w, W5500_S0, 0x1f, 16); // Sock0 TX buf size
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w5500_w1(w, W5500_S0, 0, 4); // Sock0 MR -> MACRAW
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w5500_w1(w, W5500_S0, 1, 1); // Sock0 CR -> OPEN
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return w5500_r1(w, W5500_S0, 3) == 0x42; // Sock0 SR == MACRAW
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}
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