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More STM32 examples
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@@ -0,0 +1,30 @@
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# Nucleo-F746ZG Mongoose Integration
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This guide explains how to bring up a production-grade Web UI dashboard on the
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STM32 Nucleo-F746ZG development board.
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A pre-configured, ready-to-run project zip is available for download at
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https://mongoose.ws.
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||||
To integrate the Web UI dashboard into an existing CubeMX project, or to create a
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new project from scratch:
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1. Configure the peripherals (described below).
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2. Regenerate your project code and integrate Mongoose core by following
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https://mongoose.ws/docs/guides/stm32-tcpip-stack/.
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3. Add the Web UI dashboard by following
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https://mongoose.ws/docs/guides/web-dashboard-guide/.
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## Configure peripherals
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An `.ioc` file is included in this directory for your reference. It was created
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using the following steps:
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- Open CubeMX. If you are starting a new project, select the STM32F746ZG
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microcontroller and create a new project.
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- In Clock Configuration, set the maximum clock frequency to 216 MHz.
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- In the MCU pinout view, set pins PB0, PB7, and PB14 to GPIO_Output mode.
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- In Pinout & Configuration / Connectivity, enable USART3 in asynchronous mode.
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Configure pins PD8 and PD9 for USART.
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- In Pinout & Configuration / Connectivity, enable ETH in RMII mode and set pins
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PA1, PA2, PA7, PC1, PC4, PC5, PB13, PG11, and PG13 for Ethernet.
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@@ -0,0 +1,207 @@
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||||
#MicroXplorer Configuration settings - do not modify
|
||||
CAD.formats=
|
||||
CAD.pinconfig=
|
||||
CAD.provider=
|
||||
ETH.IPParameters=MediaInterface
|
||||
ETH.MediaInterface=HAL_ETH_RMII_MODE
|
||||
File.Version=6
|
||||
GPIO.groupedBy=
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||||
KeepUserPlacement=false
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||||
Mcu.CPN=STM32F746ZGT6
|
||||
Mcu.Family=STM32F7
|
||||
Mcu.IP0=CORTEX_M7
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Mcu.IP1=ETH
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Mcu.IP2=NVIC
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||||
Mcu.IP3=RCC
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||||
Mcu.IP4=RNG
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||||
Mcu.IP5=SYS
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Mcu.IP6=USART3
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||||
Mcu.IPNb=7
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Mcu.Name=STM32F746ZGTx
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||||
Mcu.Package=LQFP144
|
||||
Mcu.Pin0=PC1
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Mcu.Pin1=PA1
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Mcu.Pin10=PD9
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Mcu.Pin11=PG11
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Mcu.Pin12=PG13
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Mcu.Pin13=PB7
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Mcu.Pin14=VP_RNG_VS_RNG
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Mcu.Pin15=VP_SYS_VS_Systick
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Mcu.Pin2=PA2
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Mcu.Pin3=PA7
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Mcu.Pin4=PC4
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Mcu.Pin5=PC5
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Mcu.Pin6=PB0
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Mcu.Pin7=PB13
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Mcu.Pin8=PB14
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Mcu.Pin9=PD8
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Mcu.PinsNb=16
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Mcu.ThirdPartyNb=0
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Mcu.UserConstants=
|
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Mcu.UserName=STM32F746ZGTx
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||||
MxCube.Version=6.17.0
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MxDb.Version=DB.6.0.170
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NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.ETH_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:true
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NVIC.ForceEnableDMAVector=true
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NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
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NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
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NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
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||||
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
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||||
PA1.Mode=RMII
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PA1.Signal=ETH_REF_CLK
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PA2.Mode=RMII
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PA2.Signal=ETH_MDIO
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||||
PA7.Mode=RMII
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||||
PA7.Signal=ETH_CRS_DV
|
||||
PB0.Locked=true
|
||||
PB0.Signal=GPIO_Output
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||||
PB13.Mode=RMII
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||||
PB13.Signal=ETH_TXD1
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PB14.Locked=true
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PB14.Signal=GPIO_Output
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PB7.Locked=true
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||||
PB7.Signal=GPIO_Output
|
||||
PC1.Mode=RMII
|
||||
PC1.Signal=ETH_MDC
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PC4.Mode=RMII
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PC4.Signal=ETH_RXD0
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PC5.Mode=RMII
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||||
PC5.Signal=ETH_RXD1
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||||
PCC.Checker=false
|
||||
PCC.Display=Plot\: All Steps
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||||
PCC.Line=STM32F7x6
|
||||
PCC.MCU=STM32F746ZGTx
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||||
PCC.PartNumber=STM32F746ZGTx
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PCC.Series=STM32F7
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PCC.Temperature=25
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PCC.Vdd=3.3
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PD8.Locked=true
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PD8.Mode=Asynchronous
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PD8.Signal=USART3_TX
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PD9.Locked=true
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PD9.Mode=Asynchronous
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PD9.Signal=USART3_RX
|
||||
PG11.Locked=true
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PG11.Mode=RMII
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PG11.Signal=ETH_TX_EN
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||||
PG13.Locked=true
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||||
PG13.Mode=RMII
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PG13.Signal=ETH_TXD0
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PinOutPanel.RotationAngle=0
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ProjectManager.AskForMigrate=true
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ProjectManager.BackupPrevious=false
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ProjectManager.CompilerLinker=GCC
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ProjectManager.CompilerOptimize=6
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ProjectManager.ComputerToolchain=false
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ProjectManager.CoupleFile=false
|
||||
ProjectManager.CustomerFirmwarePackage=
|
||||
ProjectManager.DefaultFWLocation=true
|
||||
ProjectManager.DeletePrevious=true
|
||||
ProjectManager.DeviceId=STM32F746ZGTx
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||||
ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.17.4
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ProjectManager.FreePins=false
|
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ProjectManager.FreePinsContext=
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ProjectManager.HalAssertFull=false
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ProjectManager.HeapSize=0x10000
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||||
ProjectManager.KeepUserCode=true
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||||
ProjectManager.LastFirmware=true
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ProjectManager.LibraryCopy=1
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ProjectManager.MainLocation=Core/Src
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ProjectManager.NoMain=false
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ProjectManager.PreviousToolchain=STM32CubeIDE
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||||
ProjectManager.ProjectBuild=false
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ProjectManager.ProjectFileName=nucleo_f746zg.ioc
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ProjectManager.ProjectName=nucleo_f746zg
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ProjectManager.ProjectStructure=
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ProjectManager.RegisterCallBack=
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||||
ProjectManager.StackSize=0x2000
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ProjectManager.TargetToolchain=CMake
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ProjectManager.ToolChainLocation=
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ProjectManager.UAScriptAfterPath=
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ProjectManager.UAScriptBeforePath=
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ProjectManager.UnderRoot=false
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ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ETH_Init-ETH-false-HAL-true,4-MX_RNG_Init-RNG-false-HAL-true,5-MX_USART3_UART_Init-USART3-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
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||||
RCC.48MHZClocksFreq_Value=45000000
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RCC.AHBFreq_Value=216000000
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RCC.APB1CLKDivider=RCC_HCLK_DIV4
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RCC.APB1Freq_Value=54000000
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RCC.APB1TimFreq_Value=108000000
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RCC.APB2CLKDivider=RCC_HCLK_DIV2
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RCC.APB2Freq_Value=108000000
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RCC.APB2TimFreq_Value=216000000
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RCC.CECFreq_Value=32786.88524590164
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RCC.CortexFreq_Value=216000000
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RCC.EthernetFreq_Value=216000000
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RCC.FCLKCortexFreq_Value=216000000
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RCC.FamilyName=M
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RCC.HCLKFreq_Value=216000000
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RCC.HSE_VALUE=25000000
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RCC.HSI_VALUE=16000000
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RCC.I2C1Freq_Value=54000000
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RCC.I2C2Freq_Value=54000000
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RCC.I2C3Freq_Value=54000000
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RCC.I2C4Freq_Value=54000000
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RCC.I2SClocksFreq_Value=192000000
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RCC.I2SFreq_Value=192000000
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RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SClocksFreq_Value,I2SFreq_Value,LCDTFTFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,RNGFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VCOSAIOutputFreq_ValueR,VcooutputI2S,VcooutputI2SQ
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RCC.LCDTFTFreq_Value=24500000
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RCC.LCDTFToutputFreq_Value=96000000
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RCC.LPTIM1Freq_Value=54000000
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RCC.LSE_VALUE=32768
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RCC.LSI_VALUE=32000
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RCC.MCO2PinFreq_Value=216000000
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RCC.PLLCLKFreq_Value=216000000
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RCC.PLLI2SPCLKFreq_Value=192000000
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RCC.PLLI2SQCLKFreq_Value=192000000
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RCC.PLLI2SRCLKFreq_Value=192000000
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RCC.PLLI2SRoutputFreq_Value=192000000
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RCC.PLLM=8
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RCC.PLLN=216
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RCC.PLLQ=9
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RCC.PLLQCLKFreq_Value=48000000
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RCC.PLLQoutputFreq_Value=48000000
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RCC.PLLSAIPCLKFreq_Value=192000000
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RCC.PLLSAIQCLKFreq_Value=192000000
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RCC.PLLSAIRCLKFreq_Value=192000000
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RCC.RNGFreq_Value=48000000
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RCC.RTCFreq_Value=32000
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RCC.RTCHSEDivFreq_Value=12500000
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RCC.SAI1Freq_Value=192000000
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RCC.SAI2Freq_Value=192000000
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RCC.SAI_AClocksFreq_Value=24500000
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RCC.SAI_BClocksFreq_Value=24500000
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RCC.SDMMCFreq_Value=216000000
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RCC.SPDIFRXFreq_Value=192000000
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RCC.SYSCLKFreq_VALUE=216000000
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RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
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RCC.UART4Freq_Value=54000000
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RCC.UART5Freq_Value=54000000
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RCC.UART7Freq_Value=54000000
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RCC.UART8Freq_Value=54000000
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RCC.USART1Freq_Value=108000000
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RCC.USART2Freq_Value=54000000
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RCC.USART3Freq_Value=54000000
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RCC.USART6Freq_Value=108000000
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RCC.USBFreq_Value=48000000
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||||
RCC.VCOI2SOutputFreq_Value=384000000
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RCC.VCOInputFreq_Value=2000000
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RCC.VCOOutputFreq_Value=432000000
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RCC.VCOSAIOutputFreq_Value=384000000
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||||
RCC.VCOSAIOutputFreq_ValueQ=24500000
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||||
RCC.VCOSAIOutputFreq_ValueR=49000000
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||||
RCC.VcooutputI2S=192000000
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||||
RCC.VcooutputI2SQ=192000000
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||||
USART3.IPParameters=VirtualMode,VirtualMode-Asynchronous
|
||||
USART3.VirtualMode=VM_ASYNC
|
||||
USART3.VirtualMode-Asynchronous=VM_ASYNC
|
||||
VP_RNG_VS_RNG.Mode=RNG_Activate
|
||||
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
|
||||
VP_SYS_VS_Systick.Mode=SysTick
|
||||
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
|
||||
board=custom
|
||||
@@ -0,0 +1,38 @@
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||||
# Copyright (c) 2026 Cesanta Software Limited
|
||||
# Environment setup: https://mongoose.ws/docs/getting-started/build-environment/
|
||||
|
||||
CFLAGS = -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion
|
||||
CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
|
||||
CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
|
||||
CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_f7/Include
|
||||
CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 $(CFLAGS_EXTRA)
|
||||
LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nosys.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
|
||||
|
||||
SOURCES = main.c hal.c
|
||||
SOURCES += cmsis_f7/Source/Templates/gcc/startup_stm32f746xx.s
|
||||
|
||||
TOP = ../../../..
|
||||
CFLAGS += -I$(TOP)
|
||||
SOURCES += $(TOP)/mongoose.c
|
||||
|
||||
all: firmware.bin
|
||||
|
||||
firmware.elf: cmsis_core cmsis_f7 hal.h link.ld Makefile $(SOURCES)
|
||||
arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(CFLAGS_EXTRA) $(LDFLAGS) -o $@
|
||||
|
||||
firmware.bin: firmware.elf
|
||||
arm-none-eabi-objcopy -O binary $< $@
|
||||
@echo
|
||||
@echo "To flash, run 'make flash', or use STM32CubeProgrammer"
|
||||
|
||||
flash: firmware.bin
|
||||
STM32_Programmer_CLI -c port=swd -e all -w firmware.elf -hardRst
|
||||
|
||||
cmsis_core:
|
||||
git clone -q -c advice.detachedHead=false --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
|
||||
|
||||
cmsis_f7:
|
||||
git clone -q -c advice.detachedHead=false --depth 1 -b v1.2.8 https://github.com/STMicroelectronics/cmsis_device_f7 $@
|
||||
|
||||
clean:
|
||||
rm -rf firmware.*
|
||||
@@ -0,0 +1,125 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now) {
|
||||
uint64_t diff = now - *t; // Wrap-safe elapsed time since last expiry
|
||||
if (period == 0) return false; // Avoid division by zero
|
||||
if (diff < period) return false; // Period has not elapsed yet
|
||||
*t += (diff / period) * period; // Preserve cadence, skip missed periods
|
||||
return true;
|
||||
}
|
||||
|
||||
static volatile uint64_t s_ticks; // Milliseconds since boot
|
||||
void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
|
||||
s_ticks++;
|
||||
}
|
||||
|
||||
uint64_t hal_get_tick(void) {
|
||||
return s_ticks;
|
||||
};
|
||||
|
||||
uint32_t SystemCoreClock = SYS_FREQUENCY;
|
||||
void SystemInit(void) { // Called automatically by startup code
|
||||
hal_system_init(); // Enable FPU
|
||||
hal_clock_init();
|
||||
SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
|
||||
}
|
||||
|
||||
void ExitRun0Mode(void) {
|
||||
}
|
||||
|
||||
struct stat;
|
||||
__attribute__((weak)) int _fstat(int fd, struct stat *st) {
|
||||
(void) fd, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
extern unsigned char _end[]; // End of data section, start of heap. See link.ld
|
||||
static unsigned char *s_current_heap_end = _end;
|
||||
|
||||
size_t hal_ram_used(void) {
|
||||
return (size_t) (s_current_heap_end - _end);
|
||||
}
|
||||
|
||||
size_t hal_ram_free(void) {
|
||||
unsigned char endofstack;
|
||||
return (size_t) (&endofstack - s_current_heap_end);
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
unsigned char *prev_heap;
|
||||
unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
|
||||
prev_heap = s_current_heap_end;
|
||||
// Check how much space we got from the heap end to the stack end
|
||||
if (s_current_heap_end + incr > heap_end) return (void *) -1;
|
||||
s_current_heap_end += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int mkdir(const char *path, int mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _init(void) {
|
||||
}
|
||||
@@ -0,0 +1,181 @@
|
||||
// Copyright (c) 2022-2024 Cesanta Software Limited
|
||||
// https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
|
||||
// https://www.st.com/resource/en/datasheet/stm32f746zg.pdf
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stm32f746xx.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
extern bool hal_timer_expired(volatile uint64_t *t, uint64_t prd, uint64_t now);
|
||||
extern uint64_t hal_get_tick(void);
|
||||
extern size_t hal_ram_free(void);
|
||||
extern size_t hal_ram_used(void);
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
#define HAL_ETH_PINS \
|
||||
PIN('A', 1), /* ETH_REF_CLK */ \
|
||||
PIN('A', 2), /* ETH_MDIO */ \
|
||||
PIN('A', 7), /* ETH_CRS_DV */ \
|
||||
PIN('B', 13), /* ETH_TXD1 */ \
|
||||
PIN('C', 1), /* ETH_MDC */ \
|
||||
PIN('C', 4), /* ETH_RXD0 */ \
|
||||
PIN('C', 5), /* ETH_RXD1 */ \
|
||||
PIN('G', 11), /* ETH_TX_EN */ \
|
||||
PIN('G', 13) /* ETH_TXD0 */
|
||||
|
||||
#define BIT(x) (1UL << (x))
|
||||
#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
|
||||
#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
|
||||
#define PINNO(pin) (pin & 255)
|
||||
#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
void hal_init(void);
|
||||
size_t hal_ram_free(void);
|
||||
size_t hal_ram_used(void);
|
||||
|
||||
/* System clock
|
||||
5.3.3: APB1 clock <= 54MHz; APB2 clock <= 108MHz
|
||||
3.3.2, Table 5: configure flash latency (WS) in accordance to clock freq
|
||||
38.4: The AHB clock frequency must be at least 25 MHz when the Ethernet
|
||||
controller is used */
|
||||
enum { HAL_APB1_PRE = 5 /* AHB clock / 4 */, HAL_APB2_PRE = 4 /* AHB clock / 2 */ };
|
||||
enum { PLL_HSI = 16, PLL_M = 8, PLL_N = 216, PLL_P = 2 }; // Run at 216 Mhz
|
||||
#define FLASH_LATENCY 7
|
||||
#define SYS_FREQUENCY ((PLL_HSI * PLL_N / PLL_M / PLL_P) * 1000000)
|
||||
#define APB2_FREQUENCY (SYS_FREQUENCY / (BIT(HAL_APB2_PRE - 3)))
|
||||
#define APB1_FREQUENCY (SYS_FREQUENCY / (BIT(HAL_APB1_PRE - 3)))
|
||||
|
||||
enum { HAL_GPIO_MODE_INPUT, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_MODE_AF, HAL_GPIO_MODE_ANALOG };
|
||||
enum { HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_OTYPE_OPEN_DRAIN };
|
||||
enum { HAL_GPIO_SPEED_LOW, HAL_GPIO_SPEED_MEDIUM, HAL_GPIO_SPEED_HIGH, HAL_GPIO_SPEED_INSANE };
|
||||
enum { HAL_GPIO_PULL_NONE, HAL_GPIO_PULL_UP, HAL_GPIO_PULL_DOWN };
|
||||
#define HAL_GPIO(N) ((GPIO_TypeDef *) (0x40020000 + 0x400 * (N)))
|
||||
|
||||
static GPIO_TypeDef *hal_gpio_bank(uint16_t pin) {
|
||||
return HAL_GPIO(PINBANK(pin));
|
||||
}
|
||||
static inline void hal_gpio_toggle(uint16_t pin) {
|
||||
GPIO_TypeDef *gpio = hal_gpio_bank(pin);
|
||||
uint32_t mask = BIT(PINNO(pin));
|
||||
gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
|
||||
}
|
||||
static inline int hal_gpio_read(uint16_t pin) {
|
||||
return hal_gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
|
||||
}
|
||||
static inline void hal_gpio_write(uint16_t pin, bool val) {
|
||||
GPIO_TypeDef *gpio = hal_gpio_bank(pin);
|
||||
gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
|
||||
}
|
||||
static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
uint8_t speed, uint8_t pull, uint8_t af) {
|
||||
GPIO_TypeDef *gpio = hal_gpio_bank(pin);
|
||||
uint8_t n = (uint8_t) (PINNO(pin));
|
||||
RCC->AHB1ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
|
||||
CLRSET(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
|
||||
CLRSET(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
|
||||
CLRSET(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
|
||||
CLRSET(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
|
||||
((uint32_t) af) << ((n & 7) * 4));
|
||||
CLRSET(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
|
||||
}
|
||||
static inline void hal_gpio_input(uint16_t pin) {
|
||||
hal_gpio_init(pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH,
|
||||
HAL_GPIO_PULL_NONE, 0);
|
||||
}
|
||||
static inline void hal_gpio_output(uint16_t pin) {
|
||||
hal_gpio_init(pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH,
|
||||
HAL_GPIO_PULL_NONE, 0);
|
||||
}
|
||||
|
||||
static inline void hal_irq_exti_attach(uint16_t pin) {
|
||||
uint8_t bank = (uint8_t) (PINBANK(pin)), n = (uint8_t) (PINNO(pin));
|
||||
SYSCFG->EXTICR[n / 4] &= ~(15UL << ((n % 4) * 4));
|
||||
SYSCFG->EXTICR[n / 4] |= (uint32_t) (bank << ((n % 4) * 4));
|
||||
EXTI->IMR |= BIT(n);
|
||||
EXTI->RTSR |= BIT(n);
|
||||
EXTI->FTSR |= BIT(n);
|
||||
int irqvec = n < 5 ? 6 + n : n < 10 ? 23 : 40; // IRQ vector index, 10.1.2
|
||||
NVIC_SetPriority(irqvec, 3);
|
||||
NVIC_EnableIRQ(irqvec);
|
||||
}
|
||||
|
||||
static inline void hal_uart_init(USART_TypeDef *uart, unsigned long baud) {
|
||||
uint8_t af = 7; // Alternate function
|
||||
uint16_t rx = 0, tx = 0; // pins
|
||||
uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
|
||||
|
||||
if (uart == USART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
|
||||
if (uart == USART2) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(17);
|
||||
if (uart == USART3) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(18);
|
||||
|
||||
if (uart == USART1) tx = PIN('A', 9), rx = PIN('A', 10);
|
||||
if (uart == USART2) tx = PIN('A', 2), rx = PIN('A', 3);
|
||||
if (uart == USART3) tx = PIN('D', 8), rx = PIN('D', 9);
|
||||
|
||||
hal_gpio_init(tx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af);
|
||||
hal_gpio_init(rx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af);
|
||||
uart->CR1 = 0; // Disable this UART
|
||||
uart->BRR = freq / baud; // Set baud rate
|
||||
uart->CR1 |= BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
|
||||
}
|
||||
static inline void hal_uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
|
||||
uart->TDR = byte;
|
||||
while ((uart->ISR & BIT(7)) == 0) (void) 0;
|
||||
}
|
||||
static inline void hal_uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) hal_uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int hal_uart_read_ready(USART_TypeDef *uart) {
|
||||
return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
|
||||
}
|
||||
static inline uint8_t hal_uart_read_byte(USART_TypeDef *uart) {
|
||||
return (uint8_t) (uart->RDR & 255);
|
||||
}
|
||||
|
||||
static inline void hal_rng_init(void) {
|
||||
RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;
|
||||
RNG->CR |= RNG_CR_RNGEN;
|
||||
}
|
||||
static inline uint32_t hal_rng_read(void) {
|
||||
while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
|
||||
return RNG->DR;
|
||||
}
|
||||
|
||||
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
|
||||
static inline void hal_ethernet_init(void) {
|
||||
// Initialise Ethernet. Enable MAC GPIO pins, see
|
||||
// https://www.farnell.com/datasheets/2014265.pdf section 6.10
|
||||
uint16_t pins[] = {HAL_ETH_PINS};
|
||||
for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
|
||||
hal_gpio_init(pins[i], HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_INSANE,
|
||||
HAL_GPIO_PULL_NONE, 11); // 11 is the Ethernet function
|
||||
}
|
||||
NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
|
||||
SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL; // Use RMII. Goes first!
|
||||
RCC->AHB1ENR |=
|
||||
RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | RCC_AHB1ENR_ETHMACRXEN;
|
||||
}
|
||||
|
||||
static inline void hal_clock_init(void) {
|
||||
FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9); // Flash latency, prefetch
|
||||
RCC->PLLCFGR &= ~((BIT(17) - 1)); // Clear PLL multipliers
|
||||
RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16; // Set PLL_P
|
||||
RCC->PLLCFGR |= PLL_M | (PLL_N << 6); // Set PLL_M and PLL_N
|
||||
RCC->CR |= BIT(24); // Enable PLL
|
||||
while ((RCC->CR & BIT(25)) == 0) (void) 0; // Wait until done
|
||||
RCC->CFGR = (HAL_APB1_PRE << 10) | (HAL_APB2_PRE << 13); // Set prescalers
|
||||
RCC->CFGR |= 2; // Set clock source to PLL
|
||||
while ((RCC->CFGR & 12) == 0) (void) 0; // Wait until done
|
||||
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; // Enable SYSCFG
|
||||
}
|
||||
|
||||
static inline void hal_system_init(void) {
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
@@ -0,0 +1,26 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash(rx) : ORIGIN = 0x08000000, LENGTH = 1024k
|
||||
sram(rwx) : ORIGIN = 0x20000000, LENGTH = 320k
|
||||
}
|
||||
_estack = ORIGIN(sram) + LENGTH(sram); /* stack points to end of SRAM */
|
||||
|
||||
SECTIONS {
|
||||
.vectors : { KEEP(*(.isr_vector)) } > flash
|
||||
.text : { *(.text* .text.*) } > flash
|
||||
.rodata : { *(.rodata*) } > flash
|
||||
|
||||
.data : {
|
||||
_sdata = .;
|
||||
*(.first_data)
|
||||
*(.data SORT(.data.*))
|
||||
*(.iram .iram* .iram.*)
|
||||
_edata = .;
|
||||
} > sram AT > flash
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : { _sbss = .; *(.bss SORT(.bss.*) COMMON) _ebss = .; } > sram
|
||||
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
}
|
||||
@@ -0,0 +1,70 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "mongoose.h"
|
||||
#include "hal.h"
|
||||
|
||||
#define DEBUG_UART USART3
|
||||
#define LED1 PIN('B', 0)
|
||||
#define LED2 PIN('B', 7)
|
||||
#define LED3 PIN('B', 14)
|
||||
|
||||
// Redirect stdout debug output to UART
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
if (fd == 1 || fd == 2) hal_uart_write_buf(DEBUG_UART, ptr, (size_t) len);
|
||||
return len;
|
||||
}
|
||||
|
||||
static void blink_task(void) {
|
||||
static uint64_t blink_timer = 0;
|
||||
if (hal_timer_expired(&blink_timer, 500, hal_get_tick())) {
|
||||
hal_gpio_toggle(LED1);
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t mg_millis(void) {
|
||||
return hal_get_tick();
|
||||
}
|
||||
|
||||
bool mg_random(void *buf, size_t len) {
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = hal_rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) {
|
||||
if (ev == MG_EV_HTTP_MSG) { // New HTTP request received
|
||||
struct mg_http_message *hm = (struct mg_http_message *) ev_data;
|
||||
if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) {
|
||||
mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), hal_get_tick());
|
||||
} else {
|
||||
mg_http_reply(c, 200, "", "Hi from Mongoose, tick %llu\n",
|
||||
hal_get_tick());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
hal_clock_init();
|
||||
hal_rng_init();
|
||||
hal_gpio_output(LED1);
|
||||
hal_gpio_output(LED2);
|
||||
hal_gpio_output(LED3);
|
||||
hal_uart_init(DEBUG_UART, 115200);
|
||||
|
||||
hal_ethernet_init();
|
||||
|
||||
// Start a minimal web server
|
||||
struct mg_mgr mgr;
|
||||
mg_mgr_init(&mgr);
|
||||
mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL);
|
||||
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
blink_task();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,42 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_ARMGCC
|
||||
#define MG_TLS MG_TLS_BUILTIN
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_DRIVER_STM32F 1
|
||||
#define MG_OTA MG_OTA_STM32F
|
||||
|
||||
// #define MG_DRIVER_MDC_CR 4 // RMII MDC clock divider, from 0 to 4
|
||||
// #define MG_TCPIP_PHY_ADDR 0 // PHY address
|
||||
|
||||
// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
|
||||
// By default, those are set to zero, meaning that DHCP is used
|
||||
//
|
||||
// #define MG_TCPIP_IP MG_IPV4(192, 168, 0, 10)
|
||||
// #define MG_TCPIP_GW MG_IPV4(192, 168, 0, 1)
|
||||
// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0)
|
||||
|
||||
// Set custom MAC address. By default, it is randomly generated
|
||||
// Using a build-time constant:
|
||||
// #define MG_SET_MAC_ADDRESS(mac) do { mac[0] = 2; mac[1] = 3; mac[2] = 4; mac[3] = 5; mac[4] = 6; mac[5] = 7; } while (0)
|
||||
//
|
||||
// Using custom function:
|
||||
// extern void my_function(unsigned char *mac);
|
||||
// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)
|
||||
|
||||
// Construct MAC address from the MCU unique ID. It is defined in the
|
||||
// ST CMSIS header as UID_BASE
|
||||
#define MGUID ((uint32_t *) 0x1ff0f420) // Unique 96-bit chip ID
|
||||
#define MG_SET_MAC_ADDRESS(mac) \
|
||||
do { \
|
||||
mac[0] = 2; \
|
||||
mac[1] = MGUID[0] & 255; \
|
||||
mac[2] = (MGUID[0] >> 10) & 255; \
|
||||
mac[3] = (MGUID[0] >> 19) & 255; \
|
||||
mac[4] = MGUID[1] & 255; \
|
||||
mac[5] = MGUID[2] & 255; \
|
||||
} while (0)
|
||||
@@ -0,0 +1,30 @@
|
||||
# Nucleo-H743ZI Mongoose Integration
|
||||
|
||||
This guide explains how to bring up a production-grade Web UI dashboard on the
|
||||
STM32 Nucleo-H743ZI development board.
|
||||
|
||||
A pre-configured, ready-to-run project zip is available for download at
|
||||
https://mongoose.ws.
|
||||
|
||||
To integrate the Web UI dashboard into an existing CubeMX project, or to create a
|
||||
new project from scratch:
|
||||
|
||||
1. Configure the peripherals (described below).
|
||||
2. Regenerate your project code and integrate Mongoose core by following
|
||||
https://mongoose.ws/docs/guides/stm32-tcpip-stack/.
|
||||
3. Add the Web UI dashboard by following
|
||||
https://mongoose.ws/docs/guides/web-dashboard-guide/.
|
||||
|
||||
## Configure peripherals
|
||||
|
||||
An `.ioc` file is included in this directory for your reference. It was created
|
||||
using the following steps:
|
||||
|
||||
- Open CubeMX. If you are starting a new project, select the STM32H743ZI
|
||||
microcontroller and create a new project.
|
||||
- In Clock Configuration, set the maximum clock frequency to 480 MHz.
|
||||
- In the MCU pinout view, set pins PB0, PE1, and PB14 to GPIO_Output mode.
|
||||
- In Pinout & Configuration / Connectivity, enable USART3 in asynchronous mode.
|
||||
Configure pins PD8 and PD9 for USART.
|
||||
- In Pinout & Configuration / Connectivity, enable ETH in RMII mode and set pins
|
||||
PA1, PA2, PA7, PC1, PC4, PC5, PB13, PG11, and PG13 for Ethernet.
|
||||
@@ -0,0 +1,212 @@
|
||||
#MicroXplorer Configuration settings - do not modify
|
||||
CAD.formats=
|
||||
CAD.pinconfig=
|
||||
CAD.provider=
|
||||
CORTEX_M7.DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_INSTRUCTION_ACCESS_DISABLE
|
||||
CORTEX_M7.Enable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_ENABLE
|
||||
CORTEX_M7.IPParameters=MPU_Control,Enable-Cortex_Memory_Protection_Unit_Region0_Settings,Size-Cortex_Memory_Protection_Unit_Region0_Settings,SubRegionDisable-Cortex_Memory_Protection_Unit_Region0_Settings,DisableExec-Cortex_Memory_Protection_Unit_Region0_Settings,IsShareable-Cortex_Memory_Protection_Unit_Region0_Settings
|
||||
CORTEX_M7.IsShareable-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_ACCESS_SHAREABLE
|
||||
CORTEX_M7.MPU_Control=MPU_PRIVILEGED_DEFAULT
|
||||
CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_SIZE_4GB
|
||||
CORTEX_M7.SubRegionDisable-Cortex_Memory_Protection_Unit_Region0_Settings=0x87
|
||||
ETH.IPParameters=MediaInterface
|
||||
ETH.MediaInterface=HAL_ETH_RMII_MODE
|
||||
File.Version=6
|
||||
GPIO.groupedBy=Group By Peripherals
|
||||
KeepUserPlacement=false
|
||||
Mcu.CPN=STM32H743ZIT6
|
||||
Mcu.Family=STM32H7
|
||||
Mcu.IP0=CORTEX_M7
|
||||
Mcu.IP1=ETH
|
||||
Mcu.IP2=NVIC
|
||||
Mcu.IP3=RCC
|
||||
Mcu.IP4=RNG
|
||||
Mcu.IP5=SYS
|
||||
Mcu.IP6=USART3
|
||||
Mcu.IPNb=7
|
||||
Mcu.Name=STM32H743ZITx
|
||||
Mcu.Package=LQFP144
|
||||
Mcu.Pin0=PC1
|
||||
Mcu.Pin1=PA1
|
||||
Mcu.Pin10=PD9
|
||||
Mcu.Pin11=PG11
|
||||
Mcu.Pin12=PG13
|
||||
Mcu.Pin13=PE1
|
||||
Mcu.Pin14=VP_RNG_VS_RNG
|
||||
Mcu.Pin15=VP_SYS_VS_Systick
|
||||
Mcu.Pin2=PA2
|
||||
Mcu.Pin3=PA7
|
||||
Mcu.Pin4=PC4
|
||||
Mcu.Pin5=PC5
|
||||
Mcu.Pin6=PB0
|
||||
Mcu.Pin7=PB13
|
||||
Mcu.Pin8=PB14
|
||||
Mcu.Pin9=PD8
|
||||
Mcu.PinsNb=16
|
||||
Mcu.ThirdPartyNb=0
|
||||
Mcu.UserConstants=
|
||||
Mcu.UserName=STM32H743ZITx
|
||||
MxCube.Version=6.17.0
|
||||
MxDb.Version=DB.6.0.170
|
||||
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
NVIC.ETH_IRQn=true\:0\:0\:false\:false\:false\:true\:false\:true
|
||||
NVIC.ForceEnableDMAVector=true
|
||||
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
|
||||
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
|
||||
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
PA1.Mode=RMII
|
||||
PA1.Signal=ETH_REF_CLK
|
||||
PA2.Mode=RMII
|
||||
PA2.Signal=ETH_MDIO
|
||||
PA7.Mode=RMII
|
||||
PA7.Signal=ETH_CRS_DV
|
||||
PB0.Locked=true
|
||||
PB0.Signal=GPIO_Output
|
||||
PB13.Mode=RMII
|
||||
PB13.Signal=ETH_TXD1
|
||||
PB14.Locked=true
|
||||
PB14.Signal=GPIO_Output
|
||||
PC1.Mode=RMII
|
||||
PC1.Signal=ETH_MDC
|
||||
PC4.Mode=RMII
|
||||
PC4.Signal=ETH_RXD0
|
||||
PC5.Mode=RMII
|
||||
PC5.Signal=ETH_RXD1
|
||||
PD8.Locked=true
|
||||
PD8.Mode=Asynchronous
|
||||
PD8.Signal=USART3_TX
|
||||
PD9.Locked=true
|
||||
PD9.Mode=Asynchronous
|
||||
PD9.Signal=USART3_RX
|
||||
PE1.Locked=true
|
||||
PE1.Signal=GPIO_Output
|
||||
PG11.Locked=true
|
||||
PG11.Mode=RMII
|
||||
PG11.Signal=ETH_TX_EN
|
||||
PG13.Locked=true
|
||||
PG13.Mode=RMII
|
||||
PG13.Signal=ETH_TXD0
|
||||
PinOutPanel.RotationAngle=0
|
||||
ProjectManager.AskForMigrate=true
|
||||
ProjectManager.BackupPrevious=false
|
||||
ProjectManager.CompilerLinker=GCC
|
||||
ProjectManager.CompilerOptimize=6
|
||||
ProjectManager.ComputerToolchain=false
|
||||
ProjectManager.CoupleFile=false
|
||||
ProjectManager.CustomerFirmwarePackage=
|
||||
ProjectManager.DefaultFWLocation=true
|
||||
ProjectManager.DeletePrevious=true
|
||||
ProjectManager.DeviceId=STM32H743ZITx
|
||||
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.13.0
|
||||
ProjectManager.FreePins=false
|
||||
ProjectManager.FreePinsContext=
|
||||
ProjectManager.HalAssertFull=false
|
||||
ProjectManager.HeapSize=0x10000
|
||||
ProjectManager.KeepUserCode=true
|
||||
ProjectManager.LastFirmware=true
|
||||
ProjectManager.LibraryCopy=1
|
||||
ProjectManager.MainLocation=Core/Src
|
||||
ProjectManager.NoMain=false
|
||||
ProjectManager.PreviousToolchain=STM32CubeIDE
|
||||
ProjectManager.ProjectBuild=false
|
||||
ProjectManager.ProjectFileName=nucleo_h743zi.ioc
|
||||
ProjectManager.ProjectName=nucleo_h743zi
|
||||
ProjectManager.ProjectStructure=
|
||||
ProjectManager.RegisterCallBack=
|
||||
ProjectManager.StackSize=0x2000
|
||||
ProjectManager.TargetToolchain=CMake
|
||||
ProjectManager.ToolChainLocation=
|
||||
ProjectManager.UAScriptAfterPath=
|
||||
ProjectManager.UAScriptBeforePath=
|
||||
ProjectManager.UnderRoot=false
|
||||
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ETH_Init-ETH-false-HAL-true,4-MX_RNG_Init-RNG-false-HAL-true,5-MX_USART3_UART_Init-USART3-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
|
||||
RCC.ADCFreq_Value=129000000
|
||||
RCC.AHB12Freq_Value=240000000
|
||||
RCC.AHB4Freq_Value=240000000
|
||||
RCC.APB1Freq_Value=120000000
|
||||
RCC.APB2Freq_Value=120000000
|
||||
RCC.APB3Freq_Value=120000000
|
||||
RCC.APB4Freq_Value=120000000
|
||||
RCC.AXIClockFreq_Value=240000000
|
||||
RCC.CECFreq_Value=32000
|
||||
RCC.CKPERFreq_Value=64000000
|
||||
RCC.CortexFreq_Value=480000000
|
||||
RCC.CpuClockFreq_Value=480000000
|
||||
RCC.D1CPREFreq_Value=480000000
|
||||
RCC.D1PPRE=RCC_APB3_DIV2
|
||||
RCC.D2PPRE1=RCC_APB1_DIV2
|
||||
RCC.D2PPRE2=RCC_APB2_DIV2
|
||||
RCC.D3PPRE=RCC_APB4_DIV2
|
||||
RCC.DFSDMACLkFreq_Value=480000000
|
||||
RCC.DFSDMFreq_Value=120000000
|
||||
RCC.DIVM1=4
|
||||
RCC.DIVN1=60
|
||||
RCC.DIVP1Freq_Value=480000000
|
||||
RCC.DIVP2Freq_Value=129000000
|
||||
RCC.DIVP3Freq_Value=129000000
|
||||
RCC.DIVQ1Freq_Value=480000000
|
||||
RCC.DIVQ2Freq_Value=129000000
|
||||
RCC.DIVQ3Freq_Value=129000000
|
||||
RCC.DIVR1Freq_Value=480000000
|
||||
RCC.DIVR2Freq_Value=129000000
|
||||
RCC.DIVR3Freq_Value=129000000
|
||||
RCC.FDCANFreq_Value=480000000
|
||||
RCC.FMCFreq_Value=240000000
|
||||
RCC.FamilyName=M
|
||||
RCC.HCLK3ClockFreq_Value=240000000
|
||||
RCC.HCLKFreq_Value=240000000
|
||||
RCC.HPRE=RCC_HCLK_DIV2
|
||||
RCC.HRTIMFreq_Value=240000000
|
||||
RCC.I2C123Freq_Value=120000000
|
||||
RCC.I2C4Freq_Value=120000000
|
||||
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
|
||||
RCC.LPTIM1Freq_Value=120000000
|
||||
RCC.LPTIM2Freq_Value=120000000
|
||||
RCC.LPTIM345Freq_Value=120000000
|
||||
RCC.LPUART1Freq_Value=120000000
|
||||
RCC.LTDCFreq_Value=129000000
|
||||
RCC.MCO1PinFreq_Value=64000000
|
||||
RCC.MCO2PinFreq_Value=480000000
|
||||
RCC.PLL2FRACN=0
|
||||
RCC.PLL3FRACN=0
|
||||
RCC.PLLFRACN=0
|
||||
RCC.QSPIFreq_Value=240000000
|
||||
RCC.RNGFreq_Value=48000000
|
||||
RCC.RTCFreq_Value=32000
|
||||
RCC.SAI1Freq_Value=480000000
|
||||
RCC.SAI23Freq_Value=480000000
|
||||
RCC.SAI4AFreq_Value=480000000
|
||||
RCC.SAI4BFreq_Value=480000000
|
||||
RCC.SDMMCFreq_Value=480000000
|
||||
RCC.SPDIFRXFreq_Value=480000000
|
||||
RCC.SPI123Freq_Value=480000000
|
||||
RCC.SPI45Freq_Value=120000000
|
||||
RCC.SPI6Freq_Value=120000000
|
||||
RCC.SWPMI1Freq_Value=120000000
|
||||
RCC.SYSCLKFreq_VALUE=480000000
|
||||
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
|
||||
RCC.Tim1OutputFreq_Value=240000000
|
||||
RCC.Tim2OutputFreq_Value=240000000
|
||||
RCC.TraceFreq_Value=64000000
|
||||
RCC.USART16Freq_Value=120000000
|
||||
RCC.USART234578Freq_Value=120000000
|
||||
RCC.USBFreq_Value=480000000
|
||||
RCC.VCO1OutputFreq_Value=960000000
|
||||
RCC.VCO2OutputFreq_Value=258000000
|
||||
RCC.VCO3OutputFreq_Value=258000000
|
||||
RCC.VCOInput1Freq_Value=16000000
|
||||
RCC.VCOInput2Freq_Value=2000000
|
||||
RCC.VCOInput3Freq_Value=2000000
|
||||
USART3.IPParameters=VirtualMode-Asynchronous
|
||||
USART3.VirtualMode-Asynchronous=VM_ASYNC
|
||||
VP_RNG_VS_RNG.Mode=RNG_Activate
|
||||
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
|
||||
VP_SYS_VS_Systick.Mode=SysTick
|
||||
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
|
||||
board=custom
|
||||
@@ -0,0 +1,38 @@
|
||||
# Copyright (c) 2026 Cesanta Software Limited
|
||||
# Environment setup: https://mongoose.ws/docs/getting-started/build-environment/
|
||||
|
||||
CFLAGS = -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion
|
||||
CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
|
||||
CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
|
||||
CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_h7/Include
|
||||
CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA)
|
||||
LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nosys.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
|
||||
|
||||
SOURCES = main.c hal.c
|
||||
SOURCES += cmsis_h7/Source/Templates/gcc/startup_stm32h743xx.s
|
||||
|
||||
TOP = ../../../..
|
||||
CFLAGS += -I$(TOP)
|
||||
SOURCES += $(TOP)/mongoose.c
|
||||
|
||||
all: firmware.bin
|
||||
|
||||
firmware.elf: cmsis_core cmsis_h7 hal.h link.ld Makefile $(SOURCES)
|
||||
arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(CFLAGS_EXTRA) $(LDFLAGS) -o $@
|
||||
|
||||
firmware.bin: firmware.elf
|
||||
arm-none-eabi-objcopy -O binary $< $@
|
||||
@echo
|
||||
@echo "To flash, run 'make flash', or use STM32CubeProgrammer"
|
||||
|
||||
flash: firmware.bin
|
||||
STM32_Programmer_CLI -c port=swd -e all -w firmware.elf -hardRst
|
||||
|
||||
cmsis_core:
|
||||
git clone -q -c advice.detachedHead=false --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
|
||||
|
||||
cmsis_h7:
|
||||
git clone -q -c advice.detachedHead=false --depth 1 -b v1.10.4 https://github.com/STMicroelectronics/cmsis_device_h7 $@
|
||||
|
||||
clean:
|
||||
rm -rf firmware.*
|
||||
@@ -0,0 +1,125 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now) {
|
||||
uint64_t diff = now - *t; // Wrap-safe elapsed time since last expiry
|
||||
if (period == 0) return false; // Avoid division by zero
|
||||
if (diff < period) return false; // Period has not elapsed yet
|
||||
*t += (diff / period) * period; // Preserve cadence, skip missed periods
|
||||
return true;
|
||||
}
|
||||
|
||||
static volatile uint64_t s_ticks; // Milliseconds since boot
|
||||
void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
|
||||
s_ticks++;
|
||||
}
|
||||
|
||||
uint64_t hal_get_tick(void) {
|
||||
return s_ticks;
|
||||
};
|
||||
|
||||
uint32_t SystemCoreClock = SYS_FREQUENCY;
|
||||
void SystemInit(void) { // Called automatically by startup code
|
||||
hal_system_init(); // Enable FPU
|
||||
hal_clock_init();
|
||||
SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
|
||||
}
|
||||
|
||||
void ExitRun0Mode(void) {
|
||||
}
|
||||
|
||||
struct stat;
|
||||
__attribute__((weak)) int _fstat(int fd, struct stat *st) {
|
||||
(void) fd, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
extern unsigned char _end[]; // End of data section, start of heap. See link.ld
|
||||
static unsigned char *s_current_heap_end = _end;
|
||||
|
||||
size_t hal_ram_used(void) {
|
||||
return (size_t) (s_current_heap_end - _end);
|
||||
}
|
||||
|
||||
size_t hal_ram_free(void) {
|
||||
unsigned char endofstack;
|
||||
return (size_t) (&endofstack - s_current_heap_end);
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
unsigned char *prev_heap;
|
||||
unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
|
||||
prev_heap = s_current_heap_end;
|
||||
// Check how much space we got from the heap end to the stack end
|
||||
if (s_current_heap_end + incr > heap_end) return (void *) -1;
|
||||
s_current_heap_end += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int mkdir(const char *path, int mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _init(void) {
|
||||
}
|
||||
@@ -0,0 +1,269 @@
|
||||
// Copyright (c) 2022-2024 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// Datasheet: RM0433, devboard manual: UM2407
|
||||
// https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
|
||||
// Alternate functions: https://www.st.com/resource/en/datasheet/stm32h743vi.pdf
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stm32h743xx.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
extern bool hal_timer_expired(volatile uint64_t *t, uint64_t prd, uint64_t now);
|
||||
extern uint64_t hal_get_tick(void);
|
||||
extern size_t hal_ram_free(void);
|
||||
extern size_t hal_ram_used(void);
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
#define HAL_ETH_PINS \
|
||||
PIN('A', 1), /* ETH_REF_CLK */ \
|
||||
PIN('A', 2), /* ETH_MDIO */ \
|
||||
PIN('A', 7), /* ETH_CRS_DV */ \
|
||||
PIN('B', 13), /* ETH_TXD1 */ \
|
||||
PIN('C', 1), /* ETH_MDC */ \
|
||||
PIN('C', 4), /* ETH_RXD0 */ \
|
||||
PIN('C', 5), /* ETH_RXD1 */ \
|
||||
PIN('G', 11), /* ETH_TX_EN */ \
|
||||
PIN('G', 13) /* ETH_TXD0 */
|
||||
|
||||
#define BIT(x) (1UL << (x))
|
||||
#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
|
||||
#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
|
||||
#define PINNO(pin) (pin & 255)
|
||||
#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
void hal_init(void);
|
||||
size_t hal_ram_free(void);
|
||||
size_t hal_ram_used(void);
|
||||
|
||||
// System clock (2.1, Figure 1; 8.5, Figure 45; 8.5.5, Figure 47; 8.5.6, Figure
|
||||
// 49) SYS_FREQUENCY <= 480 MHz; hclk = SYS_FREQUENCY / HAL_HPRE ; hclk <= 240 MHz;
|
||||
// APB clocks <= 120 MHz. D1 domain bus matrix (and so flash) runs at hclk
|
||||
// frequency. Configure flash latency (WS) in accordance to hclk freq (4.3.8,
|
||||
// Table 17) The Ethernet controller is in D2 domain and runs at hclk frequency
|
||||
enum {
|
||||
HAL_D1CPRE = 1, // actual divisor value
|
||||
HAL_HPRE = 2, // actual divisor value
|
||||
HAL_D1PPRE = 4, // register values, divisor value = BIT(value - 3) = / 2
|
||||
HAL_D2PPRE1 = 4,
|
||||
HAL_D2PPRE2 = 4,
|
||||
HAL_D3PPRE = 4
|
||||
};
|
||||
// PLL1_P: odd division factors are not allowed (8.7.13) (according to Cube, '1'
|
||||
// is also an "odd division factor").
|
||||
// Make sure your chip is revision 'V', otherwise set PLL1_N = 400
|
||||
enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 480, PLL1_P = 2 };
|
||||
#define FLASH_LATENCY 0x24 // WRHIGHFREQ LATENCY
|
||||
#define SYS_FREQUENCY ((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / HAL_D1CPRE) * 1000000)
|
||||
// #define SYS_FREQUENCY ((PLL1_HSI / HAL_D1CPRE) * 1000000)
|
||||
#define AHB_FREQUENCY (SYS_FREQUENCY / HAL_HPRE)
|
||||
#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(HAL_D2PPRE2 - 3)))
|
||||
#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(HAL_D2PPRE1 - 3)))
|
||||
|
||||
static inline void spin(volatile uint32_t n) {
|
||||
while (n--) (void) 0;
|
||||
}
|
||||
|
||||
enum { HAL_GPIO_MODE_INPUT, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_MODE_AF, HAL_GPIO_MODE_ANALOG };
|
||||
enum { HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_OTYPE_OPEN_DRAIN };
|
||||
enum { HAL_GPIO_SPEED_LOW, HAL_GPIO_SPEED_MEDIUM, HAL_GPIO_SPEED_HIGH, HAL_GPIO_SPEED_INSANE };
|
||||
enum { HAL_GPIO_PULL_NONE, HAL_GPIO_PULL_UP, HAL_GPIO_PULL_DOWN };
|
||||
|
||||
#define HAL_GPIO(N) ((GPIO_TypeDef *) (0x40000000 + 0x18020000UL + 0x400 * (N)))
|
||||
|
||||
static GPIO_TypeDef *hal_gpio_bank(uint16_t pin) {
|
||||
return HAL_GPIO(PINBANK(pin));
|
||||
}
|
||||
static inline void hal_gpio_toggle(uint16_t pin) {
|
||||
GPIO_TypeDef *gpio = hal_gpio_bank(pin);
|
||||
uint32_t mask = BIT(PINNO(pin));
|
||||
gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
|
||||
}
|
||||
static inline int hal_gpio_read(uint16_t pin) {
|
||||
return hal_gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
|
||||
}
|
||||
static inline void hal_gpio_write(uint16_t pin, bool val) {
|
||||
GPIO_TypeDef *gpio = hal_gpio_bank(pin);
|
||||
gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
|
||||
}
|
||||
static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
uint8_t speed, uint8_t pull, uint8_t af) {
|
||||
GPIO_TypeDef *gpio = hal_gpio_bank(pin);
|
||||
uint8_t n = (uint8_t) (PINNO(pin));
|
||||
RCC->AHB4ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
|
||||
CLRSET(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
|
||||
CLRSET(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
|
||||
CLRSET(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
|
||||
CLRSET(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
|
||||
((uint32_t) af) << ((n & 7) * 4));
|
||||
CLRSET(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
|
||||
}
|
||||
static inline void hal_gpio_input(uint16_t pin) {
|
||||
hal_gpio_init(pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL,
|
||||
HAL_GPIO_SPEED_HIGH, HAL_GPIO_PULL_NONE, 0);
|
||||
}
|
||||
static inline void hal_gpio_output(uint16_t pin) {
|
||||
hal_gpio_init(pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL,
|
||||
HAL_GPIO_SPEED_HIGH, HAL_GPIO_PULL_NONE, 0);
|
||||
}
|
||||
|
||||
static inline uint32_t hal_apb_freq(int bus) { // 1 for APB1 or 2 for APB2
|
||||
uint32_t sysclk = 0, pll_src_freq = 0;
|
||||
uint32_t hsi_freq = 64000000UL, hse_freq = 8000000UL, csi_freq = 4000000UL;
|
||||
uint32_t hclk, hpre_div, apb_div, pllm, plln, pllp, tmp;
|
||||
|
||||
// 1. Determine system clock source
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS) {
|
||||
case RCC_CFGR_SWS_HSI: sysclk = hsi_freq; break;
|
||||
case RCC_CFGR_SWS_CSI: sysclk = csi_freq; break;
|
||||
case RCC_CFGR_SWS_HSE: sysclk = hse_freq; break;
|
||||
case RCC_CFGR_SWS_PLL1:
|
||||
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1_Msk) >>
|
||||
RCC_PLLCKSELR_DIVM1_Pos);
|
||||
plln = ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1_Msk) >> RCC_PLL1DIVR_N1_Pos) + 1;
|
||||
pllp = ((RCC->PLL1DIVR & RCC_PLL1DIVR_P1_Msk) >> RCC_PLL1DIVR_P1_Pos) + 1;
|
||||
if (pllm == 0U) pllm = 1U;
|
||||
|
||||
switch (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) {
|
||||
case RCC_PLLCKSELR_PLLSRC_HSI: pll_src_freq = hsi_freq; break;
|
||||
case RCC_PLLCKSELR_PLLSRC_CSI: pll_src_freq = csi_freq; break;
|
||||
case RCC_PLLCKSELR_PLLSRC_HSE: pll_src_freq = hse_freq; break;
|
||||
default: pll_src_freq = 0U; break;
|
||||
}
|
||||
sysclk = (pll_src_freq / pllm) * plln / pllp;
|
||||
break;
|
||||
default: sysclk = hsi_freq; break;
|
||||
}
|
||||
|
||||
// 2. Compute HCLK (core bus clock) from HPRE prescaler
|
||||
tmp = (RCC->D1CFGR & RCC_D1CFGR_HPRE_Msk) >> RCC_D1CFGR_HPRE_Pos;
|
||||
hpre_div = tmp < 8U ? 1U : (1U << (tmp - 7U));
|
||||
hclk = sysclk / hpre_div;
|
||||
|
||||
// 3. Select the appropriate APB prescaler (from D2CFGR)
|
||||
if (bus == 1)
|
||||
tmp = (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1_Msk) >> RCC_D2CFGR_D2PPRE1_Pos;
|
||||
else
|
||||
tmp = (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2_Msk) >> RCC_D2CFGR_D2PPRE2_Pos;
|
||||
|
||||
apb_div = tmp < 4U ? 1U : (1U << (tmp - 3U));
|
||||
return hclk / apb_div;
|
||||
}
|
||||
|
||||
// D2 Kernel clock (8.7.21) USART1 defaults to pclk2 (APB2), while USART2,3
|
||||
// default to pclk1 (APB1). Even if using other kernel clocks, the APBx clocks
|
||||
// must be enabled for CPU access, as the kernel clock drives the BRR, not the
|
||||
// APB bus interface
|
||||
static inline void hal_uart_init(USART_TypeDef *uart, unsigned long baud) {
|
||||
uint8_t af = 7; // Alternate function
|
||||
uint16_t rx = 0, tx = 0; // pins
|
||||
uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
|
||||
|
||||
if (uart == USART1) freq = hal_apb_freq(2), RCC->APB2ENR |= BIT(4);
|
||||
if (uart == USART2) freq = hal_apb_freq(1), RCC->APB1LENR |= BIT(17);
|
||||
if (uart == USART3) freq = hal_apb_freq(1), RCC->APB1LENR |= BIT(18);
|
||||
|
||||
if (uart == USART1) tx = PIN('A', 9), rx = PIN('A', 10);
|
||||
if (uart == USART2) tx = PIN('A', 2), rx = PIN('A', 3);
|
||||
if (uart == USART3) tx = PIN('D', 8), rx = PIN('D', 9);
|
||||
|
||||
hal_gpio_init(tx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af);
|
||||
hal_gpio_init(rx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af);
|
||||
uart->CR1 = 0; // Disable this UART
|
||||
uart->BRR = freq / baud; // Set baud rate
|
||||
uart->CR1 = BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
|
||||
}
|
||||
static inline void hal_uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
|
||||
uart->TDR = byte;
|
||||
while ((uart->ISR & BIT(7)) == 0) spin(1);
|
||||
}
|
||||
static inline void hal_uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) hal_uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int hal_uart_read_ready(USART_TypeDef *uart) {
|
||||
return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
|
||||
}
|
||||
static inline uint8_t hal_uart_read_byte(USART_TypeDef *uart) {
|
||||
return (uint8_t) (uart->RDR & 255);
|
||||
}
|
||||
|
||||
static inline void hal_rng_init(void) {
|
||||
RCC->D2CCIP2R |= RCC_D2CCIP2R_RNGSEL_0; // RNG clock source pll1_q_ck
|
||||
RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; // Enable RNG clock
|
||||
RNG->CR = RNG_CR_RNGEN; // Enable RNG
|
||||
}
|
||||
|
||||
static inline uint32_t hal_rng_read(void) {
|
||||
while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
|
||||
return RNG->DR;
|
||||
}
|
||||
|
||||
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
|
||||
static inline void hal_ethernet_init(void) {
|
||||
// Initialise Ethernet. Enable MAC GPIO pins, see
|
||||
// https://www.st.com/resource/en/user_manual/um2407-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf
|
||||
uint16_t pins[] = {HAL_ETH_PINS};
|
||||
for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
|
||||
hal_gpio_init(pins[i], HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL,
|
||||
HAL_GPIO_SPEED_INSANE, HAL_GPIO_PULL_NONE, 11); // 11 is the Ethernet function
|
||||
}
|
||||
RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; // Enable SYSCFG
|
||||
CLRSET(SYSCFG->PMCR, 7 << 21, 4 << 21); // Use RMII (12.3.1)
|
||||
RCC->AHB1ENR |= BIT(15) | BIT(16) | BIT(17); // Enable Ethernet clocks
|
||||
NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
|
||||
}
|
||||
|
||||
static inline unsigned int hal_div2prescval(unsigned int div) {
|
||||
// 0 --> /1; 8 --> /2 ... 11 --> /16; 12 --> /64 ... 15 --> /512
|
||||
if (div == 1) return 0;
|
||||
if (div > 16) div /= 2;
|
||||
unsigned int val = 7;
|
||||
while (div >>= 1) ++val;
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned int hal_pllrge(unsigned int f) {
|
||||
unsigned int val = 0;
|
||||
while (f >>= 1) ++val;
|
||||
return val - 1;
|
||||
}
|
||||
|
||||
static inline void hal_clock_init(void) {
|
||||
PWR->CR3 |= BIT(1); // select LDO (reset value)
|
||||
while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
|
||||
PWR->D3CR |= BIT(15) | BIT(14); // Select VOS1
|
||||
uint32_t f = PWR->D3CR; // fake read to wait for bus clocking
|
||||
while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
|
||||
SYSCFG->PWRCR |= BIT(0); // ODEN
|
||||
f = SYSCFG->PWRCR;
|
||||
while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
|
||||
(void) f;
|
||||
CLRSET(
|
||||
RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0),
|
||||
(hal_div2prescval(HAL_D1CPRE) << 8) | (HAL_D1PPRE << 4) | (hal_div2prescval(HAL_HPRE) << 0));
|
||||
RCC->D2CFGR = (HAL_D2PPRE2 << 8) | (HAL_D2PPRE1 << 4);
|
||||
RCC->D3CFGR = (HAL_D3PPRE << 4);
|
||||
CLRSET(RCC->PLLCFGR, 3 << 2,
|
||||
hal_pllrge(PLL1_HSI / PLL1_M)
|
||||
<< 2); // keep reset config (DIVP1EN, !PLL1VCOSEL), PLL1RGE
|
||||
CLRSET(RCC->PLL1DIVR, (0x7F << 9) | (0x1FF << 0),
|
||||
((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0)); // Set PLL1_P PLL1_N
|
||||
CLRSET(RCC->PLLCKSELR, 0x3F << 4,
|
||||
PLL1_M << 4); // Set PLL1_M (source defaults to HSI)
|
||||
RCC->CR |= BIT(24); // Enable PLL1
|
||||
while ((RCC->CR & BIT(25)) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR |= (3 << 0); // Set clock source to PLL1
|
||||
while ((RCC->CFGR & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
|
||||
FLASH->ACR = FLASH_LATENCY; // default is larger
|
||||
}
|
||||
|
||||
static inline void hal_system_init(void) {
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
@@ -0,0 +1,32 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k
|
||||
sram(rwx) : ORIGIN = 0x24000000, LENGTH = 512k /* AXI SRAM in domain D1 */
|
||||
/* 2.3.2: remaining SRAM is in other (non-contiguous) banks,
|
||||
DTCM @0x20000000 is in domain D1 and not accessible by the ETH DMA controller in domain D2
|
||||
SRAM @0x30000000 is in domain D2 and not directly available at startup to be used as stack (8.5.9 page 366) */
|
||||
}
|
||||
_estack = ORIGIN(sram) + LENGTH(sram); /* stack points to end of SRAM */
|
||||
|
||||
SECTIONS {
|
||||
.vectors : { KEEP(*(.isr_vector)) } > flash
|
||||
.text : { *(.text* .text.*) } > flash
|
||||
.rodata : { *(.rodata*) } > flash
|
||||
|
||||
.data : {
|
||||
_sdata = .; /* for init_ram() */
|
||||
*(.first_data)
|
||||
*(.data SORT(.data.*))
|
||||
_edata = .; /* for init_ram() */
|
||||
} > sram AT > flash
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : {
|
||||
_sbss = .; /* for init_ram() */
|
||||
*(.bss SORT(.bss.*) COMMON)
|
||||
_ebss = .; /* for init_ram() */
|
||||
} > sram
|
||||
|
||||
. = ALIGN(8);
|
||||
_end = .; /* for cmsis_gcc.h and init_ram() */
|
||||
}
|
||||
@@ -0,0 +1,70 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "mongoose.h"
|
||||
#include "hal.h"
|
||||
|
||||
#define DEBUG_UART USART3
|
||||
#define LED1 PIN('B', 0) // On-board LED pin (green)
|
||||
#define LED2 PIN('E', 1) // On-board LED pin (yellow)
|
||||
#define LED3 PIN('B', 14) // On-board LED pin (red)
|
||||
|
||||
// Redirect stdout debug output to UART
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
if (fd == 1 || fd == 2) hal_uart_write_buf(DEBUG_UART, ptr, (size_t) len);
|
||||
return len;
|
||||
}
|
||||
|
||||
static void blink_task(void) {
|
||||
static uint64_t blink_timer = 0;
|
||||
if (hal_timer_expired(&blink_timer, 500, hal_get_tick())) {
|
||||
hal_gpio_toggle(LED1);
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t mg_millis(void) {
|
||||
return hal_get_tick();
|
||||
}
|
||||
|
||||
bool mg_random(void *buf, size_t len) {
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = hal_rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) {
|
||||
if (ev == MG_EV_HTTP_MSG) { // New HTTP request received
|
||||
struct mg_http_message *hm = (struct mg_http_message *) ev_data;
|
||||
if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) {
|
||||
mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), hal_get_tick());
|
||||
} else {
|
||||
mg_http_reply(c, 200, "", "Hi from Mongoose, tick %llu\n",
|
||||
hal_get_tick());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
hal_clock_init();
|
||||
hal_rng_init();
|
||||
hal_gpio_output(LED1);
|
||||
hal_gpio_output(LED2);
|
||||
hal_gpio_output(LED3);
|
||||
hal_uart_init(DEBUG_UART, 115200);
|
||||
|
||||
hal_ethernet_init();
|
||||
|
||||
// Start a minimal web server
|
||||
struct mg_mgr mgr;
|
||||
mg_mgr_init(&mgr);
|
||||
mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL);
|
||||
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
blink_task();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,42 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_ARMGCC
|
||||
#define MG_TLS MG_TLS_BUILTIN
|
||||
#define MG_OTA MG_OTA_STM32H7
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_DRIVER_STM32H 1
|
||||
|
||||
// #define MG_DRIVER_MDC_CR 4 // RMII MDC clock divider, from 0 to 5
|
||||
// #define MG_TCPIP_PHY_ADDR 0 // PHY address
|
||||
|
||||
// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
|
||||
// By default, those are set to zero, meaning that DHCP is used
|
||||
//
|
||||
// #define MG_TCPIP_IP MG_IPV4(192, 168, 0, 10) // IP
|
||||
// #define MG_TCPIP_GW MG_IPV4(192, 168, 0, 1) // Gateway
|
||||
// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0) // Netmask
|
||||
|
||||
// Set custom MAC address. By default, it is randomly generated
|
||||
// Using a build-time constant:
|
||||
// #define MG_SET_MAC_ADDRESS(mac) do { mac[0] = 2; mac[1] = 3; mac[2] = 4; mac[3] = 5; mac[4] = 6; mac[5] = 7; } while (0)
|
||||
//
|
||||
// Using custom function:
|
||||
// extern void my_function(unsigned char *mac);
|
||||
// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)
|
||||
|
||||
// Construct MAC address from the MCU unique ID. It is defined in the
|
||||
// ST CMSIS header as UID_BASE
|
||||
#define MGUID ((uint32_t *) 0x1ff1e800) // Unique 96-bit chip ID
|
||||
#define MG_SET_MAC_ADDRESS(mac) \
|
||||
do { \
|
||||
mac[0] = 2; \
|
||||
mac[1] = MGUID[0] & 255; \
|
||||
mac[2] = (MGUID[0] >> 10) & 255; \
|
||||
mac[3] = (MGUID[0] >> 19) & 255; \
|
||||
mac[4] = MGUID[1] & 255; \
|
||||
mac[5] = MGUID[2] & 255; \
|
||||
} while (0)
|
||||
@@ -0,0 +1,30 @@
|
||||
# STM32H747I-DISCO Mongoose Integration
|
||||
|
||||
This guide explains how to bring up a production-grade Web UI dashboard on the
|
||||
STM32H747I-DISCO development board.
|
||||
|
||||
A pre-configured, ready-to-run project zip is available for download at
|
||||
https://mongoose.ws.
|
||||
|
||||
To integrate the Web UI dashboard into an existing CubeMX project, or to create a
|
||||
new project from scratch:
|
||||
|
||||
1. Configure the peripherals (described below).
|
||||
2. Regenerate your project code and integrate Mongoose core by following
|
||||
https://mongoose.ws/docs/guides/stm32-tcpip-stack/.
|
||||
3. Add the Web UI dashboard by following
|
||||
https://mongoose.ws/docs/guides/web-dashboard-guide/.
|
||||
|
||||
## Configure peripherals
|
||||
|
||||
An `.ioc` file is included in this directory for your reference. It was created
|
||||
using the following steps:
|
||||
|
||||
- Open CubeMX. If you are starting a new project, select the STM32H747I-DISCO
|
||||
board and create a new project.
|
||||
- In Clock Configuration, set the maximum clock frequency to 400 MHz.
|
||||
- In the MCU pinout view, set pins PI11, PI12, and PI13 to GPIO_Output mode.
|
||||
- In Pinout & Configuration / Connectivity, enable USART1 in asynchronous mode.
|
||||
Configure pins PA9 and PA10 for USART.
|
||||
- In Pinout & Configuration / Connectivity, enable ETH in RMII mode and set pins
|
||||
PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG12, and PG13 for Ethernet.
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,38 @@
|
||||
# Copyright (c) 2026 Cesanta Software Limited
|
||||
# Environment setup: https://mongoose.ws/docs/getting-started/build-environment/
|
||||
|
||||
CFLAGS = -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion
|
||||
CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
|
||||
CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
|
||||
CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_h7/Include
|
||||
CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA) -DCORE_CM7
|
||||
LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nosys.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
|
||||
|
||||
SOURCES = main.c hal.c
|
||||
SOURCES += cmsis_h7/Source/Templates/gcc/startup_stm32h747xx.s
|
||||
|
||||
TOP = ../../../..
|
||||
CFLAGS += -I$(TOP)
|
||||
SOURCES += $(TOP)/mongoose.c
|
||||
|
||||
all: firmware.bin
|
||||
|
||||
firmware.elf: cmsis_core cmsis_h7 hal.h link.ld Makefile $(SOURCES)
|
||||
arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(CFLAGS_EXTRA) $(LDFLAGS) -o $@
|
||||
|
||||
firmware.bin: firmware.elf
|
||||
arm-none-eabi-objcopy -O binary $< $@
|
||||
@echo
|
||||
@echo "To flash, run 'make flash', or use STM32CubeProgrammer"
|
||||
|
||||
flash: firmware.bin
|
||||
STM32_Programmer_CLI -c port=swd -e all -w firmware.elf -hardRst
|
||||
|
||||
cmsis_core:
|
||||
git clone -q -c advice.detachedHead=false --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
|
||||
|
||||
cmsis_h7:
|
||||
git clone -q -c advice.detachedHead=false --depth 1 -b v1.10.4 https://github.com/STMicroelectronics/cmsis_device_h7 $@
|
||||
|
||||
clean:
|
||||
rm -rf firmware.*
|
||||
@@ -0,0 +1,125 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
|
||||
bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now) {
|
||||
uint64_t diff = now - *t; // Wrap-safe elapsed time since last expiry
|
||||
if (period == 0) return false; // Avoid division by zero
|
||||
if (diff < period) return false; // Period has not elapsed yet
|
||||
*t += (diff / period) * period; // Preserve cadence, skip missed periods
|
||||
return true;
|
||||
}
|
||||
|
||||
static volatile uint64_t s_ticks; // Milliseconds since boot
|
||||
void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
|
||||
s_ticks++;
|
||||
}
|
||||
|
||||
uint64_t hal_get_tick(void) {
|
||||
return s_ticks;
|
||||
};
|
||||
|
||||
uint32_t SystemCoreClock = SYS_FREQUENCY;
|
||||
void SystemInit(void) { // Called automatically by startup code
|
||||
hal_system_init(); // Enable FPU
|
||||
hal_clock_init();
|
||||
SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
|
||||
}
|
||||
|
||||
void ExitRun0Mode(void) {
|
||||
}
|
||||
|
||||
struct stat;
|
||||
__attribute__((weak)) int _fstat(int fd, struct stat *st) {
|
||||
(void) fd, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
extern unsigned char _end[]; // End of data section, start of heap. See link.ld
|
||||
static unsigned char *s_current_heap_end = _end;
|
||||
|
||||
size_t hal_ram_used(void) {
|
||||
return (size_t) (s_current_heap_end - _end);
|
||||
}
|
||||
|
||||
size_t hal_ram_free(void) {
|
||||
unsigned char endofstack;
|
||||
return (size_t) (&endofstack - s_current_heap_end);
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
unsigned char *prev_heap;
|
||||
unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
|
||||
prev_heap = s_current_heap_end;
|
||||
// Check how much space we got from the heap end to the stack end
|
||||
if (s_current_heap_end + incr > heap_end) return (void *) -1;
|
||||
s_current_heap_end += incr;
|
||||
return prev_heap;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _open(const char *path) {
|
||||
(void) path;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _close(int fd) {
|
||||
(void) fd;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _isatty(int fd) {
|
||||
(void) fd;
|
||||
return 1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _lseek(int fd, int ptr, int dir) {
|
||||
(void) fd, (void) ptr, (void) dir;
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _exit(int status) {
|
||||
(void) status;
|
||||
for (;;) asm volatile("BKPT #0");
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _kill(int pid, int sig) {
|
||||
(void) pid, (void) sig;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _getpid(void) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _write(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _read(int fd, char *ptr, int len) {
|
||||
(void) fd, (void) ptr, (void) len;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _link(const char *a, const char *b) {
|
||||
(void) a, (void) b;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _unlink(const char *a) {
|
||||
(void) a;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int _stat(const char *path, struct stat *st) {
|
||||
(void) path, (void) st;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) int mkdir(const char *path, int mode) {
|
||||
(void) path, (void) mode;
|
||||
return -1;
|
||||
}
|
||||
|
||||
__attribute__((weak)) void _init(void) {
|
||||
}
|
||||
@@ -0,0 +1,246 @@
|
||||
// Copyright (c) 2022-2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
//
|
||||
// RM0399
|
||||
// https://www.st.com/resource/en/reference_manual/rm0399-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
|
||||
// https://www.st.com/resource/en/datasheet/stm32h747xi.pdf
|
||||
// UM2411
|
||||
// https://www.st.com/resource/en/user_manual/um2411-discovery-kit-with-stm32h747xi-mcu-stmicroelectronics.pdf
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stm32h747xx.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
extern bool hal_timer_expired(volatile uint64_t *t, uint64_t prd, uint64_t now);
|
||||
extern uint64_t hal_get_tick(void);
|
||||
extern size_t hal_ram_free(void);
|
||||
extern size_t hal_ram_used(void);
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
#define HAL_ETH_PINS \
|
||||
PIN('A', 1), /* ETH_REF_CLK */ \
|
||||
PIN('A', 2), /* ETH_MDIO */ \
|
||||
PIN('A', 7), /* ETH_CRS_DV */ \
|
||||
PIN('C', 1), /* ETH_MDC */ \
|
||||
PIN('C', 4), /* ETH_RXD0 */ \
|
||||
PIN('C', 5), /* ETH_RXD1 */ \
|
||||
PIN('G', 11), /* ETH_TX_EN */ \
|
||||
PIN('G', 12), /* ETH_TXD1 */ \
|
||||
PIN('G', 13) /* ETH_TXD0 */
|
||||
|
||||
#define BIT(x) (1UL << (x))
|
||||
#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
|
||||
#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
|
||||
#define PINNO(pin) (pin & 255)
|
||||
#define PINBANK(pin) (pin >> 8)
|
||||
|
||||
void hal_init(void);
|
||||
size_t hal_ram_free(void);
|
||||
size_t hal_ram_used(void);
|
||||
|
||||
// System clock (2.1, Figure 1; 8.5, Figure 45; 8.5.5, Figure 47; 8.5.6, Figure
|
||||
// 49)
|
||||
// - This board defaults to work with an SMPS regulator, so:
|
||||
// - SYS_FREQUENCY <= 400 MHz; hclk = SYS_FREQUENCY / HPRE ; hclk <= 200 MHz;
|
||||
// APB clocks <= 100 MHz.
|
||||
// - D1 domain bus matrix (and so flash) runs at hclk frequency. Configure flash
|
||||
// latency (WS) in accordance to hclk freq (4.3.8, Table 17)
|
||||
// - The Ethernet controller is in D2 domain and runs at hclk frequency
|
||||
enum {
|
||||
HAL_D1CPRE = 1, // actual divisor value
|
||||
HAL_HPRE = 2, // actual divisor value
|
||||
HAL_D1PPRE = 4, // register values, divisor value = BIT(value - 3) = / 2
|
||||
HAL_D2PPRE1 = 4,
|
||||
HAL_D2PPRE2 = 4,
|
||||
HAL_D3PPRE = 4
|
||||
};
|
||||
// PLL1_P: odd division factors are not allowed (8.7.13) (according to Cube, '1'
|
||||
// is also an "odd division factor").
|
||||
// Make sure your chip is revision 'V', otherwise set PLL1_N = 400
|
||||
enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 400, PLL1_P = 2 };
|
||||
#define SYS_FREQUENCY ((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / HAL_D1CPRE) * 1000000)
|
||||
//#define SYS_FREQUENCY ((PLL1_HSI / HAL_D1CPRE) * 1000000)
|
||||
//#define SYS_FREQUENCY 64000000
|
||||
#define AHB_FREQUENCY (SYS_FREQUENCY / HAL_HPRE)
|
||||
#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(HAL_D2PPRE2 - 3)))
|
||||
#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(HAL_D2PPRE1 - 3)))
|
||||
|
||||
static inline void spin(volatile uint32_t n) {
|
||||
while (n--) (void) 0;
|
||||
}
|
||||
|
||||
enum { HAL_GPIO_MODE_INPUT, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_MODE_AF, HAL_GPIO_MODE_ANALOG };
|
||||
enum { HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_OTYPE_OPEN_DRAIN };
|
||||
enum { HAL_GPIO_SPEED_LOW, HAL_GPIO_SPEED_MEDIUM, HAL_GPIO_SPEED_HIGH, HAL_GPIO_SPEED_INSANE };
|
||||
enum { HAL_GPIO_PULL_NONE, HAL_GPIO_PULL_UP, HAL_GPIO_PULL_DOWN };
|
||||
|
||||
#define HAL_GPIO(N) ((GPIO_TypeDef *) (0x40000000 + 0x18020000UL + 0x400 * (N)))
|
||||
|
||||
static GPIO_TypeDef *hal_gpio_bank(uint16_t pin) {
|
||||
return HAL_GPIO(PINBANK(pin));
|
||||
}
|
||||
static inline void hal_gpio_toggle(uint16_t pin) {
|
||||
GPIO_TypeDef *gpio = hal_gpio_bank(pin);
|
||||
uint32_t mask = BIT(PINNO(pin));
|
||||
gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
|
||||
}
|
||||
static inline int hal_gpio_read(uint16_t pin) {
|
||||
return hal_gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
|
||||
}
|
||||
static inline void hal_gpio_write(uint16_t pin, bool val) {
|
||||
GPIO_TypeDef *gpio = hal_gpio_bank(pin);
|
||||
gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
|
||||
}
|
||||
static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
|
||||
uint8_t speed, uint8_t pull, uint8_t af) {
|
||||
GPIO_TypeDef *gpio = hal_gpio_bank(pin);
|
||||
uint8_t n = (uint8_t) (PINNO(pin));
|
||||
RCC->AHB4ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
|
||||
CLRSET(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
|
||||
CLRSET(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
|
||||
CLRSET(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
|
||||
CLRSET(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
|
||||
((uint32_t) af) << ((n & 7) * 4));
|
||||
CLRSET(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
|
||||
}
|
||||
static inline void hal_gpio_input(uint16_t pin) {
|
||||
hal_gpio_init(pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH,
|
||||
HAL_GPIO_PULL_NONE, 0);
|
||||
}
|
||||
static inline void hal_gpio_output(uint16_t pin) {
|
||||
hal_gpio_init(pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH,
|
||||
HAL_GPIO_PULL_NONE, 0);
|
||||
}
|
||||
|
||||
// D2 Kernel clock (8.7.21) USART1 defaults to pclk2 (APB2), while USART2,3
|
||||
// default to pclk1 (APB1). Even if using other kernel clocks, the APBx clocks
|
||||
// must be enabled for CPU access, as the kernel clock drives the BRR, not the
|
||||
// APB bus interface
|
||||
static inline void hal_uart_init(USART_TypeDef *uart, unsigned long baud) {
|
||||
uint8_t af = 7; // Alternate function
|
||||
uint16_t rx = 0, tx = 0; // pins
|
||||
uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
|
||||
|
||||
if (uart == USART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
|
||||
if (uart == USART2) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(17);
|
||||
if (uart == USART3) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(18);
|
||||
|
||||
if (uart == USART1) tx = PIN('A', 9), rx = PIN('A', 10);
|
||||
if (uart == USART2) tx = PIN('A', 2), rx = PIN('A', 3);
|
||||
if (uart == USART3) tx = PIN('D', 8), rx = PIN('D', 9);
|
||||
|
||||
#if 0 // CONSTANT BAUD RATE FOR REMOTE DEBUGGING WHILE SETTING THE PLL
|
||||
CLRSET(RCC->D2CCIP2R, 7 << 3, 3 << 3); // use HSI for UART1
|
||||
freq = 64000000;
|
||||
#endif
|
||||
|
||||
hal_gpio_init(tx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af);
|
||||
hal_gpio_init(rx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af);
|
||||
uart->CR1 = 0; // Disable this UART
|
||||
uart->BRR = freq / baud; // Set baud rate
|
||||
uart->CR1 = BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE
|
||||
}
|
||||
static inline void hal_uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
|
||||
uart->TDR = byte;
|
||||
while ((uart->ISR & BIT(7)) == 0) spin(1);
|
||||
}
|
||||
static inline void hal_uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) hal_uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int hal_uart_read_ready(USART_TypeDef *uart) {
|
||||
return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
|
||||
}
|
||||
static inline uint8_t hal_uart_read_byte(USART_TypeDef *uart) {
|
||||
return (uint8_t) (uart->RDR & 255);
|
||||
}
|
||||
|
||||
static inline void hal_rng_init(void) {
|
||||
RCC->D2CCIP2R |= RCC_D2CCIP2R_RNGSEL_0; // RNG clock source pll1_q_ck
|
||||
RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; // Enable RNG clock
|
||||
RNG->CR = RNG_CR_RNGEN; // Enable RNG
|
||||
}
|
||||
|
||||
static inline uint32_t hal_rng_read(void) {
|
||||
while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
|
||||
return RNG->DR;
|
||||
}
|
||||
|
||||
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
|
||||
static inline void hal_ethernet_init(void) {
|
||||
// Initialise Ethernet. Enable MAC GPIO pins, see UM2411
|
||||
uint16_t pins[] = {HAL_ETH_PINS};
|
||||
for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
|
||||
hal_gpio_init(pins[i], HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_INSANE,
|
||||
HAL_GPIO_PULL_NONE, 11); // 11 is the Ethernet function
|
||||
}
|
||||
NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
|
||||
CLRSET(SYSCFG->PMCR, 7 << 21, 4 << 21); // Use RMII (13.3.1)
|
||||
RCC->AHB1ENR |= BIT(15) | BIT(16) | BIT(17); // Enable Ethernet clocks
|
||||
}
|
||||
|
||||
static inline char hal_chiprev(void) {
|
||||
uint16_t rev = (uint16_t) (((uint32_t) DBGMCU->IDCODE) >> 16);
|
||||
if (rev == 0x1003) return 'Y';
|
||||
if (rev == 0x2003) return 'V';
|
||||
return '?';
|
||||
}
|
||||
|
||||
static inline unsigned int hal_div2prescval(unsigned int div) {
|
||||
// 0 --> /1; 8 --> /2 ... 11 --> /16; 12 --> /64 ... 15 --> /512
|
||||
if (div == 1) return 0;
|
||||
if (div > 16) div /= 2;
|
||||
unsigned int val = 7;
|
||||
while (div >>= 1) ++val;
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline unsigned int hal_pllrge(unsigned int f) {
|
||||
unsigned int val = 0;
|
||||
while (f >>= 1) ++val;
|
||||
return val - 1;
|
||||
}
|
||||
|
||||
static inline void hal_clock_init(void) { // Called automatically by startup code
|
||||
// Set flash latency. RM section 4.9.1, section 4.3.8 table 16
|
||||
CLRSET(FLASH->ACR, (FLASH_ACR_WRHIGHFREQ_Msk | FLASH_ACR_LATENCY_Msk),
|
||||
FLASH_ACR_LATENCY_2WS | FLASH_ACR_WRHIGHFREQ_1);
|
||||
CLRSET(PWR->CR3, BIT(1), BIT(2)); // select SMPS
|
||||
while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
|
||||
PWR->D3CR |= BIT(15) | BIT(14); // Select VOS1
|
||||
uint32_t f = PWR->D3CR; // fake read to wait for bus clocking
|
||||
while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
|
||||
#if 0
|
||||
SYSCFG->PWRCR |= BIT(0); // ODEN for LDO to go 480MHz
|
||||
f = SYSCFG->PWRCR;
|
||||
while ((PWR->CSR1 & BIT(13)) == 0) spin(1); // ACTVOSRDY
|
||||
#endif
|
||||
(void) f;
|
||||
CLRSET(RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0),
|
||||
(hal_div2prescval(HAL_D1CPRE) << 8) | (HAL_D1PPRE << 4) |
|
||||
(hal_div2prescval(HAL_HPRE) << 0));
|
||||
RCC->D2CFGR = (HAL_D2PPRE2 << 8) | (HAL_D2PPRE1 << 4);
|
||||
RCC->D3CFGR = (HAL_D3PPRE << 4);
|
||||
CLRSET(RCC->PLLCFGR, 3 << 2,
|
||||
hal_pllrge(PLL1_HSI / PLL1_M)
|
||||
<< 2); // keep reset config (DIVP1EN, !PLL1VCOSEL), PLL1RGE
|
||||
CLRSET(RCC->PLL1DIVR, (0x7F << 9) | (0x1FF << 0),
|
||||
((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0)); // Set PLL1_P PLL1_N
|
||||
CLRSET(RCC->PLLCKSELR, 0x3F << 4,
|
||||
PLL1_M << 4); // Set PLL1_M (source defaults to HSI)
|
||||
RCC->CR |= BIT(24); // Enable PLL1
|
||||
while ((RCC->CR & BIT(25)) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR |= (3 << 0); // Set clock source to PLL1
|
||||
while ((RCC->CFGR & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
|
||||
RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; // Enable SYSCFG
|
||||
}
|
||||
|
||||
static inline void hal_system_init(void) {
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
@@ -0,0 +1,31 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k
|
||||
sram(rwx) : ORIGIN = 0x24000000, LENGTH = 512k
|
||||
}
|
||||
_estack = ORIGIN(sram) + LENGTH(sram); /* stack points to end of SRAM */
|
||||
|
||||
SECTIONS {
|
||||
.vectors : { KEEP(*(.isr_vector)) } > flash
|
||||
.text : { *(.text* .text.*) } > flash
|
||||
.rodata : { *(.rodata*) } > flash
|
||||
|
||||
.data : {
|
||||
_sdata = .;
|
||||
*(.first_data)
|
||||
*(.data SORT(.data.*))
|
||||
*(.iram .iram* .iram.*)
|
||||
_edata = .;
|
||||
} > sram AT > flash
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : {
|
||||
_sbss = .;
|
||||
*(.bss SORT(.bss.*) COMMON)
|
||||
_ebss = .;
|
||||
} > sram
|
||||
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,70 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "mongoose.h"
|
||||
#include "hal.h"
|
||||
|
||||
#define DEBUG_UART USART1
|
||||
#define LED1 PIN('I', 12) // On-board LED pin (green)
|
||||
#define LED2 PIN('I', 13) // On-board LED pin (yellow)
|
||||
#define LED3 PIN('I', 14) // On-board LED pin (red)
|
||||
|
||||
// Redirect stdout debug output to UART
|
||||
int _write(int fd, char *ptr, int len) {
|
||||
if (fd == 1 || fd == 2) hal_uart_write_buf(DEBUG_UART, ptr, (size_t) len);
|
||||
return len;
|
||||
}
|
||||
|
||||
static void blink_task(void) {
|
||||
static uint64_t blink_timer = 0;
|
||||
if (hal_timer_expired(&blink_timer, 500, hal_get_tick())) {
|
||||
hal_gpio_toggle(LED1);
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t mg_millis(void) {
|
||||
return hal_get_tick();
|
||||
}
|
||||
|
||||
bool mg_random(void *buf, size_t len) {
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = hal_rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) {
|
||||
if (ev == MG_EV_HTTP_MSG) { // New HTTP request received
|
||||
struct mg_http_message *hm = (struct mg_http_message *) ev_data;
|
||||
if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) {
|
||||
mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), hal_get_tick());
|
||||
} else {
|
||||
mg_http_reply(c, 200, "", "Hi from Mongoose, tick %llu\n",
|
||||
hal_get_tick());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
hal_clock_init();
|
||||
hal_rng_init();
|
||||
hal_gpio_output(LED1);
|
||||
hal_gpio_output(LED2);
|
||||
hal_gpio_output(LED3);
|
||||
hal_uart_init(DEBUG_UART, 115200);
|
||||
|
||||
hal_ethernet_init();
|
||||
|
||||
// Start a minimal web server
|
||||
struct mg_mgr mgr;
|
||||
mg_mgr_init(&mgr);
|
||||
mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL);
|
||||
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
blink_task();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,42 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_ARMGCC
|
||||
#define MG_TLS MG_TLS_BUILTIN
|
||||
#define MG_OTA MG_OTA_STM32H7_DUAL_CORE
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_DRIVER_STM32H 1
|
||||
|
||||
// #define MG_DRIVER_MDC_CR 4 // RMII MDC clock divider, from 0 to 5
|
||||
// #define MG_TCPIP_PHY_ADDR 0 // PHY address
|
||||
|
||||
// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
|
||||
// By default, those are set to zero, meaning that DHCP is used
|
||||
//
|
||||
// #define MG_TCPIP_IP MG_IPV4(192, 168, 0, 10) // IP
|
||||
// #define MG_TCPIP_GW MG_IPV4(192, 168, 0, 1) // Gateway
|
||||
// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0) // Netmask
|
||||
|
||||
// Set custom MAC address. By default, it is randomly generated
|
||||
// Using a build-time constant:
|
||||
// #define MG_SET_MAC_ADDRESS(mac) do { mac[0] = 2; mac[1] = 3; mac[2] = 4; mac[3] = 5; mac[4] = 6; mac[5] = 7; } while (0)
|
||||
//
|
||||
// Using custom function:
|
||||
// extern void my_function(unsigned char *mac);
|
||||
// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)
|
||||
|
||||
// Construct MAC address from the MCU unique ID. It is defined in the
|
||||
// ST CMSIS header as UID_BASE
|
||||
#define MGUID ((uint32_t *) 0x1ff1e800) // Unique 96-bit chip ID
|
||||
#define MG_SET_MAC_ADDRESS(mac) \
|
||||
do { \
|
||||
mac[0] = 2; \
|
||||
mac[1] = MGUID[0] & 255; \
|
||||
mac[2] = (MGUID[0] >> 10) & 255; \
|
||||
mac[3] = (MGUID[0] >> 19) & 255; \
|
||||
mac[4] = MGUID[1] & 255; \
|
||||
mac[5] = MGUID[2] & 255; \
|
||||
} while (0)
|
||||
Reference in new issue
Block a user