More STM32 examples

2026-11-14 19:03:20 +00:00 · 2026-05-22 06:46:04 -04:00
1 parent 948b56a3ec
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+# STM32H747I-DISCO Mongoose Integration
+
+This guide explains how to bring up a production-grade Web UI dashboard on the
+STM32H747I-DISCO development board.
+
+A pre-configured, ready-to-run project zip is available for download at
+https://mongoose.ws.
+
+To integrate the Web UI dashboard into an existing CubeMX project, or to create a
+new project from scratch:
+
+1. Configure the peripherals (described below).
+2. Regenerate your project code and integrate Mongoose core by following
+   https://mongoose.ws/docs/guides/stm32-tcpip-stack/.
+3. Add the Web UI dashboard by following
+   https://mongoose.ws/docs/guides/web-dashboard-guide/.
+
+## Configure peripherals
+
+An `.ioc` file is included in this directory for your reference. It was created
+using the following steps:
+
+- Open CubeMX. If you are starting a new project, select the STM32H747I-DISCO
+  board and create a new project.
+- In Clock Configuration, set the maximum clock frequency to 400 MHz.
+- In the MCU pinout view, set pins PI11, PI12, and PI13 to GPIO_Output mode.
+- In Pinout & Configuration / Connectivity, enable USART1 in asynchronous mode.
+  Configure pins PA9 and PA10 for USART.
+- In Pinout & Configuration / Connectivity, enable ETH in RMII mode and set pins
+  PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG12, and PG13 for Ethernet.
@@ -0,0 +1,38 @@
+# Copyright (c) 2026 Cesanta Software Limited
+# Environment setup: https://mongoose.ws/docs/getting-started/build-environment/
+
+CFLAGS  = -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion
+CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
+CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
+CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_h7/Include
+CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA) -DCORE_CM7
+LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nosys.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
+
+SOURCES = main.c hal.c
+SOURCES += cmsis_h7/Source/Templates/gcc/startup_stm32h747xx.s
+
+TOP = ../../../..
+CFLAGS += -I$(TOP)
+SOURCES += $(TOP)/mongoose.c
+
+all: firmware.bin
+
+firmware.elf: cmsis_core cmsis_h7 hal.h link.ld Makefile $(SOURCES)
+	arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(CFLAGS_EXTRA) $(LDFLAGS) -o $@
+
+firmware.bin: firmware.elf
+	arm-none-eabi-objcopy -O binary $< $@
+	@echo
+	@echo "To flash, run 'make flash', or use STM32CubeProgrammer"
+
+flash: firmware.bin
+	STM32_Programmer_CLI -c port=swd -e all -w firmware.elf -hardRst
+
+cmsis_core:
+	git clone -q -c advice.detachedHead=false --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
+
+cmsis_h7:
+	git clone -q -c advice.detachedHead=false --depth 1 -b v1.10.4 https://github.com/STMicroelectronics/cmsis_device_h7 $@
+
+clean:
+	rm -rf firmware.*
@@ -0,0 +1,125 @@
+// Copyright (c) 2026 Cesanta Software Limited
+// All rights reserved
+
+#include "hal.h"
+
+bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now) {
+  uint64_t diff = now - *t;         // Wrap-safe elapsed time since last expiry
+  if (period == 0) return false;    // Avoid division by zero
+  if (diff < period) return false;  // Period has not elapsed yet
+  *t += (diff / period) * period;   // Preserve cadence, skip missed periods
+  return true;
+}
+
+static volatile uint64_t s_ticks;  // Milliseconds since boot
+void SysTick_Handler(void) {       // SyStick IRQ handler, triggered every 1ms
+  s_ticks++;
+}
+
+uint64_t hal_get_tick(void) {
+  return s_ticks;
+};
+
+uint32_t SystemCoreClock = SYS_FREQUENCY;
+void SystemInit(void) {  // Called automatically by startup code
+  hal_system_init();     // Enable FPU
+  hal_clock_init();
+  SysTick_Config(SystemCoreClock / 1000);  // Sys tick every 1ms
+}
+
+void ExitRun0Mode(void) {
+}
+
+struct stat;
+__attribute__((weak)) int _fstat(int fd, struct stat *st) {
+  (void) fd, (void) st;
+  return -1;
+}
+
+extern unsigned char _end[];  // End of data section, start of heap. See link.ld
+static unsigned char *s_current_heap_end = _end;
+
+size_t hal_ram_used(void) {
+  return (size_t) (s_current_heap_end - _end);
+}
+
+size_t hal_ram_free(void) {
+  unsigned char endofstack;
+  return (size_t) (&endofstack - s_current_heap_end);
+}
+
+void *_sbrk(int incr) {
+  unsigned char *prev_heap;
+  unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
+  prev_heap = s_current_heap_end;
+  // Check how much space we  got from the heap end to the stack end
+  if (s_current_heap_end + incr > heap_end) return (void *) -1;
+  s_current_heap_end += incr;
+  return prev_heap;
+}
+
+__attribute__((weak)) int _open(const char *path) {
+  (void) path;
+  return -1;
+}
+
+__attribute__((weak)) int _close(int fd) {
+  (void) fd;
+  return -1;
+}
+
+__attribute__((weak)) int _isatty(int fd) {
+  (void) fd;
+  return 1;
+}
+
+__attribute__((weak)) int _lseek(int fd, int ptr, int dir) {
+  (void) fd, (void) ptr, (void) dir;
+  return 0;
+}
+
+__attribute__((weak)) void _exit(int status) {
+  (void) status;
+  for (;;) asm volatile("BKPT #0");
+}
+
+__attribute__((weak)) void _kill(int pid, int sig) {
+  (void) pid, (void) sig;
+}
+
+__attribute__((weak)) int _getpid(void) {
+  return -1;
+}
+
+__attribute__((weak)) int _write(int fd, char *ptr, int len) {
+  (void) fd, (void) ptr, (void) len;
+  return -1;
+}
+
+__attribute__((weak)) int _read(int fd, char *ptr, int len) {
+  (void) fd, (void) ptr, (void) len;
+  return -1;
+}
+
+__attribute__((weak)) int _link(const char *a, const char *b) {
+  (void) a, (void) b;
+  return -1;
+}
+
+__attribute__((weak)) int _unlink(const char *a) {
+  (void) a;
+  return -1;
+}
+
+__attribute__((weak)) int _stat(const char *path, struct stat *st) {
+  (void) path, (void) st;
+  return -1;
+}
+
+__attribute__((weak)) int mkdir(const char *path, int mode) {
+  (void) path, (void) mode;
+  return -1;
+}
+
+__attribute__((weak)) void _init(void) {
+}
@@ -0,0 +1,246 @@
+// Copyright (c) 2022-2023 Cesanta Software Limited
+// All rights reserved
+//
+// RM0399
+// https://www.st.com/resource/en/reference_manual/rm0399-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
+// https://www.st.com/resource/en/datasheet/stm32h747xi.pdf
+// UM2411
+// https://www.st.com/resource/en/user_manual/um2411-discovery-kit-with-stm32h747xi-mcu-stmicroelectronics.pdf
+
+#pragma once
+
+#include <stm32h747xx.h>
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+extern bool hal_timer_expired(volatile uint64_t *t, uint64_t prd, uint64_t now);
+extern uint64_t hal_get_tick(void);
+extern size_t hal_ram_free(void);
+extern size_t hal_ram_used(void);
+extern uint32_t SystemCoreClock;
+
+#define HAL_ETH_PINS  \
+  PIN('A', 1), /* ETH_REF_CLK */ \
+  PIN('A', 2), /* ETH_MDIO */ \
+  PIN('A', 7), /* ETH_CRS_DV */ \
+  PIN('C', 1), /* ETH_MDC */ \
+  PIN('C', 4), /* ETH_RXD0 */ \
+  PIN('C', 5), /* ETH_RXD1 */ \
+  PIN('G', 11), /* ETH_TX_EN */ \
+  PIN('G', 12), /* ETH_TXD1 */ \
+  PIN('G', 13) /* ETH_TXD0 */
+
+#define BIT(x) (1UL << (x))
+#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
+#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
+#define PINNO(pin) (pin & 255)
+#define PINBANK(pin) (pin >> 8)
+
+void hal_init(void);
+size_t hal_ram_free(void);
+size_t hal_ram_used(void);
+
+// System clock (2.1, Figure 1; 8.5, Figure 45; 8.5.5, Figure 47; 8.5.6, Figure
+// 49)
+// - This board defaults to work with an SMPS regulator, so:
+//   - SYS_FREQUENCY <= 400 MHz; hclk = SYS_FREQUENCY / HPRE ; hclk <= 200 MHz;
+//   APB clocks <= 100 MHz.
+// - D1 domain bus matrix (and so flash) runs at hclk frequency. Configure flash
+// latency (WS) in accordance to hclk freq (4.3.8, Table 17)
+// - The Ethernet controller is in D2 domain and runs at hclk frequency
+enum {
+  HAL_D1CPRE = 1, // actual divisor value
+  HAL_HPRE = 2,   // actual divisor value
+  HAL_D1PPRE = 4, // register values, divisor value = BIT(value - 3) = / 2
+  HAL_D2PPRE1 = 4,
+  HAL_D2PPRE2 = 4,
+  HAL_D3PPRE = 4
+};
+// PLL1_P: odd division factors are not allowed (8.7.13) (according to Cube, '1'
+// is also an "odd division factor").
+// Make sure your chip is revision 'V', otherwise set PLL1_N = 400
+enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 400, PLL1_P = 2 };
+#define SYS_FREQUENCY ((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / HAL_D1CPRE) * 1000000)
+//#define SYS_FREQUENCY ((PLL1_HSI / HAL_D1CPRE) * 1000000)
+//#define SYS_FREQUENCY 64000000
+#define AHB_FREQUENCY (SYS_FREQUENCY / HAL_HPRE)
+#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(HAL_D2PPRE2 - 3)))
+#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(HAL_D2PPRE1 - 3)))
+
+static inline void spin(volatile uint32_t n) {
+  while (n--) (void) 0;
+}
+
+enum { HAL_GPIO_MODE_INPUT, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_MODE_AF, HAL_GPIO_MODE_ANALOG };
+enum { HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_OTYPE_OPEN_DRAIN };
+enum { HAL_GPIO_SPEED_LOW, HAL_GPIO_SPEED_MEDIUM, HAL_GPIO_SPEED_HIGH, HAL_GPIO_SPEED_INSANE };
+enum { HAL_GPIO_PULL_NONE, HAL_GPIO_PULL_UP, HAL_GPIO_PULL_DOWN };
+
+#define HAL_GPIO(N) ((GPIO_TypeDef *) (0x40000000 + 0x18020000UL + 0x400 * (N)))
+
+static GPIO_TypeDef *hal_gpio_bank(uint16_t pin) {
+  return HAL_GPIO(PINBANK(pin));
+}
+static inline void hal_gpio_toggle(uint16_t pin) {
+  GPIO_TypeDef *gpio = hal_gpio_bank(pin);
+  uint32_t mask = BIT(PINNO(pin));
+  gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
+}
+static inline int hal_gpio_read(uint16_t pin) {
+  return hal_gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
+}
+static inline void hal_gpio_write(uint16_t pin, bool val) {
+  GPIO_TypeDef *gpio = hal_gpio_bank(pin);
+  gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
+}
+static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
+                             uint8_t speed, uint8_t pull, uint8_t af) {
+  GPIO_TypeDef *gpio = hal_gpio_bank(pin);
+  uint8_t n = (uint8_t) (PINNO(pin));
+  RCC->AHB4ENR |= BIT(PINBANK(pin));  // Enable GPIO clock
+  CLRSET(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
+  CLRSET(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
+  CLRSET(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
+  CLRSET(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
+          ((uint32_t) af) << ((n & 7) * 4));
+  CLRSET(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
+}
+static inline void hal_gpio_input(uint16_t pin) {
+  hal_gpio_init(pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH,
+            HAL_GPIO_PULL_NONE, 0);
+}
+static inline void hal_gpio_output(uint16_t pin) {
+  hal_gpio_init(pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH,
+            HAL_GPIO_PULL_NONE, 0);
+}
+
+// D2 Kernel clock (8.7.21) USART1 defaults to pclk2 (APB2), while USART2,3
+// default to pclk1 (APB1). Even if using other kernel clocks, the APBx clocks
+// must be enabled for CPU access, as the kernel clock drives the BRR, not the
+// APB bus interface
+static inline void hal_uart_init(USART_TypeDef *uart, unsigned long baud) {
+  uint8_t af = 7;           // Alternate function
+  uint16_t rx = 0, tx = 0;  // pins
+  uint32_t freq = 0;        // Bus frequency. UART1 is on APB2, rest on APB1
+
+  if (uart == USART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
+  if (uart == USART2) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(17);
+  if (uart == USART3) freq = APB1_FREQUENCY, RCC->APB1LENR |= BIT(18);
+
+  if (uart == USART1) tx = PIN('A', 9), rx = PIN('A', 10);
+  if (uart == USART2) tx = PIN('A', 2), rx = PIN('A', 3);
+  if (uart == USART3) tx = PIN('D', 8), rx = PIN('D', 9);
+
+#if 0 // CONSTANT BAUD RATE FOR REMOTE DEBUGGING WHILE SETTING THE PLL
+  CLRSET(RCC->D2CCIP2R, 7 << 3, 3 << 3);  // use HSI for UART1
+  freq = 64000000;
+#endif
+
+  hal_gpio_init(tx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af);
+  hal_gpio_init(rx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af);
+  uart->CR1 = 0;                         // Disable this UART
+  uart->BRR = freq / baud;               // Set baud rate
+  uart->CR1 = BIT(0) | BIT(2) | BIT(3);  // Set UE, RE, TE
+}
+static inline void hal_uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
+  uart->TDR = byte;
+  while ((uart->ISR & BIT(7)) == 0) spin(1);
+}
+static inline void hal_uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
+  while (len-- > 0) hal_uart_write_byte(uart, *(uint8_t *) buf++);
+}
+static inline int hal_uart_read_ready(USART_TypeDef *uart) {
+  return uart->ISR & BIT(5);  // If RXNE bit is set, data is ready
+}
+static inline uint8_t hal_uart_read_byte(USART_TypeDef *uart) {
+  return (uint8_t) (uart->RDR & 255);
+}
+
+static inline void hal_rng_init(void) {
+  RCC->D2CCIP2R |= RCC_D2CCIP2R_RNGSEL_0;  // RNG clock source pll1_q_ck
+  RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;       // Enable RNG clock
+  RNG->CR = RNG_CR_RNGEN;                  // Enable RNG
+}
+
+static inline uint32_t hal_rng_read(void) {
+  while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
+  return RNG->DR;
+}
+
+// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
+static inline void hal_ethernet_init(void) {
+  // Initialise Ethernet. Enable MAC GPIO pins, see UM2411
+  uint16_t pins[] = {HAL_ETH_PINS};
+  for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
+    hal_gpio_init(pins[i], HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_INSANE,
+              HAL_GPIO_PULL_NONE, 11);  // 11 is the Ethernet function
+  }
+  NVIC_EnableIRQ(ETH_IRQn);                     // Setup Ethernet IRQ handler
+  CLRSET(SYSCFG->PMCR, 7 << 21, 4 << 21);      // Use RMII (13.3.1)
+  RCC->AHB1ENR |= BIT(15) | BIT(16) | BIT(17);  // Enable Ethernet clocks
+}
+
+static inline char hal_chiprev(void) {
+  uint16_t rev = (uint16_t) (((uint32_t) DBGMCU->IDCODE) >> 16);
+  if (rev == 0x1003) return 'Y';
+  if (rev == 0x2003) return 'V';
+  return '?';
+}
+
+static inline unsigned int hal_div2prescval(unsigned int div) {
+  // 0 --> /1; 8 --> /2 ... 11 --> /16;  12 --> /64 ... 15 --> /512
+  if (div == 1) return 0;
+  if (div > 16) div /= 2;
+  unsigned int val = 7;
+  while (div >>= 1) ++val;
+  return val;
+}
+
+static inline unsigned int hal_pllrge(unsigned int f) {
+  unsigned int val = 0;
+  while (f >>= 1) ++val;
+  return val - 1;
+}
+
+static inline void hal_clock_init(void) {  // Called automatically by startup code
+  // Set flash latency. RM section 4.9.1, section 4.3.8 table 16
+  CLRSET(FLASH->ACR, (FLASH_ACR_WRHIGHFREQ_Msk | FLASH_ACR_LATENCY_Msk),
+         FLASH_ACR_LATENCY_2WS | FLASH_ACR_WRHIGHFREQ_1);
+  CLRSET(PWR->CR3, BIT(1), BIT(2));            // select SMPS
+  while ((PWR->CSR1 & BIT(13)) == 0) spin(1);  // ACTVOSRDY
+  PWR->D3CR |= BIT(15) | BIT(14);              // Select VOS1
+  uint32_t f = PWR->D3CR;         // fake read to wait for bus clocking
+  while ((PWR->CSR1 & BIT(13)) == 0) spin(1);  // ACTVOSRDY
+#if 0
+  SYSCFG->PWRCR |= BIT(0);                     // ODEN for LDO to go 480MHz
+  f = SYSCFG->PWRCR;
+  while ((PWR->CSR1 & BIT(13)) == 0) spin(1);  // ACTVOSRDY
+#endif
+  (void) f;
+  CLRSET(RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0),
+         (hal_div2prescval(HAL_D1CPRE) << 8) | (HAL_D1PPRE << 4) |
+             (hal_div2prescval(HAL_HPRE) << 0));
+  RCC->D2CFGR = (HAL_D2PPRE2 << 8) | (HAL_D2PPRE1 << 4);
+  RCC->D3CFGR = (HAL_D3PPRE << 4);
+  CLRSET(RCC->PLLCFGR, 3 << 2,
+         hal_pllrge(PLL1_HSI / PLL1_M)
+             << 2); // keep reset config (DIVP1EN, !PLL1VCOSEL), PLL1RGE
+  CLRSET(RCC->PLL1DIVR, (0x7F << 9) | (0x1FF << 0),
+         ((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0)); // Set PLL1_P PLL1_N
+  CLRSET(RCC->PLLCKSELR, 0x3F << 4,
+         PLL1_M << 4); // Set PLL1_M (source defaults to HSI)
+  RCC->CR |= BIT(24);  // Enable PLL1
+  while ((RCC->CR & BIT(25)) == 0) spin(1);  // Wait until done
+  RCC->CFGR |= (3 << 0);                     // Set clock source to PLL1
+  while ((RCC->CFGR & (7 << 3)) != (3 << 3)) spin(1);  // Wait until done
+  RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN;                // Enable SYSCFG
+}
+
+static inline void hal_system_init(void) {
+  SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));  // Enable FPU
+  __DSB();
+  __ISB();
+}
@@ -0,0 +1,31 @@
+ENTRY(Reset_Handler);
+MEMORY {
+  flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k
+  sram(rwx) : ORIGIN = 0x24000000, LENGTH = 512k
+}
+_estack     = ORIGIN(sram) + LENGTH(sram);    /* stack points to end of SRAM */
+
+SECTIONS {
+  .vectors  : { KEEP(*(.isr_vector)) }  > flash
+  .text     : { *(.text* .text.*) }     > flash
+  .rodata   : { *(.rodata*) }           > flash
+
+  .data : {
+    _sdata = .;
+    *(.first_data)
+    *(.data SORT(.data.*))
+    *(.iram .iram* .iram.*)
+    _edata = .;
+  } > sram AT > flash
+  _sidata = LOADADDR(.data);
+
+  .bss : {
+    _sbss = .;
+    *(.bss SORT(.bss.*) COMMON)
+    _ebss = .;
+  } > sram
+
+  . = ALIGN(8);
+  _end = .;
+}
+
@@ -0,0 +1,70 @@
+// Copyright (c) 2026 Cesanta Software Limited
+// All rights reserved
+
+#include "mongoose.h"
+#include "hal.h"
+
+#define DEBUG_UART USART1
+#define LED1 PIN('I', 12)  // On-board LED pin (green)
+#define LED2 PIN('I', 13)  // On-board LED pin (yellow)
+#define LED3 PIN('I', 14)  // On-board LED pin (red)
+
+// Redirect stdout debug output to UART
+int _write(int fd, char *ptr, int len) {
+  if (fd == 1 || fd == 2) hal_uart_write_buf(DEBUG_UART, ptr, (size_t) len);
+  return len;
+}
+
+static void blink_task(void) {
+  static uint64_t blink_timer = 0;
+  if (hal_timer_expired(&blink_timer, 500, hal_get_tick())) {
+    hal_gpio_toggle(LED1);
+  }
+}
+
+uint64_t mg_millis(void) {
+  return hal_get_tick();
+}
+
+bool mg_random(void *buf, size_t len) {
+  for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
+    uint32_t r = hal_rng_read();
+    memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
+  }
+  return true;
+}
+
+static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) {
+  if (ev == MG_EV_HTTP_MSG) {  // New HTTP request received
+    struct mg_http_message *hm = (struct mg_http_message *) ev_data;
+    if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) {
+      mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), hal_get_tick());
+    } else {
+      mg_http_reply(c, 200, "", "Hi from Mongoose, tick %llu\n",
+                    hal_get_tick());
+    }
+  }
+}
+
+int main(void) {
+  hal_clock_init();
+  hal_rng_init();
+  hal_gpio_output(LED1);
+  hal_gpio_output(LED2);
+  hal_gpio_output(LED3);
+  hal_uart_init(DEBUG_UART, 115200);
+
+  hal_ethernet_init();
+
+  // Start a minimal web server
+  struct mg_mgr mgr;
+  mg_mgr_init(&mgr);
+  mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL);
+
+  for (;;) {
+    mg_mgr_poll(&mgr, 0);
+    blink_task();
+  }
+
+  return 0;
+}
@@ -0,0 +1,42 @@
+#pragma once
+
+// See https://mongoose.ws/documentation/#build-options
+#define MG_ARCH MG_ARCH_ARMGCC
+#define MG_TLS MG_TLS_BUILTIN
+#define MG_OTA MG_OTA_STM32H7_DUAL_CORE
+
+#define MG_ENABLE_TCPIP 1
+#define MG_ENABLE_CUSTOM_MILLIS 1
+#define MG_ENABLE_CUSTOM_RANDOM 1
+#define MG_ENABLE_DRIVER_STM32H 1
+
+// #define MG_DRIVER_MDC_CR 4   // RMII MDC clock divider, from 0 to 5
+// #define MG_TCPIP_PHY_ADDR 0  // PHY address
+
+// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
+// By default, those are set to zero, meaning that DHCP is used
+//
+// #define MG_TCPIP_IP MG_IPV4(192, 168, 0, 10)     // IP
+// #define MG_TCPIP_GW MG_IPV4(192, 168, 0, 1)      // Gateway
+// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0)  // Netmask
+
+// Set custom MAC address. By default, it is randomly generated
+// Using a build-time constant:
+// #define MG_SET_MAC_ADDRESS(mac) do { mac[0] = 2; mac[1] = 3; mac[2] = 4; mac[3] = 5; mac[4] = 6; mac[5] = 7; } while (0)
+//
+// Using custom function:
+// extern void my_function(unsigned char *mac);
+// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)
+
+// Construct MAC address from the MCU unique ID. It is defined in the
+// ST CMSIS header as UID_BASE
+#define MGUID ((uint32_t *) 0x1ff1e800)  // Unique 96-bit chip ID
+#define MG_SET_MAC_ADDRESS(mac)      \
+  do {                               \
+    mac[0] = 2;                      \
+    mac[1] = MGUID[0] & 255;         \
+    mac[2] = (MGUID[0] >> 10) & 255; \
+    mac[3] = (MGUID[0] >> 19) & 255; \
+    mac[4] = MGUID[1] & 255;         \
+    mac[5] = MGUID[2] & 255;         \
+  } while (0)