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Add STM32H743ZI driver and example
This commit is contained in:
Sergio R. Caprile committed
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@@ -2,14 +2,14 @@ CFLAGS ?= -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion \
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-Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion \
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-g3 -Os -ffunction-sections -fdata-sections \
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-I. -Ih7/Include -Icmsis/CMSIS/Core/Include \
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-mcpu=cortex-m7 -mthumb -mfloat-abi=soft \
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-mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 \
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$(EXTRA_CFLAGS)
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LDFLAGS ?= -Tlink.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
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SOURCES = startup.c main.c syscalls.c
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# Add Mongoose-specific flags and source files
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CFLAGS += -I../../.. -DMG_ARCH=MG_ARCH_NEWLIB -DMG_ENABLE_CUSTOM_MILLIS=1 -DMG_ENABLE_MIP=1 #-DMG_ENABLE_PACKED_FS=1
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SOURCES += ../../../mongoose.c #../../device-dashboard/net.c ../../device-dashboard/packed_fs.c
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CFLAGS += -I../../.. -DMG_ARCH=MG_ARCH_NEWLIB -DMG_ENABLE_CUSTOM_MILLIS=1 -DMG_ENABLE_MIP=1 -DMG_ENABLE_DRIVER_STM32H=1 -DMG_ENABLE_PACKED_FS=1
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SOURCES += ../../../mongoose.c ../../device-dashboard/net.c ../../device-dashboard/packed_fs.c
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all build example: firmware.bin
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@@ -25,11 +25,11 @@ flash: firmware.bin
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# Requires env variable VCON_API_KEY set
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DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/6
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test: update
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test: EXTRA_CFLAGS += -DUART_DEBUG=UART1
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test: update
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
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grep 'ticks:' /tmp/output.txt
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# grep 'Ethernet: up' /tmp/output.txt
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# grep 'MQTT connected' /tmp/output.txt
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grep 'READY, IP:' /tmp/output.txt
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grep 'MQTT connected' /tmp/output.txt
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update: firmware.bin
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
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@@ -0,0 +1,41 @@
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# Baremetal webserver on NUCLEO-H743ZI
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This firmware uses MIP, an experimental TCP/IP stack of the Mongoose Network Library,
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which implements the following:
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- A complete [HTTP device dashboard](../../device-dashboard) with:
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- User authentication
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- Real-time device data graph
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- Coninfiguration display and update
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- MQTT communication with a remote MQTT server
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- No dependencies: no HAL, no CMSIS, no RTOS
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- Hand-written [mcu.h](mcu.h) header based on the [datasheet](https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf)
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- Interrupt-driven [Ethernet driver](../../../drivers/mip_driver_stm32h.c)
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- Debug log on UART3 (st-link)
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## Requirements
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- [GNU make](http://mongoose.ws/tutorials/tools/#gnu-make)
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- [ARM GCC](http://mongoose.ws/tutorials/tools/#arm-gcc)
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- [stlink](http://mongoose.ws/tutorials/tools/#stlink) for flashing
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The links above will send you to tutorials on how to install each of those tools in your workstation for Linux, Mac, and Windows.
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## Usage
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Plugin your Nucleo board into USB, and attach an Ethernet cable.
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To build and flash:
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```sh
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$ make clean flash
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```
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To see debug log, use any serial monitor program like `picocom` at 115200 bps and configure it to insert carriage returns after line feeds:
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```sh
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$ picocom /dev/ttyACM0 -i -b 115200 --imap=lfcrlf
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```
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There is also a [tutorial on a similar example](https://mongoose.ws/tutorials/stm32/nucleo-f746zg-baremetal/) but for the NUCLEO-F746ZG board
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For more details and benchmark data on MIP, check the [F746ZG example](../nucleo-f746zg-baremetal/)
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@@ -1,7 +1,10 @@
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ENTRY(_reset);
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MEMORY {
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flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k
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sram(rwx) : ORIGIN = 0x20000000, LENGTH = 64k
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sram(rwx) : ORIGIN = 0x24000000, LENGTH = 512k /* AXI SRAM in domain D1 */
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/* 2.3.2: remaining SRAM is in other (non-contiguous) banks,
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DTCM @0x20000000 is in domain D1 and not accessible by the ETH DMA controller in domain D2
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SRAM @0x30000000 is in domain D2 and not directly available at startup to be used as stack (8.5.9 page 366) */
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}
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_estack = ORIGIN(sram) + LENGTH(sram); /* stack points to end of SRAM */
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@@ -1,4 +1,4 @@
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// Copyright (c) 2022 Cesanta Software Limited
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// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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#include "mcu.h"
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@@ -21,9 +21,30 @@ static void timer_cb(void *arg) {
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int main(void) {
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clock_init();
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systick_init(SYS_FREQUENCY / 1000); // Increment s_ticks every ms
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systick_init(CPU_FREQUENCY / 1000); // Increment s_ticks every ms
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gpio_output(LED2); // Setup LED
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uart_init(UART_DEBUG, 115200); // Initialise debug printf
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uart_init(UART_DEBUG, 115200); // Initialise debug printf
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char rev = chiprev();
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MG_INFO(("Chip revision: %c, max cpu clock: %u MHz", rev, (rev == 'V') ? 480 : 400));
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// Initialise Ethernet. Enable MAC GPIO pins, see UM2407 for MB1364 boards
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// section 6.6.7:
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// https://www.st.com/resource/en/user_manual/um2407-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf
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uint16_t pins[] = {PIN('A', 1), PIN('A', 2), PIN('A', 7),
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PIN('B', 13), PIN('C', 1), PIN('C', 4),
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PIN('C', 5), PIN('G', 11), PIN('G', 13)};
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for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
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gpio_init(pins[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
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GPIO_PULL_NONE, 11);
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}
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nvic_enable_irq(61); // Setup Ethernet IRQ handler
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RCC->APB4ENR |= BIT(1); // Enable SYSCFG
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SETBITS(SYSCFG->PMCR, 7 << 21, 4 << 21); // Use RMII (12.3.1)
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RCC->AHB1ENR |= BIT(15) | BIT(16) | BIT(17); // Enable Ethernet clocks
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RCC->AHB1RSTR |= BIT(15); // ETHMAC force reset
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RCC->AHB1RSTR &= ~BIT(15); // ETHMAC release reset
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MG_INFO(("Initialising Mongoose..."));
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struct mg_mgr mgr; // Initialise Mongoose event manager
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@@ -31,10 +52,29 @@ int main(void) {
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mg_log_set(MG_LL_DEBUG); // Set log level
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mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_cb, NULL);
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MG_INFO(("Starting event loop"));
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for (;;) {
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// Initialise Mongoose network stack
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// Specify MAC address, and IP/mask/GW in network byte order for static
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// IP configuration. If IP/mask/GW are unset, DHCP is going to be used
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struct mip_driver_stm32h_data driver_data = {.mdc_cr =
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4}; // See driver_stm32h.h
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struct mip_if mif = {
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.mac = {2, 0, 1, 2, 3, 5},
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.driver = &mip_driver_stm32h,
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.driver_data = &driver_data,
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};
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mip_init(&mgr, &mif);
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MG_INFO(("Waiting until network is up..."));
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while (mif.state != MIP_STATE_READY) {
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mg_mgr_poll(&mgr, 0);
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}
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MG_INFO(("Initialising application..."));
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extern void device_dashboard_fn(struct mg_connection *, int, void *, void *);
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mg_http_listen(&mgr, "http://0.0.0.0", device_dashboard_fn, &mgr);
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MG_INFO(("Starting event loop"));
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for (;;) mg_mgr_poll(&mgr, 0); // Infinite event loop
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return 0;
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}
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@@ -18,22 +18,32 @@
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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// TODO: Set clock. Now, running @ default of 64 MHz
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enum { PLL_HSI = 64, PLL_M = 1, PLL_N = 1, PLL_P = 1 };
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#define FLASH_LATENCY 7
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#define SYS_FREQUENCY ((PLL_HSI * PLL_N / PLL_M / PLL_P) * 1000000)
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#define APB2_FREQUENCY SYS_FREQUENCY
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#define APB1_FREQUENCY SYS_FREQUENCY
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struct systick {
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volatile uint32_t CTRL, LOAD, VAL, CALIB;
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// System clock (2.1, Figure 1; 8.5, Figure 45; 8.5.5, Figure 47; 8.5.6, Figure
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// 49) CPU_FREQUENCY <= 480 MHz; hclk = CPU_FREQUENCY / HPRE ; hclk <= 240 MHz;
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// APB clocks <= 120 MHz. D1 domain bus matrix (and so flash) runs at hclk
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// frequency. Configure flash latency (WS) in accordance to hclk freq (4.3.8,
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// Table 17) The Ethernet controller is in D2 domain and runs at hclk frequency
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enum {
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D1CPRE = 1, // actual divisor value
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HPRE = 2, // actual divisor value
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D1PPRE = 4, // register values, divisor value = BIT(value - 3) = / 2
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D2PPRE1 = 4,
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D2PPRE2 = 4,
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D3PPRE = 4
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};
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#define SYSTICK ((struct systick *) 0xe000e010)
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static inline void systick_init(uint32_t ticks) {
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if ((ticks - 1) > 0xffffff) return; // Systick timer is 24 bit
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SYSTICK->LOAD = ticks - 1;
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SYSTICK->VAL = 0;
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SYSTICK->CTRL = BIT(0) | BIT(1) | BIT(2); // Enable systick
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// PLL1_P: odd division factors are not allowed (8.7.13) (according to Cube, '1'
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// is also an "odd division factor").
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// Make sure your chip is revision 'V', otherwise set PLL1_N = 400
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enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 480, PLL1_P = 2 };
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#define FLASH_LATENCY 0x24 // WRHIGHFREQ LATENCY
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#define CPU_FREQUENCY ((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / D1CPRE) * 1000000)
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// #define CPU_FREQUENCY ((PLL1_HSI / D1CPRE) * 1000000)
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#define AHB_FREQUENCY (CPU_FREQUENCY / HPRE)
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#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(D2PPRE2 - 3)))
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#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(D2PPRE1 - 3)))
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static inline void spin(volatile uint32_t n) {
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while (n--) (void) 0;
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}
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struct rcc {
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@@ -48,10 +58,56 @@ struct rcc {
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APB3LPENR, APB1LLPENR, APB1HLPENR, APB2LPENR, APB4LPENR, RESERVED13[4];
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};
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#define RCC ((struct rcc *) (0x40000000 + 0x18020000 + 0x4400))
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struct pwr {
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volatile uint32_t CR1, CSR1, CR2, CR3, CPUCR, RESERVED0, D3CR, RESERVED1,
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WKUPCR, WKUPFR, WKUPEPR;
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};
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#define PWR ((struct pwr *) (0x40000000 + 0x18020000 + 0x4800))
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static inline void spin(volatile uint32_t n) {
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while (n--) (void) 0;
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struct nvic {
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volatile uint32_t ISER[8], RESERVED0[24], ICER[8], RSERVED1[24], ISPR[8],
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RESERVED2[24], ICPR[8], RESERVED3[24], IABR[8], RESERVED4[56], IP[240],
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RESERVED5[644], STIR;
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};
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#define NVIC ((struct nvic *) 0xe000e100)
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static inline void nvic_set_prio(int irq, uint32_t prio) {
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NVIC->IP[irq] = prio << 4;
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}
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static inline void nvic_enable_irq(int irq) {
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NVIC->ISER[irq >> 5] = (uint32_t) (1 << (irq & 31));
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}
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struct systick {
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volatile uint32_t CTRL, LOAD, VAL, CALIB;
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};
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#define SYSTICK ((struct systick *) 0xe000e010)
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static inline void systick_init(uint32_t ticks) {
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if ((ticks - 1) > 0xffffff) return; // Systick timer is 24 bit
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SYSTICK->LOAD = ticks - 1;
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SYSTICK->VAL = 0;
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SYSTICK->CTRL = BIT(0) | BIT(1) | BIT(2); // Enable systick
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}
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struct flash {
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volatile uint32_t ACR, KEYR1, OPTKEYR, CR1, SR1, CCR1, OPTCR, OPTSR_CUR,
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OPTSR_PRG, OPTCCR, PRAR_CUR1, PRAR_PRG1, SCAR_CUR1, SCAR_PRG1, WPSN_CUR1,
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WPSN_PRG1, BOOT_CUR, BOOT_PRG, RESERVED0, CRCCR1, CRCSADD1, CRCEADD1,
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CRCDATA, ECC_FA1, RESERVED1, KEYR2, RESERVED2, CR2, SR2, CCR2, RESERVED3,
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PRAR_CUR2, PRAR_PRG2, SCAR_CUR2, SCAR_PRG2, WPSN_CUR2, WPSN_PRG2,
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RESERVED4, CRCCR2, CRCSADD2, CRCEADD2, CRCDATA2, ECC_FA2;
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};
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#define FLASH ((struct flash *) (0x40000000UL + 0x12000000UL + 0x2000UL))
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struct scb {
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volatile uint32_t CPUID, ICSR, VTOR, AIRCR, SCR, CCR, SHPR[3], SHCSR, CFSR,
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HFSR, DFSR, MMFAR, BFAR, AFSR, ID_PFR[2], ID_DFR, ID_AFR, ID_MFR[4],
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ID_ISAR[5], RESERVED0[1], CLIDR, CTR, CCSIDR, CSSELR, CPACR,
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RESERVED3[93], STIR, RESERVED4[15], MVFR0, MVFR1, MVFR2, RESERVED5[1],
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ICIALLU, RESERVED6[1], ICIMVAU, DCIMVAC, DCISW, DCCMVAU, DCCMVAC, DCCSW,
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DCCIMVAC, DCCISW, RESERVED7[6], ITCMCR, DTCMCR, AHBPCR, CACR, AHBSCR,
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RESERVED8[1], ABFSR;
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};
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#define SCB ((struct scb *) 0xe000ed00)
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enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
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enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
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@@ -63,7 +119,9 @@ struct gpio {
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};
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#define GPIO(N) ((struct gpio *) (0x40000000 + 0x18020000UL + 0x400 * (N)))
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static struct gpio *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
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static struct gpio *gpio_bank(uint16_t pin) {
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return GPIO(PINBANK(pin));
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}
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static inline void gpio_toggle(uint16_t pin) {
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struct gpio *gpio = gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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@@ -97,6 +155,13 @@ static inline void gpio_output(uint16_t pin) {
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GPIO_PULL_NONE, 0);
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}
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struct syscfg {
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volatile uint32_t RESERVED1, PMCR, EXTICR[4], CFGR, RESERVED2, CCCSR, CCVR,
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CCCR, PWRCR, RESERVED3[61], PKGR, RESERVED4[118], UR0, UR1, UR2, UR3, UR4,
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UR5, UR6, UR7, UR8, UR9, UR10, UR11, UR12, UR13, UR14, UR15, UR16, UR17;
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};
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#define SYSCFG ((struct syscfg *) (0x40000000UL + 0x18000000UL + 0x0400UL))
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struct uart {
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volatile uint32_t CR1, CR2, CR3, BRR, GTPR, RTOR, RQR, ISR, ICR, RDR, TDR,
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PRESC;
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@@ -106,6 +171,10 @@ struct uart {
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#define UART3 ((struct uart *) 0x40004800)
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#define UART_DEBUG UART1
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// D2 Kernel clock (8.7.21) USART1 defaults to pclk2 (APB2), while USART2,3
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// default to pclk1 (APB1). Even if using other kernel clocks, the APBx clocks
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// must be enabled for CPU access, as the kernel clock drives the BRR, not the
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// APB bus interface
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static inline void uart_init(struct uart *uart, unsigned long baud) {
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uint8_t af = 7; // Alternate function
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uint16_t rx = 0, tx = 0; // pins
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@@ -119,7 +188,10 @@ static inline void uart_init(struct uart *uart, unsigned long baud) {
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if (uart == UART2) tx = PIN('A', 2), rx = PIN('A', 3);
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if (uart == UART3) tx = PIN('D', 8), rx = PIN('D', 9);
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freq = SYS_FREQUENCY;
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#if 0 // CONSTANT BAUD RATE FOR REMOTE DEBUGGING WHILE SETTING THE PLL
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SETBITS(RCC->D2CCIP2R, 7 << 3, 3 << 3); // use HSI for UART1
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freq = 64000000;
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#endif
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gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
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@@ -141,6 +213,66 @@ static inline uint8_t uart_read_byte(struct uart *uart) {
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return (uint8_t) (uart->RDR & 255);
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}
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struct dbgmcu {
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volatile uint32_t IDCODE, CR, RESERVED4, APB3FZ1, RESERVED5, APB1LFZ1,
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RESERVED6, APB1HFZ1, RESERVED7, APB2FZ1, RESERVED8, APB4FZ1;
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};
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#define DBGMCU ((struct dbgmcu *) 0x5C001000UL)
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static inline char chiprev(void) {
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uint16_t rev = (uint16_t)(((uint32_t) DBGMCU->IDCODE) >> 16);
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if (rev == 0x1003) return 'Y';
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if (rev == 0x2003) return 'V';
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return '?';
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}
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static inline unsigned int div2prescval(unsigned int div) {
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// 0 --> /1; 8 --> /2 ... 11 --> /16; 12 --> /64 ... 15 --> /512
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if (div == 1) return 0;
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if (div > 16) div /= 2;
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unsigned int val = 7;
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while (div >>= 1) ++val;
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return val;
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}
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static inline unsigned int pllrge(unsigned int f) {
|
||||
unsigned int val = 0;
|
||||
while (f >>= 1) ++val;
|
||||
return val - 1;
|
||||
}
|
||||
|
||||
static inline void clock_init(void) {
|
||||
// TODO: Enable FPU, set flash latency, set clock
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
asm("DSB");
|
||||
asm("ISB");
|
||||
PWR->CR3 |= BIT(1); // select LDO (reset value)
|
||||
while ((PWR->CSR1 && BIT(13)) == 0) spin(1); // ACTVOSRDY
|
||||
PWR->D3CR |= BIT(15) | BIT(14); // Select VOS1
|
||||
uint32_t f = PWR->D3CR; // fake read to wait for bus clocking
|
||||
while ((PWR->CSR1 && BIT(13)) == 0) spin(1); // ACTVOSRDY
|
||||
SYSCFG->PWRCR |= BIT(0); // ODEN
|
||||
f = SYSCFG->PWRCR;
|
||||
while ((PWR->CSR1 && BIT(13)) == 0) spin(1); // ACTVOSRDY
|
||||
(void) f;
|
||||
SETBITS(
|
||||
RCC->D1CFGR, (0x0F << 8) | (7 << 4) | (0x0F << 0),
|
||||
(div2prescval(D1CPRE) << 8) | (D1PPRE << 4) | (div2prescval(HPRE) << 0));
|
||||
RCC->D2CFGR = (D2PPRE2 << 8) | (D2PPRE1 << 4);
|
||||
RCC->D3CFGR = (D3PPRE << 4);
|
||||
SETBITS(RCC->PLLCFGR, 3 << 2,
|
||||
pllrge(PLL1_HSI / PLL1_M)
|
||||
<< 2); // keep reset config (DIVP1EN, !PLL1VCOSEL), PLL1RGE
|
||||
SETBITS(RCC->PLL1DIVR, (0x7F << 9) | (0x1FF << 0),
|
||||
((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0)); // Set PLL1_P PLL1_N
|
||||
SETBITS(RCC->PLLCKSELR, 0x3F << 4,
|
||||
PLL1_M << 4); // Set PLL1_M (source defaults to HSI)
|
||||
RCC->CR |= BIT(24); // Enable PLL1
|
||||
while ((RCC->CR & BIT(25)) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR |= (3 << 0); // Set clock source to PLL1
|
||||
while ((RCC->CFGR & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
|
||||
FLASH->ACR |= FLASH_LATENCY; // default is larger
|
||||
#if 0
|
||||
// Enable SRAM block if you want to use it for ETH buffer (needs proper attributes in driver code)
|
||||
// RCC->AHB2ENR |= BIT(29) | BIT(30) | BIT(31);
|
||||
#endif
|
||||
}
|
||||
@@ -30,6 +30,146 @@ WEAK_ALIAS void DebugMon_Handler(void);
|
||||
WEAK_ALIAS void PendSV_Handler(void);
|
||||
WEAK_ALIAS void SysTick_Handler(void);
|
||||
|
||||
WEAK_ALIAS void WWDG_IRQHandler(void);
|
||||
WEAK_ALIAS void PVD_AVD_IRQHandler(void);
|
||||
WEAK_ALIAS void TAMP_STAMP_IRQHandler(void);
|
||||
WEAK_ALIAS void RTC_WKUP_IRQHandler(void);
|
||||
WEAK_ALIAS void FLASH_IRQHandler(void);
|
||||
WEAK_ALIAS void RCC_IRQHandler(void);
|
||||
WEAK_ALIAS void EXTI0_IRQHandler(void);
|
||||
WEAK_ALIAS void EXTI1_IRQHandler(void);
|
||||
WEAK_ALIAS void EXTI2_IRQHandler(void);
|
||||
WEAK_ALIAS void EXTI3_IRQHandler(void);
|
||||
WEAK_ALIAS void EXTI4_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA1_Stream0_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA1_Stream1_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA1_Stream2_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA1_Stream3_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA1_Stream4_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA1_Stream5_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA1_Stream6_IRQHandler(void);
|
||||
WEAK_ALIAS void ADC_IRQHandler(void);
|
||||
WEAK_ALIAS void FDCAN1_IT0_IRQHandler(void);
|
||||
WEAK_ALIAS void FDCAN2_IT0_IRQHandler(void);
|
||||
WEAK_ALIAS void FDCAN1_IT1_IRQHandler(void);
|
||||
WEAK_ALIAS void FDCAN2_IT1_IRQHandler(void);
|
||||
WEAK_ALIAS void EXTI9_5_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM1_BRK_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM1_UP_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM1_TRG_COM_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM1_CC_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM2_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM3_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM4_IRQHandler(void);
|
||||
WEAK_ALIAS void I2C1_EV_IRQHandler(void);
|
||||
WEAK_ALIAS void I2C1_ER_IRQHandler(void);
|
||||
WEAK_ALIAS void I2C2_EV_IRQHandler(void);
|
||||
WEAK_ALIAS void I2C2_ER_IRQHandler(void);
|
||||
WEAK_ALIAS void SPI1_IRQHandler(void);
|
||||
WEAK_ALIAS void SPI2_IRQHandler(void);
|
||||
WEAK_ALIAS void USART1_IRQHandler(void);
|
||||
WEAK_ALIAS void USART2_IRQHandler(void);
|
||||
WEAK_ALIAS void USART3_IRQHandler(void);
|
||||
WEAK_ALIAS void EXTI15_10_IRQHandler(void);
|
||||
WEAK_ALIAS void RTC_Alarm_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM8_BRK_TIM12_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM8_UP_TIM13_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM8_TRG_COM_TIM14_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM8_CC_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA1_Stream7_IRQHandler(void);
|
||||
WEAK_ALIAS void FMC_IRQHandler(void);
|
||||
WEAK_ALIAS void SDMMC1_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM5_IRQHandler(void);
|
||||
WEAK_ALIAS void SPI3_IRQHandler(void);
|
||||
WEAK_ALIAS void UART4_IRQHandler(void);
|
||||
WEAK_ALIAS void UART5_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM6_DAC_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM7_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA2_Stream0_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA2_Stream1_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA2_Stream2_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA2_Stream3_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA2_Stream4_IRQHandler(void);
|
||||
WEAK_ALIAS void ETH_IRQHandler(void);
|
||||
WEAK_ALIAS void ETH_WKUP_IRQHandler(void);
|
||||
WEAK_ALIAS void FDCAN_CAL_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA2_Stream5_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA2_Stream6_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA2_Stream7_IRQHandler(void);
|
||||
WEAK_ALIAS void USART6_IRQHandler(void);
|
||||
WEAK_ALIAS void I2C3_EV_IRQHandler(void);
|
||||
WEAK_ALIAS void I2C3_ER_IRQHandler(void);
|
||||
WEAK_ALIAS void OTG_HS_EP1_OUT_IRQHandler(void);
|
||||
WEAK_ALIAS void OTG_HS_EP1_IN_IRQHandler(void);
|
||||
WEAK_ALIAS void OTG_HS_WKUP_IRQHandler(void);
|
||||
WEAK_ALIAS void OTG_HS_IRQHandler(void);
|
||||
WEAK_ALIAS void DCMI_IRQHandler(void);
|
||||
WEAK_ALIAS void RNG_IRQHandler(void);
|
||||
WEAK_ALIAS void FPU_IRQHandler(void);
|
||||
WEAK_ALIAS void UART7_IRQHandler(void);
|
||||
WEAK_ALIAS void UART8_IRQHandler(void);
|
||||
WEAK_ALIAS void SPI4_IRQHandler(void);
|
||||
WEAK_ALIAS void SPI5_IRQHandler(void);
|
||||
WEAK_ALIAS void SPI6_IRQHandler(void);
|
||||
WEAK_ALIAS void SAI1_IRQHandler(void);
|
||||
WEAK_ALIAS void LTDC_IRQHandler(void);
|
||||
WEAK_ALIAS void LTDC_ER_IRQHandler(void);
|
||||
WEAK_ALIAS void DMA2D_IRQHandler(void);
|
||||
WEAK_ALIAS void SAI2_IRQHandler(void);
|
||||
WEAK_ALIAS void QUADSPI_IRQHandler(void);
|
||||
WEAK_ALIAS void LPTIM1_IRQHandler(void);
|
||||
WEAK_ALIAS void CEC_IRQHandler(void);
|
||||
WEAK_ALIAS void I2C4_EV_IRQHandler(void);
|
||||
WEAK_ALIAS void I2C4_ER_IRQHandler(void);
|
||||
WEAK_ALIAS void SPDIF_RX_IRQHandler(void);
|
||||
WEAK_ALIAS void OTG_FS_EP1_OUT_IRQHandler(void);
|
||||
WEAK_ALIAS void OTG_FS_EP1_IN_IRQHandler(void);
|
||||
WEAK_ALIAS void OTG_FS_WKUP_IRQHandler(void);
|
||||
WEAK_ALIAS void OTG_FS_IRQHandler(void);
|
||||
WEAK_ALIAS void DMAMUX1_OVR_IRQHandler(void);
|
||||
WEAK_ALIAS void HRTIM1_Master_IRQHandler(void);
|
||||
WEAK_ALIAS void HRTIM1_TIMA_IRQHandler(void);
|
||||
WEAK_ALIAS void HRTIM1_TIMB_IRQHandler(void);
|
||||
WEAK_ALIAS void HRTIM1_TIMC_IRQHandler(void);
|
||||
WEAK_ALIAS void HRTIM1_TIMD_IRQHandler(void);
|
||||
WEAK_ALIAS void HRTIM1_TIME_IRQHandler(void);
|
||||
WEAK_ALIAS void HRTIM1_FLT_IRQHandler(void);
|
||||
WEAK_ALIAS void DFSDM1_FLT0_IRQHandler(void);
|
||||
WEAK_ALIAS void DFSDM1_FLT1_IRQHandler(void);
|
||||
WEAK_ALIAS void DFSDM1_FLT2_IRQHandler(void);
|
||||
WEAK_ALIAS void DFSDM1_FLT3_IRQHandler(void);
|
||||
WEAK_ALIAS void SAI3_IRQHandler(void);
|
||||
WEAK_ALIAS void SWPMI1_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM15_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM16_IRQHandler(void);
|
||||
WEAK_ALIAS void TIM17_IRQHandler(void);
|
||||
WEAK_ALIAS void MDIOS_WKUP_IRQHandler(void);
|
||||
WEAK_ALIAS void MDIOS_IRQHandler(void);
|
||||
WEAK_ALIAS void JPEG_IRQHandler(void);
|
||||
WEAK_ALIAS void MDMA_IRQHandler(void);
|
||||
WEAK_ALIAS void SDMMC2_IRQHandler(void);
|
||||
WEAK_ALIAS void HSEM1_IRQHandler(void);
|
||||
WEAK_ALIAS void ADC3_IRQHandler(void);
|
||||
WEAK_ALIAS void DMAMUX2_OVR_IRQHandler(void);
|
||||
WEAK_ALIAS void BDMA_Channel0_IRQHandler(void);
|
||||
WEAK_ALIAS void BDMA_Channel1_IRQHandler(void);
|
||||
WEAK_ALIAS void BDMA_Channel2_IRQHandler(void);
|
||||
WEAK_ALIAS void BDMA_Channel3_IRQHandler(void);
|
||||
WEAK_ALIAS void BDMA_Channel4_IRQHandler(void);
|
||||
WEAK_ALIAS void BDMA_Channel5_IRQHandler(void);
|
||||
WEAK_ALIAS void BDMA_Channel6_IRQHandler(void);
|
||||
WEAK_ALIAS void BDMA_Channel7_IRQHandler(void);
|
||||
WEAK_ALIAS void COMP1_IRQHandler(void);
|
||||
WEAK_ALIAS void LPTIM2_IRQHandler(void);
|
||||
WEAK_ALIAS void LPTIM3_IRQHandler(void);
|
||||
WEAK_ALIAS void LPTIM4_IRQHandler(void);
|
||||
WEAK_ALIAS void LPTIM5_IRQHandler(void);
|
||||
WEAK_ALIAS void LPUART1_IRQHandler(void);
|
||||
WEAK_ALIAS void CRS_IRQHandler(void);
|
||||
WEAK_ALIAS void ECC_IRQHandler(void);
|
||||
WEAK_ALIAS void SAI4_IRQHandler(void);
|
||||
WEAK_ALIAS void WAKEUP_PIN_IRQHandler(void);
|
||||
|
||||
// IRQ table
|
||||
extern void _estack();
|
||||
__attribute__((section(".vectors"))) void (*tab[16 + 150])(void) = {
|
||||
@@ -39,4 +179,48 @@ __attribute__((section(".vectors"))) void (*tab[16 + 150])(void) = {
|
||||
DebugMon_Handler, 0, PendSV_Handler, SysTick_Handler,
|
||||
|
||||
// Interrupts from peripherals
|
||||
DefaultIRQHandler};
|
||||
WWDG_IRQHandler, PVD_AVD_IRQHandler, TAMP_STAMP_IRQHandler,
|
||||
RTC_WKUP_IRQHandler, FLASH_IRQHandler, RCC_IRQHandler, EXTI0_IRQHandler,
|
||||
EXTI1_IRQHandler, EXTI2_IRQHandler, EXTI3_IRQHandler, EXTI4_IRQHandler,
|
||||
DMA1_Stream0_IRQHandler, DMA1_Stream1_IRQHandler, DMA1_Stream2_IRQHandler,
|
||||
DMA1_Stream3_IRQHandler, DMA1_Stream4_IRQHandler, DMA1_Stream5_IRQHandler,
|
||||
DMA1_Stream6_IRQHandler, ADC_IRQHandler, FDCAN1_IT0_IRQHandler,
|
||||
FDCAN2_IT0_IRQHandler, FDCAN1_IT1_IRQHandler, FDCAN2_IT1_IRQHandler,
|
||||
EXTI9_5_IRQHandler, TIM1_BRK_IRQHandler, TIM1_UP_IRQHandler,
|
||||
TIM1_TRG_COM_IRQHandler, TIM1_CC_IRQHandler, TIM2_IRQHandler,
|
||||
TIM3_IRQHandler, TIM4_IRQHandler, I2C1_EV_IRQHandler, I2C1_ER_IRQHandler,
|
||||
I2C2_EV_IRQHandler, I2C2_ER_IRQHandler, SPI1_IRQHandler, SPI2_IRQHandler,
|
||||
USART1_IRQHandler, USART2_IRQHandler, USART3_IRQHandler,
|
||||
EXTI15_10_IRQHandler, RTC_Alarm_IRQHandler, 0, TIM8_BRK_TIM12_IRQHandler,
|
||||
TIM8_UP_TIM13_IRQHandler, TIM8_TRG_COM_TIM14_IRQHandler, TIM8_CC_IRQHandler,
|
||||
DMA1_Stream7_IRQHandler, FMC_IRQHandler, SDMMC1_IRQHandler, TIM5_IRQHandler,
|
||||
SPI3_IRQHandler, UART4_IRQHandler, UART5_IRQHandler, TIM6_DAC_IRQHandler,
|
||||
TIM7_IRQHandler, DMA2_Stream0_IRQHandler, DMA2_Stream1_IRQHandler,
|
||||
DMA2_Stream2_IRQHandler, DMA2_Stream3_IRQHandler, DMA2_Stream4_IRQHandler,
|
||||
ETH_IRQHandler, ETH_WKUP_IRQHandler, FDCAN_CAL_IRQHandler, 0, 0, 0, 0,
|
||||
DMA2_Stream5_IRQHandler, DMA2_Stream6_IRQHandler, DMA2_Stream7_IRQHandler,
|
||||
USART6_IRQHandler, I2C3_EV_IRQHandler, I2C3_ER_IRQHandler,
|
||||
OTG_HS_EP1_OUT_IRQHandler, OTG_HS_EP1_IN_IRQHandler, OTG_HS_WKUP_IRQHandler,
|
||||
OTG_HS_IRQHandler, DCMI_IRQHandler, 0, RNG_IRQHandler, FPU_IRQHandler,
|
||||
UART7_IRQHandler, UART8_IRQHandler, SPI4_IRQHandler, SPI5_IRQHandler,
|
||||
SPI6_IRQHandler, SAI1_IRQHandler, LTDC_IRQHandler, LTDC_ER_IRQHandler,
|
||||
DMA2D_IRQHandler, SAI2_IRQHandler, QUADSPI_IRQHandler, LPTIM1_IRQHandler,
|
||||
CEC_IRQHandler, I2C4_EV_IRQHandler, I2C4_ER_IRQHandler, SPDIF_RX_IRQHandler,
|
||||
OTG_FS_EP1_OUT_IRQHandler, OTG_FS_EP1_IN_IRQHandler, OTG_FS_WKUP_IRQHandler,
|
||||
OTG_FS_IRQHandler, DMAMUX1_OVR_IRQHandler, HRTIM1_Master_IRQHandler,
|
||||
HRTIM1_TIMA_IRQHandler, HRTIM1_TIMB_IRQHandler, HRTIM1_TIMC_IRQHandler,
|
||||
HRTIM1_TIMD_IRQHandler, HRTIM1_TIME_IRQHandler, HRTIM1_FLT_IRQHandler,
|
||||
DFSDM1_FLT0_IRQHandler, DFSDM1_FLT1_IRQHandler, DFSDM1_FLT2_IRQHandler,
|
||||
DFSDM1_FLT3_IRQHandler, SAI3_IRQHandler, SWPMI1_IRQHandler,
|
||||
TIM15_IRQHandler, TIM16_IRQHandler, TIM17_IRQHandler, MDIOS_WKUP_IRQHandler,
|
||||
MDIOS_IRQHandler, JPEG_IRQHandler, MDMA_IRQHandler, 0, SDMMC2_IRQHandler,
|
||||
HSEM1_IRQHandler, 0, ADC3_IRQHandler, DMAMUX2_OVR_IRQHandler,
|
||||
BDMA_Channel0_IRQHandler, BDMA_Channel1_IRQHandler,
|
||||
BDMA_Channel2_IRQHandler, BDMA_Channel3_IRQHandler,
|
||||
BDMA_Channel4_IRQHandler, BDMA_Channel5_IRQHandler,
|
||||
BDMA_Channel6_IRQHandler, BDMA_Channel7_IRQHandler, COMP1_IRQHandler,
|
||||
LPTIM2_IRQHandler, LPTIM3_IRQHandler, LPTIM4_IRQHandler, LPTIM5_IRQHandler,
|
||||
LPUART1_IRQHandler, 0, CRS_IRQHandler, ECC_IRQHandler, SAI4_IRQHandler, 0,
|
||||
0, WAKEUP_PIN_IRQHandler
|
||||
}
|
||||
;
|
||||
Reference in new issue
Block a user