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Add STM32H743ZI driver and example
This commit is contained in:
Sergio R. Caprile committed
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@@ -1,7 +1,6 @@
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#include "mip.h"
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#if MG_ENABLE_MIP && \
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(!defined(MG_ENABLE_DRIVER_TM4C) || MG_ENABLE_DRIVER_TM4C == 0)
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#if MG_ENABLE_MIP && MG_ENABLE_DRIVER_STM32
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struct stm32_eth {
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volatile uint32_t MACCR, MACFFR, MACHTHR, MACHTLR, MACMIIAR, MACMIIDR, MACFCR,
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MACVLANTR, RESERVED0[2], MACRWUFFR, MACPMTCSR, RESERVED1, MACDBGR, MACSR,
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@@ -0,0 +1,276 @@
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#include "mip.h"
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#if MG_ENABLE_MIP && defined(MG_ENABLE_DRIVER_STM32H) && MG_ENABLE_DRIVER_STM32H
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struct stm32h_eth {
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volatile uint32_t MACCR, MACECR, MACPFR, MACWTR, MACHT0R, MACHT1R,
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RESERVED1[14], MACVTR, RESERVED2, MACVHTR, RESERVED3, MACVIR, MACIVIR,
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RESERVED4[2], MACTFCR, RESERVED5[7], MACRFCR, RESERVED6[7], MACISR,
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MACIER, MACRXTXSR, RESERVED7, MACPCSR, MACRWKPFR, RESERVED8[2], MACLCSR,
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MACLTCR, MACLETR, MAC1USTCR, RESERVED9[12], MACVR, MACDR, RESERVED10,
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MACHWF0R, MACHWF1R, MACHWF2R, RESERVED11[54], MACMDIOAR, MACMDIODR,
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RESERVED12[2], MACARPAR, RESERVED13[59], MACA0HR, MACA0LR, MACA1HR,
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MACA1LR, MACA2HR, MACA2LR, MACA3HR, MACA3LR, RESERVED14[248], MMCCR,
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MMCRIR, MMCTIR, MMCRIMR, MMCTIMR, RESERVED15[14], MMCTSCGPR, MMCTMCGPR,
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RESERVED16[5], MMCTPCGR, RESERVED17[10], MMCRCRCEPR, MMCRAEPR,
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RESERVED18[10], MMCRUPGR, RESERVED19[9], MMCTLPIMSTR, MMCTLPITCR,
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MMCRLPIMSTR, MMCRLPITCR, RESERVED20[65], MACL3L4C0R, MACL4A0R,
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RESERVED21[2], MACL3A0R0R, MACL3A1R0R, MACL3A2R0R, MACL3A3R0R,
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RESERVED22[4], MACL3L4C1R, MACL4A1R, RESERVED23[2], MACL3A0R1R,
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MACL3A1R1R, MACL3A2R1R, MACL3A3R1R, RESERVED24[108], MACTSCR, MACSSIR,
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MACSTSR, MACSTNR, MACSTSUR, MACSTNUR, MACTSAR, RESERVED25, MACTSSR,
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RESERVED26[3], MACTTSSNR, MACTTSSSR, RESERVED27[2], MACACR, RESERVED28,
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MACATSNR, MACATSSR, MACTSIACR, MACTSEACR, MACTSICNR, MACTSECNR,
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RESERVED29[4], MACPPSCR, RESERVED30[3], MACPPSTTSR, MACPPSTTNR, MACPPSIR,
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MACPPSWR, RESERVED31[12], MACPOCR, MACSPI0R, MACSPI1R, MACSPI2R, MACLMIR,
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RESERVED32[11], MTLOMR, RESERVED33[7], MTLISR, RESERVED34[55], MTLTQOMR,
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MTLTQUR, MTLTQDR, RESERVED35[8], MTLQICSR, MTLRQOMR, MTLRQMPOCR, MTLRQDR,
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RESERVED36[177], DMAMR, DMASBMR, DMAISR, DMADSR, RESERVED37[60], DMACCR,
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DMACTCR, DMACRCR, RESERVED38[2], DMACTDLAR, RESERVED39, DMACRDLAR,
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DMACTDTPR, RESERVED40, DMACRDTPR, DMACTDRLR, DMACRDRLR, DMACIER,
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DMACRIWTR, DMACSFCSR, RESERVED41, DMACCATDR, RESERVED42, DMACCARDR,
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RESERVED43, DMACCATBR, RESERVED44, DMACCARBR, DMACSR, RESERVED45[2],
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DMACMFCR;
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};
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#undef ETH
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#define ETH \
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((struct stm32h_eth *) (uintptr_t) (0x40000000UL + 0x00020000UL + 0x8000UL))
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#undef BIT
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#define BIT(x) ((uint32_t) 1 << (x))
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#define ETH_PKT_SIZE 1540 // Max frame size
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#define ETH_DESC_CNT 4 // Descriptors count
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#define ETH_DS 4 // Descriptor size (words)
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static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
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static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
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static struct mip_if *s_ifp; // MIP interface
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enum {
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PHY_ADDR = 0,
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PHY_BCR = 0,
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PHY_BSR = 1,
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PHY_CSCR = 31
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}; // PHY constants
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static uint32_t eth_read_phy(uint8_t addr, uint8_t reg) {
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ETH->MACMDIOAR &= (0xF << 8);
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ETH->MACMDIOAR |= ((uint32_t) addr << 21) | ((uint32_t) reg << 16) | 3 << 2;
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ETH->MACMDIOAR |= BIT(0);
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while (ETH->MACMDIOAR & BIT(0)) (void) 0;
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return ETH->MACMDIODR;
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}
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static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
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ETH->MACMDIODR = val;
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ETH->MACMDIOAR &= (0xF << 8);
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ETH->MACMDIOAR |= ((uint32_t) addr << 21) | ((uint32_t) reg << 16) | 1 << 2;
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ETH->MACMDIOAR |= BIT(0);
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while (ETH->MACMDIOAR & BIT(0)) (void) 0;
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}
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static uint32_t get_hclk(void) {
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struct rcc {
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volatile uint32_t CR, HSICFGR, CRRCR, CSICFGR, CFGR, RESERVED1, D1CFGR,
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D2CFGR, D3CFGR, RESERVED2, PLLCKSELR, PLLCFGR, PLL1DIVR, PLL1FRACR,
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PLL2DIVR, PLL2FRACR, PLL3DIVR, PLL3FRACR, RESERVED3, D1CCIPR, D2CCIP1R,
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D2CCIP2R, D3CCIPR, RESERVED4, CIER, CIFR, CICR, RESERVED5, BDCR, CSR,
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RESERVED6, AHB3RSTR, AHB1RSTR, AHB2RSTR, AHB4RSTR, APB3RSTR, APB1LRSTR,
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APB1HRSTR, APB2RSTR, APB4RSTR, GCR, RESERVED8, D3AMR, RESERVED11[9],
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RSR, AHB3ENR, AHB1ENR, AHB2ENR, AHB4ENR, APB3ENR, APB1LENR, APB1HENR,
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APB2ENR, APB4ENR, RESERVED12, AHB3LPENR, AHB1LPENR, AHB2LPENR,
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AHB4LPENR, APB3LPENR, APB1LLPENR, APB1HLPENR, APB2LPENR, APB4LPENR,
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RESERVED13[4];
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} *rcc = ((struct rcc *) (0x40000000 + 0x18020000 + 0x4400));
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uint32_t clk = 0, hsi = 64000000 /* 64 MHz */, hse = 8000000 /* 8MHz */,
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csi = 4000000 /* 4MHz */;
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unsigned int sel = (rcc->CFGR & (7 << 3)) >> 3;
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if (sel == 1) {
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clk = csi;
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} else if (sel == 2) {
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clk = hse;
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} else if (sel == 3) {
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uint32_t vco, m, n, p;
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unsigned int src = (rcc->PLLCKSELR & (3 << 0)) >> 0;
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m = ((rcc->PLLCKSELR & (0x3F << 4)) >> 4);
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n = ((rcc->PLL1DIVR & (0x1FF << 0)) >> 0) + 1 +
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((rcc->PLLCFGR & BIT(0)) ? 1 : 0); // round-up in fractional mode
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p = ((rcc->PLL1DIVR & (0x7F << 9)) >> 9) + 1;
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if (src == 1) {
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clk = csi;
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} else if (src == 2) {
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clk = hse;
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} else {
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clk = hsi;
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clk >>= ((rcc->CR & 3) >> 3);
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}
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vco = (uint32_t) ((uint64_t) clk * n / m);
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clk = vco / p;
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} else {
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clk = hsi;
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clk >>= ((rcc->CR & 3) >> 3);
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}
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const uint8_t cptab[12] = {1, 2, 3, 4, 6, 7, 8, 9}; // log2(div)
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uint32_t d1cpre = (rcc->D1CFGR & (0x0F << 8)) >> 8;
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if (d1cpre >= 8) clk >>= cptab[d1cpre - 8];
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MG_DEBUG(("D1 CLK: %u", clk));
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uint32_t hpre = (rcc->D1CFGR & (0x0F << 0)) >> 0;
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if (hpre < 8) return clk;
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return ((uint32_t) clk) >> cptab[hpre - 8];
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}
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// Guess CR from AHB1 clock. MDC clock is generated from the ETH peripheral
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// clock (AHB1); as per 802.3, it must not exceed 2. As the AHB clock can
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// be derived from HSI or CSI (internal RC) clocks, and those can go above
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// specs, the datasheets specify a range of frequencies and activate one of a
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// series of dividers to keep the MDC clock safely below 2.5MHz. We guess a
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// divider setting based on HCLK with some drift. If the user uses a different
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// clock from our defaults, needs to set the macros on top. Valid for
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// STM32H74xxx/75xxx (58.11.4)(4.5% worst case drift)(CSI clock has a 7.5 %
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// worst case drift @ max temp)
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static int guess_mdc_cr(void) {
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const uint8_t crs[] = {2, 3, 0, 1, 4, 5}; // ETH->MACMDIOAR::CR values
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const uint8_t div[] = {16, 26, 42, 62, 102, 124}; // Respective HCLK dividers
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uint32_t hclk = get_hclk(); // Guess system HCLK
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int result = -1; // Invalid CR value
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for (int i = 0; i < 6; i++) {
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if (hclk / div[i] <= 2375000UL /* 2.5MHz - 5% */) {
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result = crs[i];
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break;
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}
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}
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if (result < 0) MG_ERROR(("HCLK too high"));
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MG_DEBUG(("HCLK: %u, CR: %d", hclk, result));
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return result;
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}
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static bool mip_driver_stm32h_init(struct mip_if *ifp) {
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struct mip_driver_stm32h_data *d =
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(struct mip_driver_stm32h_data *) ifp->driver_data;
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s_ifp = ifp;
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// Init RX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_rxdesc[i][0] = (uint32_t) (uintptr_t) s_rxbuf[i]; // Point to data buffer
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s_rxdesc[i][3] = BIT(31) | BIT(30) | BIT(24); // OWN, IOC, BUF1V
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}
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// Init TX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_txdesc[i][0] = (uint32_t) (uintptr_t) s_txbuf[i]; // Buf pointer
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}
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ETH->DMAMR |= BIT(0); // Software reset
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while ((ETH->DMAMR & BIT(0)) != 0) (void) 0; // Wait until done
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// Set MDC clock divider. If user told us the value, use it. Otherwise, guess
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int cr = (d == NULL || d->mdc_cr < 0) ? guess_mdc_cr() : d->mdc_cr;
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ETH->MACMDIOAR = ((uint32_t) cr & 0xF) << 8;
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// NOTE(scaprile): We do not use timing facilities so the DMA engine does not
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// re-write buffer address
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ETH->DMAMR = 0 << 16; // use interrupt mode 0 (58.8.1) (reset value)
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ETH->DMASBMR |= BIT(12); // AAL NOTE(scaprile): is this actually needed
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ETH->MACIER = 0; // Do not enable additional irq sources (reset value)
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ETH->MACTFCR = BIT(7); // Disable zero-quanta pause
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// ETH->MACPFR = BIT(31); // Receive all
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eth_write_phy(PHY_ADDR, PHY_BCR, BIT(15)); // Reset PHY
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eth_write_phy(PHY_ADDR, PHY_BCR, BIT(12)); // Set autonegotiation
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ETH->DMACRDLAR =
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(uint32_t) (uintptr_t) s_rxdesc; // RX descriptors start address
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ETH->DMACRDRLR = ETH_DESC_CNT - 1; // ring length
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ETH->DMACRDTPR =
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(uint32_t) (uintptr_t) &s_rxdesc[ETH_DESC_CNT -
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1]; // last valid descriptor address
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ETH->DMACTDLAR =
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(uint32_t) (uintptr_t) s_txdesc; // TX descriptors start address
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ETH->DMACTDRLR = ETH_DESC_CNT - 1; // ring length
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ETH->DMACTDTPR =
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(uint32_t) (uintptr_t) s_txdesc; // first available descriptor address
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ETH->DMACCR = 0; // DSL = 0 (contiguous descriptor table) (reset value)
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ETH->DMACIER = BIT(6) | BIT(15); // RIE, NIE
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ETH->MACCR = BIT(0) | BIT(1) | BIT(13) | BIT(14) |
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BIT(15); // RE, TE, Duplex, Fast, Reserved
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ETH->MTLTQOMR |= BIT(1); // TSF
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ETH->MTLRQOMR |= BIT(5); // RSF
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ETH->DMACTCR |= BIT(0); // ST
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ETH->DMACRCR |= BIT(0); // SR
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// MAC address filtering
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ETH->MACA0HR = ((uint32_t) ifp->mac[5] << 8U) | ifp->mac[4];
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ETH->MACA0LR = (uint32_t) (ifp->mac[3] << 24) |
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((uint32_t) ifp->mac[2] << 16) |
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((uint32_t) ifp->mac[1] << 8) | ifp->mac[0];
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if (ifp->queue.len == 0) ifp->queue.len = 8192;
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return true;
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}
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static uint32_t s_txno;
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static size_t mip_driver_stm32h_tx(const void *buf, size_t len,
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struct mip_if *ifp) {
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if (len > sizeof(s_txbuf[s_txno])) {
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MG_ERROR(("Frame too big, %ld", (long) len));
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len = 0; // Frame is too big
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} else if ((s_txdesc[s_txno][3] & BIT(31))) {
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MG_ERROR(("No free descriptors: %u %08X %08X %08X", s_txno,
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s_txdesc[s_txno][3], ETH->DMACSR, ETH->DMACTCR));
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for (int i = 0; i < ETH_DESC_CNT; i++) MG_ERROR(("%08X", s_txdesc[i][3]));
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len = 0; // All descriptors are busy, fail
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} else {
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][2] = (uint32_t) len; // Set data len
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s_txdesc[s_txno][3] = BIT(28) | BIT(29); // FD, LD
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s_txdesc[s_txno][3] |= BIT(31); // Set OWN bit - let DMA take over
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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ETH->DMACSR |= BIT(2) | BIT(1); // Clear any prior TBU, TPS
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ETH->DMACTDTPR = (uint32_t) (uintptr_t) &s_txdesc[s_txno]; // and resume
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return len;
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(void) ifp;
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}
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static bool mip_driver_stm32h_up(struct mip_if *ifp) {
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uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR);
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bool up = bsr & BIT(2) ? 1 : 0;
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if ((ifp->state == MIP_STATE_DOWN) && up) { // link state just went up
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uint32_t scsr = eth_read_phy(PHY_ADDR, PHY_CSCR);
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uint32_t maccr = ETH->MACCR | BIT(14) | BIT(13); // 100M, Full-duplex
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if ((scsr & BIT(3)) == 0) maccr &= ~BIT(14); // 10M
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if ((scsr & BIT(4)) == 0) maccr &= ~BIT(13); // Half-duplex
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ETH->MACCR = maccr; // IRQ handler does not fiddle with this register
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MG_DEBUG(("Link is %uM %s-duplex", maccr & BIT(14) ? 100 : 10,
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maccr & BIT(13) ? "full" : "half"));
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}
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return up;
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}
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void ETH_IRQHandler(void);
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static uint32_t s_rxno;
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void ETH_IRQHandler(void) {
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qp_mark(QP_IRQTRIGGERED, 0);
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if (ETH->DMACSR & BIT(6)) { // Frame received, loop
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ETH->DMACSR = BIT(15) | BIT(6); // Clear flag
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for (uint32_t i = 0; i < 10; i++) { // read as they arrive but not forever
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if (s_rxdesc[s_rxno][3] & BIT(31)) break; // exit when done
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if (((s_rxdesc[s_rxno][3] & (BIT(28) | BIT(29))) ==
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(BIT(28) | BIT(29))) &&
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!(s_rxdesc[s_rxno][3] & BIT(15))) { // skip partial/errored frames
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uint32_t len = s_rxdesc[s_rxno][3] & (BIT(15) - 1);
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// MG_DEBUG(("%lx %lu %lx %08lx", s_rxno, len, s_rxdesc[s_rxno][3],
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// ETH->DMACSR));
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mip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp);
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}
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s_rxdesc[s_rxno][3] = BIT(31) | BIT(30) | BIT(24); // OWN, IOC, BUF1V
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if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
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}
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}
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ETH->DMACSR = BIT(7) | BIT(8); // Clear possible RBU RPS while processing
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ETH->DMACRDTPR =
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(uint32_t) (uintptr_t) &s_rxdesc[ETH_DESC_CNT - 1]; // and resume RX
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}
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struct mip_driver mip_driver_stm32h = {mip_driver_stm32h_init,
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mip_driver_stm32h_tx, mip_driver_rx,
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mip_driver_stm32h_up};
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#endif
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@@ -0,0 +1,16 @@
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#pragma once
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struct mip_driver_stm32h_data {
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// MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz
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// HCLK range DIVIDER mdc_cr VALUE
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// -------------------------------------
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// -1 <-- tell driver to guess the value
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// 60-100 MHz HCLK/42 0
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// 100-150 MHz HCLK/62 1
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// 20-35 MHz HCLK/16 2
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// 35-60 MHz HCLK/26 3
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// 150-250 MHz HCLK/102 4 <-- value for Nucleo-H* on max speed driven by HSI
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// 250-300 MHz HCLK/124 5 <-- value for Nucleo-H* on max speed driven by CSI
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// 110, 111 Reserved
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int mdc_cr; // Valid values: -1, 0, 1, 2, 3, 4, 5
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};
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@@ -60,6 +60,7 @@ size_t mip_driver_rx(void *buf, size_t len, struct mip_if *ifp);
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extern struct mip_driver mip_driver_stm32;
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extern struct mip_driver mip_driver_w5500;
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extern struct mip_driver mip_driver_tm4c;
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extern struct mip_driver mip_driver_stm32h;
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// Drivers that require SPI, can use this SPI abstraction
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struct mip_spi {
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@@ -69,6 +70,14 @@ struct mip_spi {
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uint8_t (*txn)(void *, uint8_t); // SPI transaction: write 1 byte, read reply
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};
|
||||
|
||||
#if MG_ENABLE_MIP
|
||||
#if !defined(MG_ENABLE_DRIVER_STM32H) && !defined(MG_ENABLE_DRIVER_TM4C)
|
||||
#define MG_ENABLE_DRIVER_STM32 1
|
||||
#else
|
||||
#define MG_ENABLE_DRIVER_STM32 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef MIP_QPROFILE
|
||||
enum {
|
||||
QP_IRQTRIGGERED = 0, // payload is number of interrupts so far
|
||||
|
||||
Reference in new issue
Block a user