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Refactor OTA API
This commit is contained in:
Sergio R. Caprile committed
1 parent
3319ce78d3
commit
9b99f62311
27 files changed
+1716
-2143
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+380
@@ -0,0 +1,380 @@
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#include "flash.h"
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#include "log.h"
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#include "ota.h"
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#if MG_OTA == MG_OTA_RT1020 || MG_OTA == MG_OTA_RT1060
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static bool mg_imxrt_write(void *, const void *, size_t);
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static bool mg_imxrt_swap(void);
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// TODO(): fill at init, support more devices in a dynamic way
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// TODO(): then, check alignment is <= 256, see Wizard's #251
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static struct mg_flash s_mg_flash_imxrt = {
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(void *) 0x60000000, // Start,
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8 * 1024 * 1024, // Size, 8mb
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4 * 1024, // Sector size, 4k
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256, // Align,
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mg_imxrt_write,
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mg_imxrt_swap,
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};
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struct mg_flexspi_lut_seq {
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uint8_t seqNum;
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uint8_t seqId;
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uint16_t reserved;
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};
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struct mg_flexspi_mem_config {
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uint32_t tag;
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uint32_t version;
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uint32_t reserved0;
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uint8_t readSampleClkSrc;
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uint8_t csHoldTime;
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uint8_t csSetupTime;
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uint8_t columnAddressWidth;
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uint8_t deviceModeCfgEnable;
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uint8_t deviceModeType;
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uint16_t waitTimeCfgCommands;
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struct mg_flexspi_lut_seq deviceModeSeq;
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uint32_t deviceModeArg;
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uint8_t configCmdEnable;
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uint8_t configModeType[3];
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struct mg_flexspi_lut_seq configCmdSeqs[3];
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uint32_t reserved1;
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uint32_t configCmdArgs[3];
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uint32_t reserved2;
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uint32_t controllerMiscOption;
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uint8_t deviceType;
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uint8_t sflashPadType;
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uint8_t serialClkFreq;
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uint8_t lutCustomSeqEnable;
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uint32_t reserved3[2];
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uint32_t sflashA1Size;
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uint32_t sflashA2Size;
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uint32_t sflashB1Size;
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uint32_t sflashB2Size;
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uint32_t csPadSettingOverride;
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uint32_t sclkPadSettingOverride;
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uint32_t dataPadSettingOverride;
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uint32_t dqsPadSettingOverride;
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uint32_t timeoutInMs;
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uint32_t commandInterval;
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uint16_t dataValidTime[2];
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uint16_t busyOffset;
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uint16_t busyBitPolarity;
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uint32_t lookupTable[64];
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struct mg_flexspi_lut_seq lutCustomSeq[12];
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uint32_t reserved4[4];
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};
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struct mg_flexspi_nor_config {
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struct mg_flexspi_mem_config memConfig;
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uint32_t pageSize;
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uint32_t sectorSize;
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uint8_t ipcmdSerialClkFreq;
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uint8_t isUniformBlockSize;
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uint8_t reserved0[2];
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uint8_t serialNorType;
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uint8_t needExitNoCmdMode;
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uint8_t halfClkForNonReadCmd;
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uint8_t needRestoreNoCmdMode;
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uint32_t blockSize;
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uint32_t reserve2[11];
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};
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/* FLEXSPI memory config block related defintions */
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#define MG_FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
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#define MG_FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
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#define MG_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
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(MG_FLEXSPI_LUT_OPERAND0(op0) | MG_FLEXSPI_LUT_NUM_PADS0(pad0) | \
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MG_FLEXSPI_LUT_OPCODE0(cmd0) | MG_FLEXSPI_LUT_OPERAND1(op1) | \
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MG_FLEXSPI_LUT_NUM_PADS1(pad1) | MG_FLEXSPI_LUT_OPCODE1(cmd1))
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#define MG_CMD_SDR 0x01
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#define MG_CMD_DDR 0x21
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#define MG_DUMMY_SDR 0x0C
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#define MG_DUMMY_DDR 0x2C
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#define MG_RADDR_SDR 0x02
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#define MG_RADDR_DDR 0x22
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#define MG_READ_SDR 0x09
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#define MG_READ_DDR 0x29
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#define MG_WRITE_SDR 0x08
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#define MG_WRITE_DDR 0x28
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#define MG_STOP 0
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#define MG_FLEXSPI_1PAD 0
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#define MG_FLEXSPI_2PAD 1
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#define MG_FLEXSPI_4PAD 2
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#define MG_FLEXSPI_8PAD 3
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#define MG_FLEXSPI_QSPI_LUT \
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{ \
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[0] = MG_FLEXSPI_LUT_SEQ(MG_CMD_SDR, MG_FLEXSPI_1PAD, 0xEB, MG_RADDR_SDR, \
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MG_FLEXSPI_4PAD, 0x18), \
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[1] = MG_FLEXSPI_LUT_SEQ(MG_DUMMY_SDR, MG_FLEXSPI_4PAD, 0x06, MG_READ_SDR, \
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MG_FLEXSPI_4PAD, 0x04), \
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[4 * 1 + 0] = MG_FLEXSPI_LUT_SEQ(MG_CMD_SDR, MG_FLEXSPI_1PAD, 0x05, \
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MG_READ_SDR, MG_FLEXSPI_1PAD, 0x04), \
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[4 * 3 + 0] = MG_FLEXSPI_LUT_SEQ(MG_CMD_SDR, MG_FLEXSPI_1PAD, 0x06, \
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MG_STOP, MG_FLEXSPI_1PAD, 0x0), \
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[4 * 5 + 0] = MG_FLEXSPI_LUT_SEQ(MG_CMD_SDR, MG_FLEXSPI_1PAD, 0x20, \
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MG_RADDR_SDR, MG_FLEXSPI_1PAD, 0x18), \
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[4 * 8 + 0] = MG_FLEXSPI_LUT_SEQ(MG_CMD_SDR, MG_FLEXSPI_1PAD, 0xD8, \
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MG_RADDR_SDR, MG_FLEXSPI_1PAD, 0x18), \
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[4 * 9 + 0] = MG_FLEXSPI_LUT_SEQ(MG_CMD_SDR, MG_FLEXSPI_1PAD, 0x02, \
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MG_RADDR_SDR, MG_FLEXSPI_1PAD, 0x18), \
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[4 * 9 + 1] = MG_FLEXSPI_LUT_SEQ(MG_WRITE_SDR, MG_FLEXSPI_1PAD, 0x04, \
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MG_STOP, MG_FLEXSPI_1PAD, 0x0), \
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[4 * 11 + 0] = MG_FLEXSPI_LUT_SEQ(MG_CMD_SDR, MG_FLEXSPI_1PAD, 0x60, \
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MG_STOP, MG_FLEXSPI_1PAD, 0x0), \
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}
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#define MG_FLEXSPI_LUT_OPERAND0(x) (((uint32_t) (((uint32_t) (x)))) & 0xFFU)
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#define MG_FLEXSPI_LUT_NUM_PADS0(x) \
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(((uint32_t) (((uint32_t) (x)) << 8U)) & 0x300U)
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#define MG_FLEXSPI_LUT_OPCODE0(x) \
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(((uint32_t) (((uint32_t) (x)) << 10U)) & 0xFC00U)
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#define MG_FLEXSPI_LUT_OPERAND1(x) \
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(((uint32_t) (((uint32_t) (x)) << 16U)) & 0xFF0000U)
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#define MG_FLEXSPI_LUT_NUM_PADS1(x) \
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(((uint32_t) (((uint32_t) (x)) << 24U)) & 0x3000000U)
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#define MG_FLEXSPI_LUT_OPCODE1(x) \
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(((uint32_t) (((uint32_t) (x)) << 26U)) & 0xFC000000U)
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#define FLEXSPI_NOR_INSTANCE 0
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#if MG_OTA == MG_OTA_RT1020
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struct mg_flexspi_nor_driver_interface {
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uint32_t version;
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int (*init)(uint32_t instance, struct mg_flexspi_nor_config *config);
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int (*program)(uint32_t instance, struct mg_flexspi_nor_config *config,
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uint32_t dst_addr, const uint32_t *src);
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uint32_t reserved;
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int (*erase)(uint32_t instance, struct mg_flexspi_nor_config *config,
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uint32_t start, uint32_t lengthInBytes);
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uint32_t reserved2;
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int (*update_lut)(uint32_t instance, uint32_t seqIndex,
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const uint32_t *lutBase, uint32_t seqNumber);
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int (*xfer)(uint32_t instance, char *xfer);
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void (*clear_cache)(uint32_t instance);
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};
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#elif MG_OTA == MG_OTA_RT1060
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struct mg_flexspi_nor_driver_interface {
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uint32_t version;
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int (*init)(uint32_t instance, struct mg_flexspi_nor_config *config);
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int (*program)(uint32_t instance, struct mg_flexspi_nor_config *config,
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uint32_t dst_addr, const uint32_t *src);
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int (*erase_all)(uint32_t instance, struct mg_flexspi_nor_config *config);
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int (*erase)(uint32_t instance, struct mg_flexspi_nor_config *config,
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uint32_t start, uint32_t lengthInBytes);
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int (*read)(uint32_t instance, struct mg_flexspi_nor_config *config,
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uint32_t *dst, uint32_t addr, uint32_t lengthInBytes);
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void (*clear_cache)(uint32_t instance);
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int (*xfer)(uint32_t instance, char *xfer);
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int (*update_lut)(uint32_t instance, uint32_t seqIndex,
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const uint32_t *lutBase, uint32_t seqNumber);
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int (*get_config)(uint32_t instance, struct mg_flexspi_nor_config *config,
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uint32_t *option);
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};
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#endif
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#define flexspi_nor \
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(*((struct mg_flexspi_nor_driver_interface **) (*(uint32_t *) 0x0020001c + \
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16)))
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static bool s_flash_irq_disabled;
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MG_IRAM static bool flash_page_start(volatile uint32_t *dst) {
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char *base = (char *) s_mg_flash_imxrt.start, *end = base + s_mg_flash_imxrt.size;
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volatile char *p = (char *) dst;
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return p >= base && p < end && ((p - base) % s_mg_flash_imxrt.secsz) == 0;
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}
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// Note: the get_config function below works both for RT1020 and 1060
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#if MG_OTA == MG_OTA_RT1020
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MG_IRAM static int flexspi_nor_get_config(
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struct mg_flexspi_nor_config *config) {
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struct mg_flexspi_nor_config default_config = {
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.memConfig = {.tag = MG_FLEXSPI_CFG_BLK_TAG,
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.version = MG_FLEXSPI_CFG_BLK_VERSION,
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.readSampleClkSrc = 1, // ReadSampleClk_LoopbackFromDqsPad
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.csHoldTime = 3,
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.csSetupTime = 3,
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.controllerMiscOption = MG_BIT(4),
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.deviceType = 1, // serial NOR
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.sflashPadType = 4,
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.serialClkFreq = 7, // 133MHz
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.sflashA1Size = 8 * 1024 * 1024,
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.lookupTable = MG_FLEXSPI_QSPI_LUT},
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.pageSize = 256,
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.sectorSize = 4 * 1024,
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.ipcmdSerialClkFreq = 1,
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.blockSize = 64 * 1024,
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.isUniformBlockSize = false};
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*config = default_config;
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return 0;
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}
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#else
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MG_IRAM static int flexspi_nor_get_config(
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struct mg_flexspi_nor_config *config) {
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uint32_t options[] = {0xc0000000, 0x00};
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MG_ARM_DISABLE_IRQ();
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uint32_t status =
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flexspi_nor->get_config(FLEXSPI_NOR_INSTANCE, config, options);
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if (!s_flash_irq_disabled) {
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MG_ARM_ENABLE_IRQ();
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}
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if (status) {
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MG_ERROR(("Failed to extract flash configuration: status %u", status));
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}
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return status;
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}
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#endif
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MG_IRAM static bool flash_erase(struct mg_flexspi_nor_config *config,
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void *addr) {
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if (flash_page_start(addr) == false) {
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MG_ERROR(("%p is not on a sector boundary", addr));
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return false;
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}
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void *dst = (void *) ((char *) addr - (char *) s_mg_flash_imxrt.start);
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bool ok = (flexspi_nor->erase(FLEXSPI_NOR_INSTANCE, config, (uint32_t) dst,
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s_mg_flash_imxrt.secsz) == 0);
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MG_DEBUG(("Sector starting at %p erasure: %s", addr, ok ? "ok" : "fail"));
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return ok;
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}
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#if 0
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// standalone erase call
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MG_IRAM static bool mg_imxrt_erase(void *addr) {
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struct mg_flexspi_nor_config config;
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bool ret;
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// Interrupts must be disabled before calls to ROM API in RT1020 and 1060
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MG_ARM_DISABLE_IRQ();
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ret = (flexspi_nor_get_config(&config) == 0);
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if (ret) ret = flash_erase(&config, addr);
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MG_ARM_ENABLE_IRQ();
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return ret;
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}
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#endif
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MG_IRAM bool mg_imxrt_swap(void) {
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return true;
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}
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static inline void spin(volatile uint32_t count) {
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while (count--) (void) 0;
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}
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static inline void flash_wait(void) {
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while ((*((volatile uint32_t *) (0x402A8000 + 0xE0)) & MG_BIT(1)) == 0)
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spin(1);
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}
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MG_IRAM static bool mg_imxrt_write(void *addr, const void *buf, size_t len) {
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struct mg_flexspi_nor_config config;
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bool ok = false;
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// Interrupts must be disabled before calls to ROM API in RT1020 and 1060
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MG_ARM_DISABLE_IRQ();
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if (flexspi_nor_get_config(&config) != 0) goto fwxit;
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if ((len % s_mg_flash_imxrt.align) != 0) {
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MG_ERROR(("%lu is not aligned to %lu", len, s_mg_flash_imxrt.align));
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goto fwxit;
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}
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if ((char *) addr < (char *) s_mg_flash_imxrt.start) {
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MG_ERROR(("Invalid flash write address: %p", addr));
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goto fwxit;
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}
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uint32_t *dst = (uint32_t *) addr;
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uint32_t *src = (uint32_t *) buf;
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uint32_t *end = (uint32_t *) ((char *) buf + len);
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ok = true;
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while (ok && src < end) {
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if (flash_page_start(dst) && flash_erase(&config, dst) == false) {
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ok = false;
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break;
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}
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uint32_t status;
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uint32_t dst_ofs = (uint32_t) dst - (uint32_t) s_mg_flash_imxrt.start;
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if ((char *) buf >= (char *) s_mg_flash_imxrt.start) {
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// If we copy from FLASH to FLASH, then we first need to copy the source
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// to RAM
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size_t tmp_buf_size = s_mg_flash_imxrt.align / sizeof(uint32_t);
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uint32_t tmp[tmp_buf_size];
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for (size_t i = 0; i < tmp_buf_size; i++) {
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flash_wait();
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tmp[i] = src[i];
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}
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status = flexspi_nor->program(FLEXSPI_NOR_INSTANCE, &config,
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(uint32_t) dst_ofs, tmp);
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} else {
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status = flexspi_nor->program(FLEXSPI_NOR_INSTANCE, &config,
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(uint32_t) dst_ofs, src);
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}
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src = (uint32_t *) ((char *) src + s_mg_flash_imxrt.align);
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dst = (uint32_t *) ((char *) dst + s_mg_flash_imxrt.align);
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if (status != 0) {
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ok = false;
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}
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}
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MG_DEBUG(("Flash write %lu bytes @ %p: %s.", len, dst, ok ? "ok" : "fail"));
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fwxit:
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if (!s_flash_irq_disabled) MG_ARM_ENABLE_IRQ();
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return ok;
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}
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// just overwrite instead of swap
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MG_IRAM static void single_bank_swap(char *p1, char *p2, size_t s, size_t ss) {
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// no stdlib calls here
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for (size_t ofs = 0; ofs < s; ofs += ss) {
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mg_imxrt_write(p1 + ofs, p2 + ofs, ss);
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}
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*(volatile unsigned long *) 0xe000ed0c = 0x5fa0004;
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}
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bool mg_ota_begin(size_t new_firmware_size) {
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return mg_ota_flash_begin(new_firmware_size, &s_mg_flash_imxrt);
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}
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bool mg_ota_write(const void *buf, size_t len) {
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return mg_ota_flash_write(buf, len, &s_mg_flash_imxrt);
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}
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bool mg_ota_end(void) {
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if (mg_ota_flash_end(&s_mg_flash_imxrt)) {
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if (0) { // is_dualbank()
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// TODO(): no devices so far
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*(volatile unsigned long *) 0xe000ed0c = 0x5fa0004;
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} else {
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// Swap partitions. Pray power does not go away
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char *tmpsector = malloc(s_mg_flash_imxrt.secsz);
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bool ramtmp = (tmpsector != NULL);
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if (!ramtmp) {
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MG_ERROR(("OOM"));
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return false;
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}
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MG_INFO(("Swapping partitions, size %u (%u sectors)",
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s_mg_flash_imxrt.size,
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s_mg_flash_imxrt.size / s_mg_flash_imxrt.secsz));
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MG_INFO(("Do NOT power off..."));
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mg_log_level = MG_LL_NONE;
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s_flash_irq_disabled = true;
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// Runs in RAM, will reset when finished
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single_bank_swap(
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(char *) s_mg_flash_imxrt.start,
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(char *) s_mg_flash_imxrt.start + s_mg_flash_imxrt.size / 2,
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s_mg_flash_imxrt.size / 2, s_mg_flash_imxrt.secsz);
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}
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}
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return false;
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}
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#endif
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