Kill ARP cache, kill qprofile

examples/stm32/nucleo-f429zi-freertos-mip/main.c

@@ -48,7 +48,8 @@ static void server(void *args) {
   // IP configuration. If IP/mask/GW are unset, DHCP is going to be used
   MG_INFO(("Initializing Ethernet driver"));
   ethernet_init();
-  struct mip_driver_stm32_data driver_data = {.mdc_cr = 4};  // See driver_stm32.h
+  struct mip_driver_stm32_data driver_data = {.mdc_cr =
+                                                  4};  // See driver_stm32.h
   struct mip_if mif = {
       .mac = {2, 0, 1, 2, 3, 5},
       .driver = &mip_driver_stm32,
@@ -74,9 +75,9 @@ static void blinker(void *args) {
 }
 
 int main(void) {
-  clock_init();               // Set clock to max of 180 MHz
+  clock_init();                        // Set clock to max of 180 MHz
   systick_init(SYS_FREQUENCY / 1000);  // Tick every 1 ms
-  uart_init(UART3, 115200);   // Initialise UART
+  uart_init(UART_DEBUG, 115200);       // Initialise UART
   xTaskCreate(blinker, "blinker", 128, ":)", configMAX_PRIORITIES - 1, NULL);
   xTaskCreate(server, "server", 2048, 0, configMAX_PRIORITIES - 1, NULL);
   vTaskStartScheduler();  // This blocks

examples/stm32/nucleo-f429zi-freertos-mip/mcu.h

@@ -101,6 +101,10 @@ static inline void gpio_toggle(uint16_t pin) {
 #define UART2 USART2
 #define UART3 USART3
 
+#ifndef UART_DEBUG
+#define UART_DEBUG USART3
+#endif
+
 static inline void uart_init(USART_TypeDef *uart, unsigned long baud) {
   // https://www.st.com/resource/en/datasheet/stm32f429zi.pdf
   uint8_t af = 7;           // Alternate function

examples/stm32/nucleo-f429zi-freertos-mip/syscalls.c

@@ -1,14 +1,11 @@
+#include <sys/stat.h>
+
 #include "mcu.h"
 
-int _write(int fd, char *ptr, int len) {
-  (void) fd, (void) ptr, (void) len;
-  if (fd == 1) uart_write_buf(UART3, ptr, (size_t) len);
-  return len;
-}
-
 int _fstat(int fd, struct stat *st) {
-  (void) fd, (void) st;
-  return -1;
+  if (fd < 0) return -1;
+  st->st_mode = S_IFCHR;
+  return 0;
 }
 
 void *_sbrk(int incr) {
@@ -21,6 +18,11 @@ void *_sbrk(int incr) {
   return prev_heap;
 }
 
+int _open(const char *path) {
+  (void) path;
+  return -1;
+}
+
 int _close(int fd) {
   (void) fd;
   return -1;
@@ -31,12 +33,53 @@ int _isatty(int fd) {
   return 1;
 }
 
+int _lseek(int fd, int ptr, int dir) {
+  (void) fd, (void) ptr, (void) dir;
+  return 0;
+}
+
+void _exit(int status) {
+  (void) status;
+  for (;;) asm volatile("BKPT #0");
+}
+
+void _kill(int pid, int sig) {
+  (void) pid, (void) sig;
+}
+
+int _getpid(void) {
+  return -1;
+}
+
+int _write(int fd, char *ptr, int len) {
+  (void) fd, (void) ptr, (void) len;
+  if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
+  return -1;
+}
+
 int _read(int fd, char *ptr, int len) {
   (void) fd, (void) ptr, (void) len;
   return -1;
 }
 
-int _lseek(int fd, int ptr, int dir) {
-  (void) fd, (void) ptr, (void) dir;
-  return 0;
+int _link(const char *a, const char *b) {
+  (void) a, (void) b;
+  return -1;
 }
+
+int _unlink(const char *a) {
+  (void) a;
+  return -1;
+}
+
+int _stat(const char *path, struct stat *st) {
+  (void) path, (void) st;
+  return -1;
+}
+
+int mkdir(const char *path, mode_t mode) {
+  (void) path, (void) mode;
+  return -1;
+}
+
+void _init(void) {}

examples/stm32/nucleo-f746zg-baremetal/Makefile

@@ -1,68 +1,39 @@
-# Download CMSIS header files from Github on demand
-CMSIS_CORE_VERSION ?= 5.9.0      # ARM Cortex-M definitions
-CMSIS_CORE_REPO ?= https://github.com/ARM-software/CMSIS_5
-CMSIS_DEVICE_VERSION ?= v1.2.8   # ST MCU peripheral definitions
-CMSIS_DEVICE_REPO ?= https://github.com/STMicroelectronics/cmsis_device_f7
-
 CFLAGS  = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
 CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
 CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
-CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_device_f7/Include
+CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_f7/Include
 CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16
 LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
 
 SOURCES = main.c syscalls.c sysinit.c
+SOURCES += cmsis_f7/Source/Templates/gcc/startup_stm32f746xx.s # ST startup file. Compiler-dependent!
 
-# Using ST-provided startup file. NOTE: this is compiler-dependant
-SOURCES += cmsis_device_f7/Source/Templates/gcc/startup_stm32f746xx.s
+# Mongoose-specific source code files and build options. See https://mongoose.ws/documentation/#build-options
+SOURCES += ../../../mongoose.c ../../device-dashboard/net.c ../../device-dashboard/packed_fs.c
+CFLAGS += -I../../.. -DMG_ARCH=MG_ARCH_NEWLIB -DMG_ENABLE_CUSTOM_MILLIS=1
+CFLAGS += -DMG_ENABLE_CUSTOM_RANDOM=1 -DMG_ENABLE_MIP=1 -DMG_ENABLE_PACKED_FS=1 $(CFLAGS_EXTRA)
 
-# Mongoose-specific build flags and source code files
-# Build options reference: https://mongoose.ws/documentation/#build-options
-SOURCES += ../../../mongoose.c
-SOURCES += ../../device-dashboard/net.c
-SOURCES += ../../device-dashboard/packed_fs.c
-
-CFLAGS += -I../../..
-CFLAGS += -DMG_ARCH=MG_ARCH_NEWLIB
-CFLAGS += -DMG_ENABLE_CUSTOM_MILLIS=1
-CFLAGS += -DMG_ENABLE_CUSTOM_RANDOM=1
-CFLAGS += -DMG_ENABLE_MIP=1
-CFLAGS += -DMG_ENABLE_PACKED_FS=1
-CFLAGS += $(CFLAGS_EXTRA)
-
-# Build flashable .bin file
 all build example: firmware.bin
 
-# .bin file is made from .elf file, by concatenating .text and .data sections
 firmware.bin: firmware.elf
 	arm-none-eabi-objcopy -O binary $< $@
 
-# .elf file is produced by compiling sources
-firmware.elf: $(SOURCES) hal.h link.ld cmsis_core cmsis_device_f7
+firmware.elf: cmsis_core cmsis_f7 $(SOURCES) hal.h link.ld 
 	arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
 
-# Flash .bin file to the target board via the built-in debugger
 flash: firmware.bin
 	st-flash --reset write $< 0x8000000
 
-# Download ST's CMSIS headers with peripheral definitions
-cmsis_device_f7/Source/Templates/gcc/startup_stm32f746xx.s: cmsis_device_f7
-cmsis_device_f7:
-	git clone --depth 1 -b $(CMSIS_DEVICE_VERSION) $(CMSIS_DEVICE_REPO) $@
+cmsis_f7:       # ARM CMSIS core headers
+	git clone --depth 1 -b v1.2.8 https://github.com/STMicroelectronics/cmsis_device_f7 $@
+cmsis_core:     # ST CMSIS headers for STM32F7 series
+	git clone --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
 
-# Download ARM's CMSIS headers with core Cortex-M definitions
-cmsis_core:
-	git clone --depth 1 -b $(CMSIS_CORE_VERSION) $(CMSIS_CORE_REPO) $@
-
-# Requires env variable VCON_API_KEY set
+# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
 DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/5
-
-# Upload firmware to a remote test device
 update: firmware.bin
 	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
 
-# Read serial port on a remote test device for 5 seconds, store in a
-# temporary file, and check the output for expected patterns
 test: CFLAGS_EXTRA += -DUART_DEBUG=USART1
 test: update
 	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt

examples/stm32/nucleo-f746zg-baremetal/main.c

@@ -4,7 +4,12 @@
 #include "hal.h"
 #include "mongoose.h"
 
-#define LED PIN('B', 7)       // On-board LED pin
+#define LED1 PIN('B', 0)   // On-board LED pin (green)
+#define LED2 PIN('B', 7)   // On-board LED pin (blue)
+#define LED3 PIN('B', 14)  // On-board LED pin (red)
+#define BTN1 PIN('C', 13)  // On-board user button
+
+#define LED LED2              // Use blue LED for blinking
 #define BLINK_PERIOD_MS 1000  // LED blinking period in millis
 
 static uint64_t s_ticks;      // Milliseconds since boot
@@ -29,7 +34,7 @@ static void timer_fn(void *arg) {
   const char *names[] = {"down", "up", "ready"};  // network stats
   MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u",
            names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent,
-           ifp->ndropped, ifp->nerr));
+           ifp->ndrop, ifp->nerr));
 }
 
 static void ethernet_init(void) {

examples/stm32/nucleo-f746zg-freertos-mip/FreeRTOSConfig.h

@@ -1,6 +1,6 @@
 #pragma once
 
-#include "mcu.h"
+#include "hal.h"
 
 #define configUSE_PREEMPTION 1
 #define configCPU_CLOCK_HZ SYS_FREQUENCY

examples/stm32/nucleo-f746zg-freertos-mip/Makefile

@@ -1,34 +1,49 @@
-CFLAGS  ?=  -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion \
-            -Wformat-truncation -fno-common -Wconversion \
-            -g3 -Os -ffunction-sections -fdata-sections \
-            -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 \
-            -I. -I../../../ $(EXTRA_CFLAGS)
-LDFLAGS ?= -Tlink.ld -nostartfiles -nostdlib --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
-SOURCES = main.c boot.c syscalls.c ../../../mongoose.c
+CFLAGS  = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
+CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
+CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
+CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_f7/Include
+CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16
+LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
 
-FREERTOS_VERSION ?= V10.5.0
-FREERTOS_REPO ?= https://github.com/FreeRTOS/FreeRTOS-Kernel 
+SOURCES = main.c syscalls.c sysinit.c
+SOURCES += cmsis_f7/Source/Templates/gcc/startup_stm32f746xx.s # ST startup file. Compiler-dependent!
 
-build example: firmware.bin
+# FreeRTOS
+SOURCES += FreeRTOS-Kernel/portable/MemMang/heap_4.c
+SOURCES += FreeRTOS-Kernel/portable/GCC/ARM_CM7/r0p1/port.c
+CFLAGS += -IFreeRTOS-Kernel/include 
+CFLAGS += -IFreeRTOS-Kernel/portable/GCC/ARM_CM7/r0p1 -Wno-conversion
+
+SOURCES += ../../../mongoose.c # Mongoose options are defined in mongoose_custom.h
+CFLAGS += -I../../.. $(CFLAGS_EXTRA)
+
+all build example: firmware.bin
 
-firmware.elf: FreeRTOS-Kernel $(SOURCES) 
-	arm-none-eabi-gcc -o $@ $(SOURCES) $(CFLAGS) \
-	  -IFreeRTOS-Kernel/include \
-	  -IFreeRTOS-Kernel/portable/GCC/ARM_CM7/r0p1 \
-	  -Wno-conversion \
-	  $(wildcard FreeRTOS-Kernel/*.c) \
-	  FreeRTOS-Kernel/portable/MemMang/heap_4.c \
-	  FreeRTOS-Kernel/portable/GCC/ARM_CM7/r0p1/port.c \
-	  $(LDFLAGS)
-	
 firmware.bin: firmware.elf
 	arm-none-eabi-objcopy -O binary $< $@
 
-flash: firmware.bin
-	st-flash --reset write firmware.bin 0x8000000
+firmware.elf: FreeRTOS-Kernel cmsis_core cmsis_f7 $(SOURCES) hal.h link.ld 
+	arm-none-eabi-gcc $(SOURCES) $(wildcard FreeRTOS-Kernel/*.c) $(CFLAGS) $(LDFLAGS) -o $@
 
-FreeRTOS-Kernel:
-	git clone --depth 1 -b $(FREERTOS_VERSION) $(FREERTOS_REPO) $@
+flash: firmware.bin
+	st-flash --reset write $< 0x8000000
+
+cmsis_f7:  # ARM CMSIS core headers
+	git clone --depth 1 -b v1.2.8 https://github.com/STMicroelectronics/cmsis_device_f7 $@
+cmsis_core:  # ST CMSIS headers for STM32F7 series
+	git clone --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
+FreeRTOS-Kernel:  # FreeRTOS sources
+	git clone --depth 1 -b V10.5.0 https://github.com/FreeRTOS/FreeRTOS-Kernel $@
+
+# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
+DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/5
+update: firmware.bin
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
+
+test: CFLAGS_EXTRA += -DUART_DEBUG=USART1
+test: update
+	curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
+	grep 'READY, IP:' /tmp/output.txt       # Check for network init
 
 clean:
-	rm -rf firmware.* FreeRTOS-Kernel
+	@rm -rf firmware.* *.su cmsis_core cmsis_f7 FreeRTOS-Kernel

examples/stm32/nucleo-f746zg-freertos-mip/boot.c

@@ -1,169 +0,0 @@
-// Copyright (c) 2022 Cesanta Software Limited
-// All rights reserved
-
-// Startup code
-__attribute__((naked, noreturn)) void _reset(void) {
-  // Initialise memory
-  extern long _sbss, _ebss, _sdata, _edata, _sidata;
-  for (long *src = &_sbss; src < &_ebss; src++) *src = 0;
-  for (long *src = &_sdata, *dst = &_sidata; src < &_edata;) *src++ = *dst++;
-
-  // Call main()
-  extern void main(void);
-  main();
-  for (;;) (void) 0;
-}
-
-void __attribute__((weak)) DefaultIRQHandler(void) {
-  for (;;) (void) 0;
-}
-
-#define WEAK_ALIAS __attribute__((weak, alias("DefaultIRQHandler")))
-
-WEAK_ALIAS void NMI_Handler(void);
-WEAK_ALIAS void HardFault_Handler(void);
-WEAK_ALIAS void MemManage_Handler(void);
-WEAK_ALIAS void BusFault_Handler(void);
-WEAK_ALIAS void UsageFault_Handler(void);
-WEAK_ALIAS void SVC_Handler(void);
-WEAK_ALIAS void DebugMon_Handler(void);
-WEAK_ALIAS void PendSV_Handler(void);
-WEAK_ALIAS void SysTick_Handler(void);
-
-WEAK_ALIAS void WWDG_IRQHandler(void);
-WEAK_ALIAS void PVD_IRQHandler(void);
-WEAK_ALIAS void TAMP_STAMP_IRQHandler(void);
-WEAK_ALIAS void RTC_WKUP_IRQHandler(void);
-WEAK_ALIAS void FLASH_IRQHandler(void);
-WEAK_ALIAS void RCC_IRQHandler(void);
-WEAK_ALIAS void EXTI0_IRQHandler(void);
-WEAK_ALIAS void EXTI1_IRQHandler(void);
-WEAK_ALIAS void EXTI2_IRQHandler(void);
-WEAK_ALIAS void EXTI3_IRQHandler(void);
-WEAK_ALIAS void EXTI4_IRQHandler(void);
-WEAK_ALIAS void EXTI9_5_IRQHandler(void);
-WEAK_ALIAS void EXTI15_10_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream0_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream1_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream2_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream3_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream4_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream5_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream6_IRQHandler(void);
-WEAK_ALIAS void ADC_IRQHandler(void);
-WEAK_ALIAS void CAN1_TX_IRQHandler(void);
-WEAK_ALIAS void CAN1_RX0_IRQHandler(void);
-WEAK_ALIAS void CAN1_RX1_IRQHandler(void);
-WEAK_ALIAS void CAN1_SCE_IRQHandler(void);
-WEAK_ALIAS void TIM1_BRK_TIM9_IRQHandler(void);
-WEAK_ALIAS void TIM1_UP_TIM10_IRQHandler(void);
-WEAK_ALIAS void TIM1_TRG_COM_TIM11_IRQHandler(void);
-WEAK_ALIAS void TIM1_CC_IRQHandler(void);
-WEAK_ALIAS void TIM2_IRQHandler(void);
-WEAK_ALIAS void TIM3_IRQHandler(void);
-WEAK_ALIAS void TIM4_IRQHandler(void);
-WEAK_ALIAS void I2C1_EV_IRQHandler(void);
-WEAK_ALIAS void I2C1_ER_IRQHandler(void);
-WEAK_ALIAS void I2C2_EV_IRQHandler(void);
-WEAK_ALIAS void I2C2_ER_IRQHandler(void);
-WEAK_ALIAS void SPI1_IRQHandler(void);
-WEAK_ALIAS void SPI2_IRQHandler(void);
-WEAK_ALIAS void USART1_IRQHandler(void);
-WEAK_ALIAS void USART2_IRQHandler(void);
-WEAK_ALIAS void USART3_IRQHandler(void);
-WEAK_ALIAS void RTC_Alarm_IRQHandler(void);
-WEAK_ALIAS void OTG_FS_WKUP_IRQHandler(void);
-WEAK_ALIAS void TIM8_BRK_TIM12_IRQHandler(void);
-WEAK_ALIAS void TIM8_UP_TIM13_IRQHandler(void);
-WEAK_ALIAS void TIM8_TRG_COM_TIM14_IRQHandler(void);
-WEAK_ALIAS void TIM8_CC_IRQHandler(void);
-WEAK_ALIAS void DMA1_Stream7_IRQHandler(void);
-WEAK_ALIAS void FMC_IRQHandler(void);
-WEAK_ALIAS void SDMMC1_IRQHandler(void);
-WEAK_ALIAS void TIM5_IRQHandler(void);
-WEAK_ALIAS void SPI3_IRQHandler(void);
-WEAK_ALIAS void UART4_IRQHandler(void);
-WEAK_ALIAS void UART5_IRQHandler(void);
-WEAK_ALIAS void TIM6_DAC_IRQHandler(void);
-WEAK_ALIAS void TIM7_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream0_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream1_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream2_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream3_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream4_IRQHandler(void);
-WEAK_ALIAS void ETH_IRQHandler(void);
-WEAK_ALIAS void ETH_WKUP_IRQHandler(void);
-WEAK_ALIAS void CAN2_TX_IRQHandler(void);
-WEAK_ALIAS void CAN2_RX0_IRQHandler(void);
-WEAK_ALIAS void CAN2_RX1_IRQHandler(void);
-WEAK_ALIAS void CAN2_SCE_IRQHandler(void);
-WEAK_ALIAS void OTG_FS_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream5_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream6_IRQHandler(void);
-WEAK_ALIAS void DMA2_Stream7_IRQHandler(void);
-WEAK_ALIAS void USART6_IRQHandler(void);
-WEAK_ALIAS void I2C3_EV_IRQHandler(void);
-WEAK_ALIAS void I2C3_ER_IRQHandler(void);
-WEAK_ALIAS void OTG_HS_EP1_OUT_IRQHandler(void);
-WEAK_ALIAS void OTG_HS_EP1_IN_IRQHandler(void);
-WEAK_ALIAS void OTG_HS_WKUP_IRQHandler(void);
-WEAK_ALIAS void OTG_HS_IRQHandler(void);
-WEAK_ALIAS void DCMI_IRQHandler(void);
-WEAK_ALIAS void RNG_IRQHandler(void);
-WEAK_ALIAS void FPU_IRQHandler(void);
-WEAK_ALIAS void UART7_IRQHandler(void);
-WEAK_ALIAS void UART8_IRQHandler(void);
-WEAK_ALIAS void SPI4_IRQHandler(void);
-WEAK_ALIAS void SPI5_IRQHandler(void);
-WEAK_ALIAS void SPI6_IRQHandler(void);
-WEAK_ALIAS void SAI1_IRQHandler(void);
-WEAK_ALIAS void LTDC_IRQHandler(void);
-WEAK_ALIAS void LTDC_ER_IRQHandler(void);
-WEAK_ALIAS void DMA2D_IRQHandler(void);
-WEAK_ALIAS void SAI2_IRQHandler(void);
-WEAK_ALIAS void QUADSPI_IRQHandler(void);
-WEAK_ALIAS void LPTIM1_IRQHandler(void);
-WEAK_ALIAS void CEC_IRQHandler(void);
-WEAK_ALIAS void I2C4_EV_IRQHandler(void);
-WEAK_ALIAS void I2C4_ER_IRQHandler(void);
-WEAK_ALIAS void SPDIF_RX_IRQHandler(void);
-
-// IRQ table
-extern void _estack();
-__attribute__((section(".vectors"))) void (*tab[16 + 98])(void) = {
-    // Cortex interrupts
-    _estack, _reset, NMI_Handler, HardFault_Handler, MemManage_Handler,
-    BusFault_Handler, UsageFault_Handler, 0, 0, 0, 0, SVC_Handler,
-    DebugMon_Handler, 0, PendSV_Handler, SysTick_Handler,
-
-    // Interrupts from peripherals
-    WWDG_IRQHandler, PVD_IRQHandler, TAMP_STAMP_IRQHandler, RTC_WKUP_IRQHandler,
-    FLASH_IRQHandler, RCC_IRQHandler, EXTI0_IRQHandler, EXTI1_IRQHandler,
-    EXTI2_IRQHandler, EXTI3_IRQHandler, EXTI4_IRQHandler,
-    DMA1_Stream0_IRQHandler, DMA1_Stream1_IRQHandler, DMA1_Stream2_IRQHandler,
-    DMA1_Stream3_IRQHandler, DMA1_Stream4_IRQHandler, DMA1_Stream5_IRQHandler,
-    DMA1_Stream6_IRQHandler, ADC_IRQHandler, CAN1_TX_IRQHandler,
-    CAN1_RX0_IRQHandler, CAN1_RX1_IRQHandler, CAN1_SCE_IRQHandler,
-    EXTI9_5_IRQHandler, TIM1_BRK_TIM9_IRQHandler, TIM1_UP_TIM10_IRQHandler,
-    TIM1_TRG_COM_TIM11_IRQHandler, TIM1_CC_IRQHandler, TIM2_IRQHandler,
-    TIM3_IRQHandler, TIM4_IRQHandler, I2C1_EV_IRQHandler, I2C1_ER_IRQHandler,
-    I2C2_EV_IRQHandler, I2C2_ER_IRQHandler, SPI1_IRQHandler, SPI2_IRQHandler,
-    USART1_IRQHandler, USART2_IRQHandler, USART3_IRQHandler,
-    EXTI15_10_IRQHandler, RTC_Alarm_IRQHandler, OTG_FS_WKUP_IRQHandler,
-    TIM8_BRK_TIM12_IRQHandler, TIM8_UP_TIM13_IRQHandler,
-    TIM8_TRG_COM_TIM14_IRQHandler, TIM8_CC_IRQHandler, DMA1_Stream7_IRQHandler,
-    FMC_IRQHandler, SDMMC1_IRQHandler, TIM5_IRQHandler, SPI3_IRQHandler,
-    UART4_IRQHandler, UART5_IRQHandler, TIM6_DAC_IRQHandler, TIM7_IRQHandler,
-    DMA2_Stream0_IRQHandler, DMA2_Stream1_IRQHandler, DMA2_Stream2_IRQHandler,
-    DMA2_Stream3_IRQHandler, DMA2_Stream4_IRQHandler, ETH_IRQHandler,
-    ETH_WKUP_IRQHandler, CAN2_TX_IRQHandler, CAN2_RX0_IRQHandler,
-    CAN2_RX1_IRQHandler, CAN2_SCE_IRQHandler, OTG_FS_IRQHandler,
-    DMA2_Stream5_IRQHandler, DMA2_Stream6_IRQHandler, DMA2_Stream7_IRQHandler,
-    USART6_IRQHandler, I2C3_EV_IRQHandler, I2C3_ER_IRQHandler,
-    OTG_HS_EP1_OUT_IRQHandler, OTG_HS_EP1_IN_IRQHandler, OTG_HS_WKUP_IRQHandler,
-    OTG_HS_IRQHandler, DCMI_IRQHandler, 0, RNG_IRQHandler, FPU_IRQHandler,
-    UART7_IRQHandler, UART8_IRQHandler, SPI4_IRQHandler, SPI5_IRQHandler,
-    SPI6_IRQHandler, SAI1_IRQHandler, LTDC_IRQHandler, LTDC_ER_IRQHandler,
-    DMA2D_IRQHandler, SAI2_IRQHandler, QUADSPI_IRQHandler, LPTIM1_IRQHandler,
-    CEC_IRQHandler, I2C4_EV_IRQHandler, I2C4_ER_IRQHandler,
-    SPDIF_RX_IRQHandler};

examples/stm32/nucleo-f746zg-freertos-mip/hal.h

@@ -0,0 +1,134 @@
+// Copyright (c) 2022 Cesanta Software Limited
+// All rights reserved
+// https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
+
+#pragma once
+
+#include <stm32f746xx.h>
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#define BIT(x) (1UL << (x))
+#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
+#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
+#define PINNO(pin) (pin & 255)
+#define PINBANK(pin) (pin >> 8)
+
+/* System clock
+5.3.3: APB1 clock <= 54MHz; APB2 clock <= 108MHz
+3.3.2, Table 5: configure flash latency (WS) in accordance to clock freq
+38.4: The AHB clock frequency must be at least 25 MHz when the Ethernet
+controller is used */
+enum { APB1_PRE = 5 /* AHB clock / 4 */, APB2_PRE = 4 /* AHB clock / 2 */ };
+enum { PLL_HSI = 16, PLL_M = 8, PLL_N = 216, PLL_P = 2 };  // Run at 216 Mhz
+#define FLASH_LATENCY 7
+#define SYS_FREQUENCY ((PLL_HSI * PLL_N / PLL_M / PLL_P) * 1000000)
+#define APB2_FREQUENCY (SYS_FREQUENCY / (BIT(APB2_PRE - 3)))
+#define APB1_FREQUENCY (SYS_FREQUENCY / (BIT(APB1_PRE - 3)))
+
+static inline void spin(volatile uint32_t count) {
+  while (count--) (void) 0;
+}
+
+enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
+enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
+enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
+enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
+#define GPIO(N) ((GPIO_TypeDef *) (0x40020000 + 0x400 * (N)))
+
+static GPIO_TypeDef *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
+static inline void gpio_toggle(uint16_t pin) {
+  GPIO_TypeDef *gpio = gpio_bank(pin);
+  uint32_t mask = BIT(PINNO(pin));
+  gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
+}
+static inline int gpio_read(uint16_t pin) {
+  return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
+}
+static inline void gpio_write(uint16_t pin, bool val) {
+  GPIO_TypeDef *gpio = gpio_bank(pin);
+  gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
+}
+static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
+                             uint8_t speed, uint8_t pull, uint8_t af) {
+  GPIO_TypeDef *gpio = gpio_bank(pin);
+  uint8_t n = (uint8_t) (PINNO(pin));
+  RCC->AHB1ENR |= BIT(PINBANK(pin));  // Enable GPIO clock
+  SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
+  SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
+  SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
+  SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
+          ((uint32_t) af) << ((n & 7) * 4));
+  SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
+}
+static inline void gpio_input(uint16_t pin) {
+  gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
+            GPIO_PULL_NONE, 0);
+}
+static inline void gpio_output(uint16_t pin) {
+  gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
+            GPIO_PULL_NONE, 0);
+}
+
+static inline void irq_exti_attach(uint16_t pin) {
+  uint8_t bank = (uint8_t) (PINBANK(pin)), n = (uint8_t) (PINNO(pin));
+  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;  // Enable SYSCFG
+  SYSCFG->EXTICR[n / 4] &= ~(15UL << ((n % 4) * 4));
+  SYSCFG->EXTICR[n / 4] |= (uint32_t) (bank << ((n % 4) * 4));
+  EXTI->IMR |= BIT(n);
+  EXTI->RTSR |= BIT(n);
+  EXTI->FTSR |= BIT(n);
+  int irqvec = n < 5 ? 6 + n : n < 10 ? 23 : 40;  // IRQ vector index, 10.1.2
+  NVIC_SetPriority(irqvec, 3);
+  NVIC_EnableIRQ(irqvec);
+}
+
+#ifndef UART_DEBUG
+#define UART_DEBUG USART3
+#endif
+
+static inline void uart_init(USART_TypeDef *uart, unsigned long baud) {
+  // https://www.st.com/resource/en/datasheet/stm32f746zg.pdf
+  uint8_t af = 7;           // Alternate function
+  uint16_t rx = 0, tx = 0;  // pins
+  uint32_t freq = 0;        // Bus frequency. UART1 is on APB2, rest on APB1
+
+  if (uart == USART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
+  if (uart == USART2) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(17);
+  if (uart == USART3) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(18);
+
+  if (uart == USART1) tx = PIN('A', 9), rx = PIN('A', 10);
+  if (uart == USART2) tx = PIN('A', 2), rx = PIN('A', 3);
+  if (uart == USART3) tx = PIN('D', 8), rx = PIN('D', 9);
+
+  gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
+  gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
+  uart->CR1 = 0;                          // Disable this UART
+  uart->BRR = freq / baud;                // Set baud rate
+  uart->CR1 |= BIT(0) | BIT(2) | BIT(3);  // Set UE, RE, TE
+}
+static inline void uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
+  uart->TDR = byte;
+  while ((uart->ISR & BIT(7)) == 0) spin(1);
+}
+static inline void uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
+  while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
+}
+static inline int uart_read_ready(USART_TypeDef *uart) {
+  return uart->ISR & BIT(5);  // If RXNE bit is set, data is ready
+}
+static inline uint8_t uart_read_byte(USART_TypeDef *uart) {
+  return (uint8_t) (uart->RDR & 255);
+}
+
+static inline void rng_init(void) {
+  RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;
+  RNG->CR |= RNG_CR_RNGEN;
+}
+static inline uint32_t rng_read(void) {
+  while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0;
+  return RNG->DR;
+}

examples/stm32/nucleo-f746zg-freertos-mip/link.ld

@@ -1,14 +1,14 @@
-ENTRY(_reset);
+ENTRY(Reset_Handler);
 MEMORY {
-  flash(rx)  : ORIGIN = 0x08000000, LENGTH = 1024k
+  flash(rx) : ORIGIN = 0x08000000, LENGTH = 1024k
   sram(rwx) : ORIGIN = 0x20000000, LENGTH = 320k
 }
 _estack     = ORIGIN(sram) + LENGTH(sram);    /* stack points to end of SRAM */
 
 SECTIONS {
-  .vectors  : { KEEP(*(.vectors)) }   > flash
-  .text     : { *(.text*) }           > flash
-  .rodata   : { *(.rodata*) }         > flash
+  .vectors  : { KEEP(*(.isr_vector)) }  > flash
+  .text     : { *(.text* .text.*) }     > flash
+  .rodata   : { *(.rodata*) }           > flash
 
   .data : {
     _sdata = .;   /* for init_ram() */

examples/stm32/nucleo-f746zg-freertos-mip/main.c

@@ -1,9 +1,24 @@
 // Copyright (c) 2022 Cesanta Software Limited
 // All rights reserved
 
-#include "mcu.h"
+#include "hal.h"
 #include "mongoose.h"
 
+#define LED1 PIN('B', 0)   // On-board LED pin (green)
+#define LED2 PIN('B', 7)   // On-board LED pin (blue)
+#define LED3 PIN('B', 14)  // On-board LED pin (red)
+#define BTN1 PIN('C', 13)  // On-board user button
+
+#define LED LED2              // Use blue LED for blinking
+#define BLINK_PERIOD_MS 1000  // LED blinking period in millis
+
+void mg_random(void *buf, size_t len) {  // Use on-board RNG
+  for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
+    uint32_t r = rng_read();
+    memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
+  }
+}
+
 // HTTP server event handler function
 static void fn(struct mg_connection *c, int ev, void *ev_data, void *fn_data) {
   if (ev == MG_EV_HTTP_MSG) {
@@ -27,14 +42,20 @@ static void ethernet_init(void) {
                      PIN('C', 5),  PIN('G', 11), PIN('G', 13)};
   for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
     gpio_init(pins[i], GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_INSANE,
-              GPIO_PULL_NONE, 11);
+              GPIO_PULL_NONE, 11);  // 11 is the Ethernet function
   }
-  nvic_enable_irq(61);                          // Setup Ethernet IRQ handler
-  RCC->APB2ENR |= BIT(14);                      // Enable SYSCFG
-  SYSCFG->PMC |= BIT(23);                       // Use RMII. Goes first!
-  RCC->AHB1ENR |= BIT(25) | BIT(26) | BIT(27);  // Enable Ethernet clocks
-  RCC->AHB1RSTR |= BIT(25);                     // ETHMAC force reset
-  RCC->AHB1RSTR &= ~BIT(25);                    // ETHMAC release reset
+  NVIC_EnableIRQ(ETH_IRQn);                // Setup Ethernet IRQ handler
+  SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;  // Use RMII. Goes first!
+  RCC->AHB1ENR |=
+      RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | RCC_AHB1ENR_ETHMACRXEN;
+}
+
+static void timer_fn(void *arg) {
+  struct mip_if *ifp = arg;                       // And show
+  const char *names[] = {"down", "up", "ready"};  // network stats
+  MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u",
+           names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent,
+           ifp->ndrop, ifp->nerr));
 }
 
 static void server(void *args) {
@@ -47,37 +68,36 @@ static void server(void *args) {
   // IP configuration. If IP/mask/GW are unset, DHCP is going to be used
   MG_INFO(("Initializing Ethernet driver"));
   ethernet_init();
-  struct mip_driver_stm32_data driver_data = {.mdc_cr = 4};  // See driver_stm32.h
-  struct mip_if mif = {
-      .mac = {2, 0, 1, 2, 3, 5},
-      .driver = &mip_driver_stm32,
-      .driver_data = &driver_data,
-  };
+  struct mip_driver_stm32_data driver_data = {.mdc_cr = 4};
+  struct mip_if mif = {.driver = &mip_driver_stm32,
+                       .driver_data = &driver_data};
   mip_init(&mgr, &mif);
 
   MG_INFO(("Starting Mongoose v%s", MG_VERSION));    // Tell the world
   mg_http_listen(&mgr, "http://0.0.0.0", fn, &mgr);  // Web listener
-  while (args == NULL) mg_mgr_poll(&mgr, 1000);      // Infinite event loop
-  mg_mgr_free(&mgr);                                 // Unreachable
+  mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
+
+  for (;;) mg_mgr_poll(&mgr, 1);  // Infinite event loop
+  (void) args;
 }
 
 static void blinker(void *args) {
-  uint16_t led = PIN('B', 7);
-  gpio_init(led, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
+  gpio_init(LED, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM,
             GPIO_PULL_NONE, 0);
   for (;;) {
-    gpio_toggle(led);
-    vTaskDelay(pdMS_TO_TICKS(750));
-    MG_INFO(("blink %s,  RAM: %u", (char *) args, xPortGetFreeHeapSize()));
+    gpio_toggle(LED);
+    vTaskDelay(pdMS_TO_TICKS(BLINK_PERIOD_MS));
   }
+  (void) args;
 }
 
 int main(void) {
-  clock_init();               // Set clock to max of 180 MHz
-  systick_init(SYS_FREQUENCY / 1000);  // Tick every 1 ms
-  uart_init(UART3, 115200);   // Initialise UART
+  uart_init(UART_DEBUG, 115200);  // Initialise UART
+
+  // Start tasks. NOTE: stack sizes are in 32-bit words
   xTaskCreate(blinker, "blinker", 128, ":)", configMAX_PRIORITIES - 1, NULL);
   xTaskCreate(server, "server", 2048, 0, configMAX_PRIORITIES - 1, NULL);
+
   vTaskStartScheduler();  // This blocks
   return 0;
 }

examples/stm32/nucleo-f746zg-freertos-mip/mcu.h

@@ -1,216 +0,0 @@
-// Copyright (c) 2022 Cesanta Software Limited
-// All rights reserved
-// https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf
-
-#pragma once
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string.h>
-
-#define BIT(x) (1UL << (x))
-#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
-#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
-#define PINNO(pin) (pin & 255)
-#define PINBANK(pin) (pin >> 8)
-
-/* System clock
-5.3.3: APB1 clock <= 54MHz; APB2 clock <= 108MHz
-3.3.2, Table 5: configure flash latency (WS) in accordance to clock freq
-38.4: The AHB clock frequency must be at least 25 MHz when the Ethernet controller is used */
-enum { APB1_PRE = 5 /* AHB clock / 4 */, APB2_PRE = 4 /* AHB clock / 2 */ };
-enum { PLL_HSI = 16, PLL_M = 8, PLL_N = 216, PLL_P = 2 };  // Run at 216 Mhz
-#define FLASH_LATENCY 7 
-#define SYS_FREQUENCY ((PLL_HSI * PLL_N / PLL_M / PLL_P) * 1000000)
-#define APB2_FREQUENCY (SYS_FREQUENCY / (BIT(APB2_PRE - 3)))
-#define APB1_FREQUENCY (SYS_FREQUENCY / (BIT(APB1_PRE - 3)))
-
-static inline void spin(volatile uint32_t count) {
-  while (count--) asm("nop");
-}
-
-struct rcc {
-  volatile uint32_t CR, PLLCFGR, CFGR, CIR, AHB1RSTR, AHB2RSTR, AHB3RSTR,
-      RESERVED0, APB1RSTR, APB2RSTR, RESERVED1[2], AHB1ENR, AHB2ENR, AHB3ENR,
-      RESERVED2, APB1ENR, APB2ENR, RESERVED3[2], AHB1LPENR, AHB2LPENR,
-      AHB3LPENR, RESERVED4, APB1LPENR, APB2LPENR, RESERVED5[2], BDCR, CSR,
-      RESERVED6[2], SSCGR, PLLI2SCFGR, PLLSAICFGR, DCKCFGR1, DCKCFGR2;
-};
-#define RCC ((struct rcc *) 0x40023800)
-
-struct pwr {
-  volatile uint32_t CR1, CSR1, CR2, CSR2;
-};
-#define PWR ((struct pwr *) 0x40007000)
-
-struct nvic {
-  volatile uint32_t ISER[8], RESERVED0[24], ICER[8], RSERVED1[24], ISPR[8],
-      RESERVED2[24], ICPR[8], RESERVED3[24], IABR[8], RESERVED4[56], IP[240],
-      RESERVED5[644], STIR;
-};
-#define NVIC ((struct nvic *) 0xe000e100)
-static inline void nvic_set_prio(int irq, uint32_t prio) {
-  NVIC->IP[irq] = prio << 4;
-}
-static inline void nvic_enable_irq(int irq) {
-  NVIC->ISER[irq >> 5] = (uint32_t) (1 << (irq & 31));
-}
-
-struct systick {
-  volatile uint32_t CTRL, LOAD, VAL, CALIB;
-};
-#define SYSTICK ((struct systick *) 0xe000e010)  // 2.2.2
-static inline void systick_init(uint32_t ticks) {
-  if ((ticks - 1) > 0xffffff) return;  // Systick timer is 24 bit
-  SYSTICK->LOAD = ticks - 1;
-  SYSTICK->VAL = 0;
-  SYSTICK->CTRL = BIT(0) | BIT(1) | BIT(2);  // Enable systick
-}
-
-struct flash {
-  volatile uint32_t ACR, KEYR, OPTKEYR, SR, CR, AR, RESERVED, OBR, WRPR;
-};
-#define FLASH ((struct flash *) 0x40023c00)
-
-struct scb {
-  volatile uint32_t CPUID, ICSR, VTOR, AIRCR, SCR, CCR, SHPR[3], SHCSR, CFSR,
-      HFSR, DFSR, MMFAR, BFAR, AFSR, ID_PFR[2], ID_DFR, ID_AFR, ID_MFR[4],
-      ID_ISAR[5], RESERVED0[1], CLIDR, CTR, CCSIDR, CSSELR, CPACR,
-      RESERVED3[93], STIR, RESERVED4[15], MVFR0, MVFR1, MVFR2, RESERVED5[1],
-      ICIALLU, RESERVED6[1], ICIMVAU, DCIMVAC, DCISW, DCCMVAU, DCCMVAC, DCCSW,
-      DCCIMVAC, DCCISW, RESERVED7[6], ITCMCR, DTCMCR, AHBPCR, CACR, AHBSCR,
-      RESERVED8[1], ABFSR;
-};
-#define SCB ((struct scb *) 0xe000ed00)
-
-enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF, GPIO_MODE_ANALOG };
-enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN };
-enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_HIGH, GPIO_SPEED_INSANE };
-enum { GPIO_PULL_NONE, GPIO_PULL_UP, GPIO_PULL_DOWN };
-
-struct gpio {
-  volatile uint32_t MODER, OTYPER, OSPEEDR, PUPDR, IDR, ODR, BSRR, LCKR, AFR[2];
-};
-#define GPIO(N) ((struct gpio *) (0x40020000 + 0x400 * (N)))
-
-static struct gpio *gpio_bank(uint16_t pin) { return GPIO(PINBANK(pin)); }
-static inline void gpio_toggle(uint16_t pin) {
-  struct gpio *gpio = gpio_bank(pin);
-  uint32_t mask = BIT(PINNO(pin));
-  gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
-}
-static inline int gpio_read(uint16_t pin) {
-  return gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
-}
-static inline void gpio_write(uint16_t pin, bool val) {
-  struct gpio *gpio = gpio_bank(pin);
-  gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
-}
-static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
-                             uint8_t speed, uint8_t pull, uint8_t af) {
-  struct gpio *gpio = gpio_bank(pin);
-  uint8_t n = (uint8_t) (PINNO(pin));
-  RCC->AHB1ENR |= BIT(PINBANK(pin));  // Enable GPIO clock
-  SETBITS(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
-  SETBITS(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
-  SETBITS(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
-  SETBITS(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
-          ((uint32_t) af) << ((n & 7) * 4));
-  SETBITS(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
-}
-static inline void gpio_input(uint16_t pin) {
-  gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
-            GPIO_PULL_NONE, 0);
-}
-static inline void gpio_output(uint16_t pin) {
-  gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
-            GPIO_PULL_NONE, 0);
-}
-
-struct syscfg {
-  volatile uint32_t MEMRMP, PMC, EXTICR[4], RESERVED[2], CMPCR;
-};
-#define SYSCFG ((struct syscfg *) 0x40013800)
-
-struct exti {
-  volatile uint32_t IMR, EMR, RTSR, FTSR, SWIER, PR;
-};
-#define EXTI ((struct exti *) 0x40013c00)
-
-static inline void irq_exti_attach(uint16_t pin) {
-  uint8_t bank = (uint8_t) (PINBANK(pin)), n = (uint8_t) (PINNO(pin));
-  RCC->APB2ENR |= BIT(14);  // Enable SYSCFG
-  SYSCFG->EXTICR[n / 4] &= ~(15UL << ((n % 4) * 4));
-  SYSCFG->EXTICR[n / 4] |= (uint32_t) (bank << ((n % 4) * 4));
-  EXTI->IMR |= BIT(n);
-  EXTI->RTSR |= BIT(n);
-  EXTI->FTSR |= BIT(n);
-  int irqvec = n < 5 ? 6 + n : n < 10 ? 23 : 40;  // IRQ vector index, 10.1.2
-  nvic_set_prio(irqvec, 3);
-  nvic_enable_irq(irqvec);
-}
-
-struct uart {
-  volatile uint32_t CR1, CR2, CR3, BRR, GTPR, RTOR, RQR, ISR, ICR, RDR, TDR;
-};
-#define UART1 ((struct uart *) 0x40011000)
-#define UART2 ((struct uart *) 0x40004400)
-#define UART3 ((struct uart *) 0x40004800)
-
-static inline void uart_init(struct uart *uart, unsigned long baud) {
-  // https://www.st.com/resource/en/datasheet/stm32f746zg.pdf
-  uint8_t af = 7;           // Alternate function
-  uint16_t rx = 0, tx = 0;  // pins
-  uint32_t freq = 0;        // Bus frequency. UART1 is on APB2, rest on APB1
-
-  if (uart == UART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= BIT(4);
-  if (uart == UART2) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(17);
-  if (uart == UART3) freq = APB1_FREQUENCY, RCC->APB1ENR |= BIT(18);
-
-  if (uart == UART1) tx = PIN('A', 9), rx = PIN('A', 10);
-  if (uart == UART2) tx = PIN('A', 2), rx = PIN('A', 3);
-  if (uart == UART3) tx = PIN('D', 8), rx = PIN('D', 9);
-
-  gpio_init(tx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
-  gpio_init(rx, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, 0, af);
-  uart->CR1 = 0;                          // Disable this UART
-  uart->BRR = freq / baud;                 // Set baud rate
-  uart->CR1 |= BIT(0) | BIT(2) | BIT(3);  // Set UE, RE, TE
-}
-static inline void uart_write_byte(struct uart *uart, uint8_t byte) {
-  uart->TDR = byte;
-  while ((uart->ISR & BIT(7)) == 0) spin(1);
-}
-static inline void uart_write_buf(struct uart *uart, char *buf, size_t len) {
-  while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
-}
-static inline int uart_read_ready(struct uart *uart) {
-  return uart->ISR & BIT(5);  // If RXNE bit is set, data is ready
-}
-static inline uint8_t uart_read_byte(struct uart *uart) {
-  return (uint8_t) (uart->RDR & 255);
-}
-
-static inline void clock_init(void) {  // Set clock frequency
-#if 0
-  RCC->APB1ENR |= BIT(28);                     // Power enable
-  PWR->CR1 |= 3UL << 14;                       // Voltage regulator scale 3
-  PWR->CR1 |= BIT(16);                         // Enable overdrive
-  while ((PWR->CSR1 & BIT(16)) == 0) spin(1);  // Wait until done
-  PWR->CR1 |= BIT(17);                         // Enable overdrive switching
-  while ((PWR->CSR1 & BIT(17)) == 0) spin(1);  // Wait until done
-#endif
-  SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));  // Enable FPU
-  asm ("DSB");
-  asm ("ISB");
-  FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9);    // Flash latency, prefetch
-  RCC->PLLCFGR &= ~((BIT(17) - 1));                 // Clear PLL multipliers
-  RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16;    // Set PLL_P
-  RCC->PLLCFGR |= PLL_M | (PLL_N << 6);             // Set PLL_M and PLL_N
-  RCC->CR |= BIT(24);                               // Enable PLL
-  while ((RCC->CR & BIT(25)) == 0) spin(1);         // Wait until done
-  RCC->CFGR = (APB1_PRE << 10) | (APB2_PRE << 13);  // Set prescalers
-  RCC->CFGR |= 2;                                   // Set clock source to PLL
-  while ((RCC->CFGR & 12) == 0) spin(1);            // Wait until done
-}

examples/stm32/nucleo-f746zg-freertos-mip/mongoose_custom.h

@@ -2,6 +2,8 @@
 
 #include <errno.h>	// we are not using lwIP
 
+// See https://mongoose.ws/documentation/#build-options
 #define MG_ARCH MG_ARCH_FREERTOS
 #define MG_ENABLE_MIP 1
 #define MG_IO_SIZE 256
+#define MG_ENABLE_CUSTOM_RANDOM 1

examples/stm32/nucleo-f746zg-freertos-mip/syscalls.c

@@ -1,6 +1,6 @@
 #include <sys/stat.h>
 
-#include "mcu.h"
+#include "hal.h"
 
 int _fstat(int fd, struct stat *st) {
   if (fd < 0) return -1;
@@ -8,12 +8,6 @@ int _fstat(int fd, struct stat *st) {
   return 0;
 }
 
-int _write(int fd, char *ptr, int len) {
-  (void) fd, (void) ptr, (void) len;
-  if (fd == 1) uart_write_buf(UART3, ptr, (size_t) len);
-  return len;
-}
-
 void *_sbrk(int incr) {
   extern char _end;
   static unsigned char *heap = NULL;
@@ -24,6 +18,11 @@ void *_sbrk(int incr) {
   return prev_heap;
 }
 
+int _open(const char *path) {
+  (void) path;
+  return -1;
+}
+
 int _close(int fd) {
   (void) fd;
   return -1;
@@ -34,12 +33,53 @@ int _isatty(int fd) {
   return 1;
 }
 
+int _lseek(int fd, int ptr, int dir) {
+  (void) fd, (void) ptr, (void) dir;
+  return 0;
+}
+
+void _exit(int status) {
+  (void) status;
+  for (;;) asm volatile("BKPT #0");
+}
+
+void _kill(int pid, int sig) {
+  (void) pid, (void) sig;
+}
+
+int _getpid(void) {
+  return -1;
+}
+
+int _write(int fd, char *ptr, int len) {
+  (void) fd, (void) ptr, (void) len;
+  if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
+  return -1;
+}
+
 int _read(int fd, char *ptr, int len) {
   (void) fd, (void) ptr, (void) len;
   return -1;
 }
 
-int _lseek(int fd, int ptr, int dir) {
-  (void) fd, (void) ptr, (void) dir;
-  return 0;
+int _link(const char *a, const char *b) {
+  (void) a, (void) b;
+  return -1;
 }
+
+int _unlink(const char *a) {
+  (void) a;
+  return -1;
+}
+
+int _stat(const char *path, struct stat *st) {
+  (void) path, (void) st;
+  return -1;
+}
+
+int mkdir(const char *path, mode_t mode) {
+  (void) path, (void) mode;
+  return -1;
+}
+
+void _init(void) {}

examples/stm32/nucleo-f746zg-freertos-mip/sysinit.c

@@ -0,0 +1,29 @@
+// Copyright (c) 2023 Cesanta Software Limited
+// All rights reserved
+//
+// This file contains essentials required by the CMSIS:
+// uint32_t SystemCoreClock - holds the system core clock value
+// SystemInit() - initialises the system, e.g. sets up clocks
+
+#include "hal.h"
+
+uint32_t SystemCoreClock = SYS_FREQUENCY;
+
+void SystemInit(void) {  // Called automatically by startup code
+  SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));  // Enable FPU
+  asm("DSB");
+  asm("ISB");
+  FLASH->ACR |= FLASH_LATENCY | BIT(8) | BIT(9);    // Flash latency, prefetch
+  RCC->PLLCFGR &= ~((BIT(17) - 1));                 // Clear PLL multipliers
+  RCC->PLLCFGR |= (((PLL_P - 2) / 2) & 3) << 16;    // Set PLL_P
+  RCC->PLLCFGR |= PLL_M | (PLL_N << 6);             // Set PLL_M and PLL_N
+  RCC->CR |= BIT(24);                               // Enable PLL
+  while ((RCC->CR & BIT(25)) == 0) spin(1);         // Wait until done
+  RCC->CFGR = (APB1_PRE << 10) | (APB2_PRE << 13);  // Set prescalers
+  RCC->CFGR |= 2;                                   // Set clock source to PLL
+  while ((RCC->CFGR & 12) == 0) spin(1);            // Wait until done
+
+  RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;    // Enable SYSCFG
+  rng_init();                              // Initialise random number generator
+  SysTick_Config(SystemCoreClock / 1000);  // Sys tick every 1ms
+}

examples/ti/ek-tm4c1294xl-freertos-mip/main.c

@@ -32,7 +32,7 @@ static void ethernet_init(void) {
             GPIO_PULL_NONE, 5);  // EN0LED1
   gpio_init(LED4, GPIO_MODE_AF, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH,
             GPIO_PULL_NONE, 5);  // EN0LED0
-  nvic_enable_irq(40);  // Setup Ethernet IRQ handler
+  nvic_enable_irq(40);           // Setup Ethernet IRQ handler
   // Initialize Ethernet clocks, see datasheet section 5
   // Turn Flash Prefetch off (silicon errata ETH#02)
   volatile uint32_t *IMC = (uint32_t *) 0x400FD000;
@@ -85,15 +85,15 @@ static void blinker(void *args) {
   for (;;) {
     gpio_toggle(LED1);
     vTaskDelay(pdMS_TO_TICKS(750));
-    (void)args;//MG_INFO(("blink %s,  RAM: %u", (char *) args, xPortGetFreeHeapSize()));
+    (void) args;  // MG_INFO(("blink %s,  RAM: %u", (char *) args,
+                  // xPortGetFreeHeapSize()));
   }
 }
 
 int main(void) {
-  static struct uart *uart = UART0;  // Use UART0 (attached to ICDI)
-  clock_init();                      // Set clock to 120MHz
-  systick_init(FREQ / 1000);  // Tick every 1 ms
-  uart_init(uart, 115200);   // Initialise UART
+  clock_init();                   // Set clock to 120MHz
+  systick_init(FREQ / 1000);      // Tick every 1 ms
+  uart_init(UART_DEBUG, 115200);  // Initialise UART
   xTaskCreate(blinker, "blinker", 128, ":)", configMAX_PRIORITIES - 1, NULL);
   xTaskCreate(server, "server", 2048, 0, configMAX_PRIORITIES - 1, NULL);
   vTaskStartScheduler();  // This blocks

examples/ti/ek-tm4c1294xl-freertos-mip/mcu.h

@@ -190,6 +190,10 @@ struct uart {
 
 #define UART0 USART(0)
 
+#ifndef UART_DEBUG
+#define UART_DEBUG UART0
+#endif
+
 static inline void uart_init(struct uart *uart, unsigned long baud) {
   struct uarthw {
     uint16_t rx, tx;  // pins

examples/ti/ek-tm4c1294xl-freertos-mip/syscalls.c

@@ -8,12 +8,6 @@ int _fstat(int fd, struct stat *st) {
   return 0;
 }
 
-int _write(int fd, char *ptr, int len) {
-  (void) fd, (void) ptr, (void) len;
-  if (fd == 1) uart_write_buf(UART0, ptr, (size_t) len);
-  return len;
-}
-
 void *_sbrk(int incr) {
   extern char _end;
   static unsigned char *heap = NULL;
@@ -24,6 +18,11 @@ void *_sbrk(int incr) {
   return prev_heap;
 }
 
+int _open(const char *path) {
+  (void) path;
+  return -1;
+}
+
 int _close(int fd) {
   (void) fd;
   return -1;
@@ -34,12 +33,53 @@ int _isatty(int fd) {
   return 1;
 }
 
+int _lseek(int fd, int ptr, int dir) {
+  (void) fd, (void) ptr, (void) dir;
+  return 0;
+}
+
+void _exit(int status) {
+  (void) status;
+  for (;;) asm volatile("BKPT #0");
+}
+
+void _kill(int pid, int sig) {
+  (void) pid, (void) sig;
+}
+
+int _getpid(void) {
+  return -1;
+}
+
+int _write(int fd, char *ptr, int len) {
+  (void) fd, (void) ptr, (void) len;
+  if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
+  return -1;
+}
+
 int _read(int fd, char *ptr, int len) {
   (void) fd, (void) ptr, (void) len;
   return -1;
 }
 
-int _lseek(int fd, int ptr, int dir) {
-  (void) fd, (void) ptr, (void) dir;
-  return 0;
+int _link(const char *a, const char *b) {
+  (void) a, (void) b;
+  return -1;
 }
+
+int _unlink(const char *a) {
+  (void) a;
+  return -1;
+}
+
+int _stat(const char *path, struct stat *st) {
+  (void) path, (void) st;
+  return -1;
+}
+
+int mkdir(const char *path, mode_t mode) {
+  (void) path, (void) mode;
+  return -1;
+}
+
+void _init(void) {}