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https://github.com/cesanta/mongoose.git
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move vendors -> tutorials
This commit is contained in:
Sergio R. Caprile committed
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@@ -0,0 +1,53 @@
|
||||
CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion
|
||||
CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
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||||
CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
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||||
CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include
|
||||
CFLAGS += -Icmsis_mcu/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include
|
||||
CFLAGS += -Icmsis_mcu/ra/fsp/src/bsp/mcu/all
|
||||
CFLAGS += -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard $(CFLAGS_EXTRA)
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LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
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||||
SOURCES = main.c hal.c mongoose.c net.c packed_fs.c
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||||
# CMSIS startup and system files are deeply tied to the BSP, and we don't use it. See hal.c
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||||
|
||||
# Example specific build options. See README.md
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||||
CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\"
|
||||
|
||||
ifeq ($(OS),Windows_NT)
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||||
RM = cmd /C del /Q /F /S
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else
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RM = rm -rf
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endif
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||||
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||||
all build example: firmware.bin
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firmware.bin: firmware.elf
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arm-none-eabi-objcopy -O binary $< $@
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||||
|
||||
firmware.elf: cmsis_core cmsis_mcu $(SOURCES) hal.h link.ld Makefile
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arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@
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arm-none-eabi-size $@
|
||||
|
||||
flash: firmware.bin
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||||
rfp-cli -d ra -t jlink -v -p -bin 0x0000000 $<
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rfp-cli -d ra -t jlink -rv 0x8000000 256
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|
||||
cmsis_core: # ARM CMSIS core headers
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git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
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||||
cmsis_mcu:
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||||
git clone -q --depth 1 -b v5.1.0 https://github.com/renesas/fsp $@
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||||
|
||||
|
||||
# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
|
||||
DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/14
|
||||
update: firmware.bin
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
|
||||
|
||||
update: CFLAGS += -DUART_DEBUG=R_SCI7
|
||||
|
||||
test: update
|
||||
curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt
|
||||
grep 'READY, IP:' /tmp/output.txt # Check for network init
|
||||
|
||||
clean:
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$(RM) firmware.* *.su cmsis_core cmsis_mcu mbedtls *.zip
|
||||
@@ -0,0 +1,164 @@
|
||||
// Copyright (c) 2024 Cesanta Software Limited
|
||||
// All rights reserved
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||||
|
||||
#include <stdint.h>
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#include <string.h>
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#include <sys/stat.h> // For _fstat()
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||||
|
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#include "hal.h"
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|
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uint32_t SystemCoreClock = SYS_FREQUENCY;
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||||
static volatile uint64_t s_ticks; // Milliseconds since boot
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||||
|
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extern void _estack(void); // Defined in link.ld
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void Reset_Handler(void);
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void SysTick_Handler(void);
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||||
extern void EDMAC_IRQHandler(void);
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||||
|
||||
// 16 ARM and 200 peripheral handlers
|
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__attribute__((section(".vectors"))) void (*const tab[16 + 10])(void) = {
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_estack, Reset_Handler, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
SysTick_Handler, EDMAC_IRQHandler};
|
||||
|
||||
void Reset_Handler(void) {
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extern long _sbss[], _ebss[], _sdata[], _edata[], _sidata[];
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extern int main(void);
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|
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SCB->VTOR = (uint32_t) tab;
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||||
for (long *dst = _sbss; dst < _ebss; dst++) *dst = 0;
|
||||
for (long *dst = _sdata, *src = _sidata; dst < _edata;) *dst++ = *src++;
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||||
|
||||
SystemInit();
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main();
|
||||
while (1) (void) 0;
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||||
}
|
||||
|
||||
void SystemInit(void) { // Called automatically by startup code
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||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU
|
||||
__DSB();
|
||||
__ISB();
|
||||
clock_init(); // Set system clock to SYS_FREQUENCY
|
||||
rng_init(); // Initialise random number generator
|
||||
SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
|
||||
}
|
||||
|
||||
void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
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s_ticks++;
|
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}
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||||
|
||||
#if 0
|
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bool mg_random(void *buf, size_t len) { // Use on-board RNG
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for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
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uint32_t r = rng_read();
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memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
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}
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return true;
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}
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#endif
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uint64_t mg_millis(void) { // Let Mongoose use our uptime function
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return s_ticks; // Return number of milliseconds since boot
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}
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|
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void hal_init(void) {
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uart_init(UART_DEBUG, 115200); // Initialise UART
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gpio_output(LED1); // Initialise LED
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gpio_output(LED2); // Initialise LED
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gpio_output(LED3); // Initialise LED
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||||
ethernet_init(); // Initialise Ethernet pins
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}
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|
||||
// Newlib syscalls. Implemented are: _sbrk() for malloc, and _write()
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int _fstat(int fd, struct stat *st) {
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(void) fd, (void) st;
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return -1;
|
||||
}
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extern unsigned char _end[]; // End of data section, start of heap. See link.ld
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static unsigned char *s_current_heap_end = _end;
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size_t hal_ram_used(void) {
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return (size_t) (s_current_heap_end - _end);
|
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}
|
||||
|
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size_t hal_ram_free(void) {
|
||||
unsigned char endofstack;
|
||||
return (size_t) (&endofstack - s_current_heap_end);
|
||||
}
|
||||
|
||||
void *_sbrk(int incr) {
|
||||
unsigned char *prev_heap;
|
||||
unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
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||||
prev_heap = s_current_heap_end;
|
||||
// Check how much space we got from the heap end to the stack end
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if (s_current_heap_end + incr > heap_end) return (void *) -1;
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s_current_heap_end += incr;
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return prev_heap;
|
||||
}
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||||
|
||||
int _open(const char *path) {
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||||
(void) path;
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||||
return -1;
|
||||
}
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||||
|
||||
int _close(int fd) {
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||||
(void) fd;
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||||
return -1;
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||||
}
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int _isatty(int fd) {
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(void) fd;
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return 1;
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}
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int _lseek(int fd, int ptr, int dir) {
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(void) fd, (void) ptr, (void) dir;
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||||
return 0;
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||||
}
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||||
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||||
void _exit(int status) {
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(void) status;
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||||
for (;;) asm volatile("BKPT #0");
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||||
}
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void _kill(int pid, int sig) {
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||||
(void) pid, (void) sig;
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||||
}
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||||
int _getpid(void) {
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return -1;
|
||||
}
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||||
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int _write(int fd, char *ptr, int len) {
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(void) fd, (void) ptr, (void) len;
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||||
if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len);
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||||
return -1;
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||||
}
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||||
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||||
int _read(int fd, char *ptr, int len) {
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||||
(void) fd, (void) ptr, (void) len;
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||||
return -1;
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||||
}
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||||
|
||||
int _link(const char *a, const char *b) {
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||||
(void) a, (void) b;
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return -1;
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||||
}
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||||
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||||
int _unlink(const char *a) {
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(void) a;
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return -1;
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||||
}
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||||
|
||||
int _stat(const char *path, struct stat *st) {
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||||
(void) path, (void) st;
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return -1;
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}
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||||
|
||||
int mkdir(const char *path, mode_t mode) {
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||||
(void) path, (void) mode;
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return -1;
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}
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||||
|
||||
void _init(void) {
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||||
}
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@@ -0,0 +1,202 @@
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// Copyright (c) 2024 Cesanta Software Limited
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// All rights reserved
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||||
//
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||||
// MCU and ek-ra6m4 eval board datasheets:
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||||
// https://www.renesas.com/us/en/document/man/ra6m4-group-user-s-manual-hardware
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||||
// https://www.renesas.com/us/en/document/man/ek-ra6m5-v1-users-manual
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||||
#pragma once
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||||
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||||
#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include "bsp_exceptions.h"
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#include "R7FA6M4AF.h"
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extern void hal_init(void);
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#define BIT(x) (1UL << (x))
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#define SETBITS(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
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#define PIN(port, num) ((((port) - '0') << 8) | (num))
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#define PIN_NUM(pin) (pin & 255)
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#define PIN_PORT(pin) (pin >> 8)
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#define LED1 PIN('4', 15) // blue
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#define LED2 PIN('4', 4) // green
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#define LED3 PIN('4', 0) // red
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#define LED LED2 // Use green LED for blinking
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#define rng_read() 0
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#define rng_init()
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#define GENERATE_MAC_ADDRESS() \
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{ 2, 3, 4, 5, 6, 7 }
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// Clock
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||||
// Board UM: P212 P213 24MHz xtal
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||||
// - (8.1 Table 8.1) (50.3.1 Table 50.14): PLL 120 ~ 200 MHz; input 8 ~ 24 MHz.
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||||
// System clock (ICLK) <= 200 MHz; PCLKA <= 100 MHz; PCLKB <= 50 MHz
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||||
// - (8.2.2): ICLK >= other clocks of interest for us
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||||
// - (8.7.3): FlashIF Clock (FCLK) (8.1 Table 8.1): 4 MHz to 50 MHz(P/E), up to
|
||||
// 50 MHz (R)
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||||
// - (8.2.9): MOSCCR Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting
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||||
// this register.
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// - (10.2.9) OPCCR : Operating Power Control Register, defaults to high-speed
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||||
// mode
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||||
// - (45.2.4) 1 wait state for SRAM (default);
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||||
#define SYS_FREQUENCY 200000000
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#define PLL_MUL 49 // x25 ((n+1)/2)
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#define PLL_DIV 2 // /3 (n+1)
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||||
#define ICLK_DIV 0 // /1 -> 200MHz (/(2^n))
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||||
#define FCLK_DIV 2 // /4 -> 50MHz
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||||
#define PCLKAD_DIV 1 // /2 -> 100MHz
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||||
#define PCLKBC_DIV 2 // /4 -> 50MHz
|
||||
#define FLASH_MHZ (SYS_FREQUENCY / ((1 << FCLK_DIV) * 1000000))
|
||||
static inline void clock_init(void) {
|
||||
R_SYSTEM->PRCR = 0xA501; // enable writing to osc control regs (12.2.1)
|
||||
R_SYSTEM->MOSCWTCR = 9; // (8.2.5, 8.2.4)
|
||||
R_SYSTEM->MOSCCR = 0; // enable main oscillator, default cfg (20~24MHz)
|
||||
while (R_SYSTEM->OSCSF_b.MOSCSF == 0) (void) 0; // wait until it stabilizes
|
||||
R_SYSTEM->PLLCCR =
|
||||
(PLL_MUL << R_SYSTEM_PLLCCR_PLLMUL_Pos) |
|
||||
(PLL_DIV
|
||||
<< R_SYSTEM_PLLCCR_PLIDIV_Pos); // config PLL for MOSC /3 x 25 (8.2.4)
|
||||
R_SYSTEM->PLLCR = 0; // enable PLL
|
||||
R_SYSTEM->SCKDIVCR =
|
||||
(FCLK_DIV << R_SYSTEM_SCKDIVCR_FCK_Pos) |
|
||||
(ICLK_DIV << R_SYSTEM_SCKDIVCR_ICK_Pos) |
|
||||
(PCLKAD_DIV << R_SYSTEM_SCKDIVCR_BCK_Pos) |
|
||||
(PCLKAD_DIV << R_SYSTEM_SCKDIVCR_PCKA_Pos) |
|
||||
(PCLKBC_DIV << R_SYSTEM_SCKDIVCR_PCKB_Pos) |
|
||||
(PCLKBC_DIV << R_SYSTEM_SCKDIVCR_PCKC_Pos) |
|
||||
(PCLKAD_DIV << R_SYSTEM_SCKDIVCR_PCKD_Pos); // set dividers
|
||||
R_FCACHE->FLWT = 3; // flash: 3 wait states (47.4.3)
|
||||
R_FLAD->FCKMHZ = FLASH_MHZ; // flash: read speed optimization (47.4.28)
|
||||
R_FACI_HP->FPCKAR = (0x1E << 8) + FLASH_MHZ; // flash: write (47.4.26)
|
||||
while (R_SYSTEM->OSCSF_b.PLLSF == 0) (void) 0; // PLL stabilization
|
||||
while (R_FLAD->FCKMHZ != FLASH_MHZ) (void) 0; // flash module magic
|
||||
R_SYSTEM->SCKSCR = 5; // select PLL (8.2.3)
|
||||
}
|
||||
|
||||
// GPIO
|
||||
#define GPIO(N) ((R_PORT0_Type *) (R_PORT0_BASE + 0x20 * (N)))
|
||||
enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_AF };
|
||||
|
||||
static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t af) {
|
||||
R_PORT0_Type *gpio = GPIO(PIN_PORT(pin));
|
||||
|
||||
if (mode == GPIO_MODE_OUTPUT) {
|
||||
gpio->PCNTR1 |= BIT(PIN_NUM(pin));
|
||||
} else if (mode == GPIO_MODE_INPUT) {
|
||||
gpio->PCNTR1 &= ~BIT(PIN_NUM(pin));
|
||||
} else { // GPIO_MODE_AF
|
||||
// TODO(): only non-analog supported (19.2.5)
|
||||
R_PMISC->PWPR_b.B0WI = 0; // (19.5.1--> (RM says this is PFS...)
|
||||
R_PMISC->PWPR_b.PFSWE = 1;
|
||||
R_PFS->PORT[PIN_PORT(pin)].PIN[PIN_NUM(pin)].PmnPFS_b.PMR = 0;
|
||||
R_PFS->PORT[PIN_PORT(pin)].PIN[PIN_NUM(pin)].PmnPFS_b.PSEL =
|
||||
af & (R_PFS_PORT_PIN_PmnPFS_PSEL_Msk >> R_PFS_PORT_PIN_PmnPFS_PSEL_Pos);
|
||||
R_PFS->PORT[PIN_PORT(pin)].PIN[PIN_NUM(pin)].PmnPFS_b.PMR = 1;
|
||||
R_PFS->PORT[PIN_PORT(pin)].PIN[PIN_NUM(pin)].PmnPFS_b.DSCR = 2; // high
|
||||
R_PMISC->PWPR_b.PFSWE = 0;
|
||||
R_PMISC->PWPR_b.B0WI = 1; // <--19.5.1)
|
||||
}
|
||||
}
|
||||
|
||||
static inline void gpio_output(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_OUTPUT, 0);
|
||||
}
|
||||
|
||||
static inline void gpio_input(uint16_t pin) {
|
||||
gpio_init(pin, GPIO_MODE_INPUT, 0);
|
||||
}
|
||||
|
||||
static inline bool gpio_read(uint16_t pin) {
|
||||
R_PORT0_Type *gpio = GPIO(PIN_PORT(pin));
|
||||
return gpio->PCNTR2 & BIT(PIN_NUM(pin)) ? true : false;
|
||||
}
|
||||
|
||||
static inline void gpio_write(uint16_t pin, bool val) {
|
||||
R_PORT0_Type *gpio = GPIO(PIN_PORT(pin));
|
||||
gpio->PCNTR3 = BIT(PIN_NUM(pin)) << (val ? 0 : 16U);
|
||||
}
|
||||
|
||||
static inline void gpio_toggle(uint16_t pin) {
|
||||
gpio_write(pin, !gpio_read(pin));
|
||||
}
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG R_SCI7
|
||||
#endif
|
||||
#define UART_TX PIN('6', 13) // SCI7
|
||||
#define UART_RX PIN('6', 14)
|
||||
|
||||
// UART
|
||||
// (datasheet, after BSP rev.eng.) SCI uses PCLKA in this chip
|
||||
static inline void uart_init(R_SCI0_Type *uart, unsigned baud) {
|
||||
if (uart != R_SCI7) return;
|
||||
R_MSTP->MSTPCRB_b.MSTPB24 = 0; // enable SCI7
|
||||
(void) R_MSTP->MSTPCRB; // (10.10.15)
|
||||
uart->SCR = 0; // (29.3.7 -->) disable SCI
|
||||
uart->FCR_b.FM = 0; // disable FIFO
|
||||
uart->SIMR1 = 0; // disable I2C (default)
|
||||
uart->SPMR = 0; // disable SPI (default)
|
||||
uart->SCMR_b.SMIF = 0; // no smartcard (default)
|
||||
uart->SMR = 0; // async 8N1, use PCLK
|
||||
uart->SCMR_b.CHR1 = 1; // disable 9-bit mode (default)
|
||||
uart->SEMR = 0; // 16x clocking (other SCIs need internal clock setting)
|
||||
uart->SPTR = 3; // no inversions, high on idle
|
||||
uart->BRR = (uint8_t) (SYS_FREQUENCY / (32 * (1 << PCLKAD_DIV) * baud));
|
||||
gpio_init(UART_TX, GPIO_MODE_AF, 5); // (19.6)
|
||||
gpio_init(UART_RX, GPIO_MODE_AF, 5);
|
||||
(void) uart, (void) baud;
|
||||
uart->SCR = R_SCI0_SCR_TE_Msk | R_SCI0_SCR_RE_Msk; // enable Tx, Rx
|
||||
}
|
||||
|
||||
static inline void uart_write_byte(R_SCI0_Type *uart, uint8_t byte) {
|
||||
uart->TDR = byte;
|
||||
while (uart->SSR_b.TDRE == 0) (void) 0;
|
||||
}
|
||||
|
||||
static inline void uart_write_buf(R_SCI0_Type *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
|
||||
static inline int uart_read_ready(R_SCI0_Type *uart) {
|
||||
return uart->SSR_b.RDRF; // If RDRF bit is set, data is ready
|
||||
}
|
||||
static inline uint8_t uart_read_byte(R_SCI0_Type *uart) {
|
||||
return uart->RDR;
|
||||
}
|
||||
|
||||
// Ethernet
|
||||
// - (13.3.2 Table 13.4) Event table: Event 0x16F, ETHER_EINT0
|
||||
// - (13.1) ICU (13.3.1) Interrupt Vector Table (13.5)
|
||||
// - Choose a IELSRx, that is IRQn=x in NVIC, write event number
|
||||
static inline void ethernet_init(void) {
|
||||
R_MSTP->MSTPCRB_b.MSTPB15 = 0; // enable ETHERC0 and EDMAC0
|
||||
(void) R_MSTP->MSTPCRB; // (10.10.15)
|
||||
// (Board manual: 4.3.3 Table 1, 6.1 Table 20) (RM: 19.6)
|
||||
R_SYSTEM->PRCR = 0xA502; // enable writing to next reg (12.2.1)
|
||||
R_SYSTEM->VBTICTLR = 0; // enable MDC pins (19.5.5) (11.2.6)
|
||||
gpio_init(PIN('4', 1), GPIO_MODE_AF, 0x17); // MDC
|
||||
gpio_init(PIN('4', 2), GPIO_MODE_AF, 0x17); // MDIO
|
||||
gpio_output(PIN('4', 3)); // PHY RST
|
||||
gpio_write(PIN('0', 2), 1); // prevent NAND_TREE
|
||||
gpio_write(PIN('4', 3), 0); // assert RST
|
||||
gpio_init(PIN('4', 5), GPIO_MODE_AF, 0x17); // TX_EN
|
||||
gpio_init(PIN('4', 6), GPIO_MODE_AF, 0x17); // TXD1
|
||||
gpio_init(PIN('7', 0), GPIO_MODE_AF, 0x17); // TXD0
|
||||
gpio_init(PIN('7', 1), GPIO_MODE_AF, 0x17); // REF50CK0
|
||||
gpio_init(PIN('7', 2), GPIO_MODE_AF, 0x17); // RXD0
|
||||
gpio_init(PIN('7', 3), GPIO_MODE_AF, 0x17); // RXD1
|
||||
gpio_init(PIN('7', 4), GPIO_MODE_AF, 0x17); // RX_ER
|
||||
gpio_init(PIN('7', 5), GPIO_MODE_AF, 0x17); // CRS_DV
|
||||
R_PMISC->PFENET_b.PHYMODE0 = 0; // select RMII
|
||||
for (volatile int i = 0; i < 0x2000; i++)
|
||||
(void) 0; // keep PHY RST low for a while
|
||||
gpio_write(PIN('4', 3), 1); // deassert RST
|
||||
gpio_input(PIN('0', 2)); // PHY IRQ, not used
|
||||
NVIC_EnableIRQ(0); // (13.5.1) no CMSIS support
|
||||
R_ICU->IELSR[0] = 0x16f; // (13.2.15)(13.5.4.1)
|
||||
}
|
||||
@@ -0,0 +1,30 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash(rx) : ORIGIN = 0x00000000, LENGTH = 1024k
|
||||
sram(rwx) : ORIGIN = 0x20000000, LENGTH = 256k
|
||||
}
|
||||
_estack = ORIGIN(sram) + LENGTH(sram); /* End of RAM. stack points here */
|
||||
|
||||
SECTIONS {
|
||||
.vectors : { KEEP(*(.isr_vector)) } > flash
|
||||
.text : { *(.text* .text.*) } > flash
|
||||
.rodata : { *(.rodata*) } > flash
|
||||
|
||||
.data : {
|
||||
_sdata = .;
|
||||
*(.first_data)
|
||||
*(.ram)
|
||||
*(.data SORT(.data.*))
|
||||
_edata = .;
|
||||
} > sram AT > flash
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : {
|
||||
_sbss = .;
|
||||
*(.bss SORT(.bss.*) COMMON)
|
||||
_ebss = .;
|
||||
} > sram
|
||||
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
}
|
||||
@@ -0,0 +1,55 @@
|
||||
// Copyright (c) 2023 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
#include "mongoose.h"
|
||||
#include "net.h"
|
||||
|
||||
#define BLINK_PERIOD_MS 1000 // LED blinking period in millis
|
||||
|
||||
static void timer_fn(void *arg) {
|
||||
gpio_toggle(LED); // Blink LED
|
||||
struct mg_tcpip_if *ifp = arg; // And show
|
||||
const char *names[] = {"down", "up", "req", "ready"}; // network stats
|
||||
MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u",
|
||||
names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent,
|
||||
ifp->ndrop, ifp->nerr));
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
hal_init();
|
||||
|
||||
struct mg_mgr mgr; // Initialise
|
||||
mg_mgr_init(&mgr); // Mongoose event manager
|
||||
mg_log_set(MG_LL_DEBUG); // Set log level
|
||||
|
||||
MG_INFO(("Starting, CPU freq %g MHz", (double) SystemCoreClock / 1000000));
|
||||
|
||||
// Initialise Mongoose network stack
|
||||
struct mg_tcpip_driver_ra_data driver_data = {
|
||||
.clock = SystemCoreClock, .irqno = 0, .phy_addr = 1};
|
||||
struct mg_tcpip_if mif = {// .mac = {...}, generate random mac address
|
||||
// Uncomment below for static configuration:
|
||||
// .ip = mg_htonl(MG_U32(192, 168, 0, 223)),
|
||||
// .mask = mg_htonl(MG_U32(255, 255, 255, 0)),
|
||||
// .gw = mg_htonl(MG_U32(192, 168, 0, 1)),
|
||||
.driver = &mg_tcpip_driver_ra,
|
||||
.driver_data = &driver_data};
|
||||
mg_tcpip_init(&mgr, &mif);
|
||||
mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif);
|
||||
|
||||
MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac));
|
||||
while (mif.state != MG_TCPIP_STATE_READY) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
MG_INFO(("Initialising application..."));
|
||||
web_init(&mgr);
|
||||
|
||||
MG_INFO(("Starting event loop"));
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1 @@
|
||||
../../../mongoose.c
|
||||
@@ -0,0 +1 @@
|
||||
../../../mongoose.h
|
||||
@@ -0,0 +1,11 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_NEWLIB
|
||||
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 0
|
||||
#define MG_ENABLE_PACKED_FS 1
|
||||
#define MG_ENABLE_DRIVER_RA 1
|
||||
//#define MG_ENABLE_LINES 1
|
||||
@@ -0,0 +1 @@
|
||||
../../device-dashboard/net.c
|
||||
@@ -0,0 +1 @@
|
||||
../../device-dashboard/net.h
|
||||
@@ -0,0 +1 @@
|
||||
../../device-dashboard/packed_fs.c
|
||||
Reference in new issue
Block a user