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Add teensy41 example
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cpq committed
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-462
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+76
-56
@@ -27,14 +27,10 @@ struct rt1020_enet {
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};
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#undef ENET
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#define ENET ((struct rt1020_enet *) (uintptr_t) 0x402D8000u)
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#define ENET ((struct rt1020_enet *) (uintptr_t) 0x402D8000U)
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#undef BIT
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#define BIT(x) ((uint32_t) 1 << (x))
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// Max frame size, every buffer must be 64-bit aligned (1536 = 0x600)
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#define ETH_PKT_SIZE 1536
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#define ETH_DESC_CNT 4 // Descriptors count
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#define ETH_PKT_SIZE 1536 // Max frame size, 64-bit aligned
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#define ETH_DESC_CNT 4 // Descriptors count
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typedef struct {
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uint16_t length; // Data length
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@@ -43,29 +39,30 @@ typedef struct {
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} enet_bd_t;
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// TODO(): handle these in a portable compiler-independent CMSIS-friendly way
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// Descriptors: in non-cached area (TODO(scaprile)), 64-bit aligned
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enet_bd_t s_rxdesc[ETH_DESC_CNT] __attribute__((aligned((64U))));
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enet_bd_t s_txdesc[ETH_DESC_CNT] __attribute__((aligned((64U))));
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// Buffers: 64-bit aligned
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uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] __attribute__((aligned((64U))));
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uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] __attribute__((aligned((64U))));
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#define MG_A64 __attribute__((aligned((64U))))
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// Descriptors: in non-cached area (TODO(scaprile)), 64-bit aligned
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// Buffers: 64-bit aligned
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static volatile enet_bd_t s_rxdesc[ETH_DESC_CNT] MG_A64;
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static volatile enet_bd_t s_txdesc[ETH_DESC_CNT] MG_A64;
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_A64;
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE] MG_A64;
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static struct mg_tcpip_if *s_ifp; // MIP interface
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enum { PHY_ADDR = 2, PHY_BCR = 0, PHY_BSR = 1, PHY_PC1R = 30, PHY_PC2R = 31 };
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enum { PHY_BCR = 0, PHY_BSR = 1, PHY_ID1 = 2, PHY_ID2 = 3 };
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static uint32_t eth_read_phy(uint8_t addr, uint8_t reg) {
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ENET->EIR |= BIT(23); // MII interrupt clear
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static uint16_t rt10xx_phy_read(uint8_t addr, uint8_t reg) {
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ENET->EIR |= MG_BIT(23); // MII interrupt clear
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ENET->MMFR = (1 << 30) | (2 << 28) | (addr << 23) | (reg << 18) | (2 << 16);
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while ((ENET->EIR & BIT(23)) == 0) (void) 0;
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while ((ENET->EIR & MG_BIT(23)) == 0) (void) 0;
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return ENET->MMFR & 0xffff;
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}
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static void eth_write_phy(uint8_t addr, uint8_t reg, uint32_t val) {
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ENET->EIR |= BIT(23); // MII interrupt clear
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static void rt10xx_phy_write(uint8_t addr, uint8_t reg, uint16_t val) {
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ENET->EIR |= MG_BIT(23); // MII interrupt clear
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ENET->MMFR =
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(1 << 30) | (1 << 28) | (addr << 23) | (reg << 18) | (2 << 16) | val;
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while ((ENET->EIR & BIT(23)) == 0) (void) 0;
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while ((ENET->EIR & MG_BIT(23)) == 0) (void) 0;
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}
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// MDC clock is generated from IPS Bus clock (ipg_clk); as per 802.3,
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@@ -78,34 +75,51 @@ static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) {
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// Init RX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_rxdesc[i].control = BIT(15); // Own (E)
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s_rxdesc[i].control = MG_BIT(15); // Own (E)
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s_rxdesc[i].buffer = (uint32_t *) s_rxbuf[i]; // Point to data buffer
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}
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s_rxdesc[ETH_DESC_CNT - 1].control |= BIT(13); // Wrap last descriptor
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s_rxdesc[ETH_DESC_CNT - 1].control |= MG_BIT(13); // Wrap last descriptor
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// Init TX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_txdesc[i].control = BIT(10); // Own (TC)
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//s_txdesc[i].control = MG_BIT(10); // Own (TC)
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s_txdesc[i].buffer = (uint32_t *) s_txbuf[i];
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}
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s_txdesc[ETH_DESC_CNT - 1].control |= BIT(13); // Wrap last descriptor
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s_txdesc[ETH_DESC_CNT - 1].control |= MG_BIT(13); // Wrap last descriptor
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ENET->ECR = BIT(0); // Software reset, disable
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while ((ENET->ECR & BIT(0))) (void) 0; // Wait until done
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ENET->ECR = MG_BIT(0); // Software reset, disable
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while ((ENET->ECR & MG_BIT(0))) (void) 0; // Wait until done
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// Set MDC clock divider. If user told us the value, use it.
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// TODO(): Otherwise, guess (currently assuming max freq)
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int cr = (d == NULL || d->mdc_cr < 0) ? 24 : d->mdc_cr;
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ENET->MSCR = (1 << 8) | ((cr & 0x3f) << 1); // HOLDTIME 2 clks
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eth_write_phy(PHY_ADDR, PHY_BCR, BIT(15)); // Reset PHY
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eth_write_phy(PHY_ADDR, PHY_BCR, BIT(12)); // Set autonegotiation
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rt10xx_phy_write(d->phy_addr, PHY_BCR, MG_BIT(15)); // Reset PHY
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rt10xx_phy_write(d->phy_addr, PHY_BCR, MG_BIT(12)); // Set autonegotiation
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// PHY: Enable 50 MHz external ref clock at XI (preserve defaults)
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eth_write_phy(PHY_ADDR, PHY_PC2R, BIT(15) | BIT(8) | BIT(7));
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uint16_t phy_id2 = rt10xx_phy_read(d->phy_addr, PHY_ID1);
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uint16_t phy_id3 = rt10xx_phy_read(d->phy_addr, PHY_ID2);
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MG_INFO(("PHY ID: %#04x %#04x", phy_id2, phy_id3));
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// 2000 a140 - TI DP83825I
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// 0007 c0fx - LAN8720
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// 0022 1561 - KSZ8081RNB
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if (phy_id2 == 0x22) { // KSZ8081RNB, like EVK-RTxxxx boards
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rt10xx_phy_write(d->phy_addr, 31,
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MG_BIT(15) | MG_BIT(8) | MG_BIT(7)); // PC2R
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} else if (phy_id2 == 0x2000) { // DP83825I, like Teensy4.1
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rt10xx_phy_write(d->phy_addr, 23, 0x81); // 50Mhz clock input
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rt10xx_phy_write(d->phy_addr, 24, 0x280); // LED status, active high
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} else { // Default to LAN8720
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MG_INFO(("Defauling to LAN8720 PHY..."));
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}
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// Select RMII mode, 100M, keep CRC, set max rx length, disable loop
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ENET->RCR = (1518 << 16) | BIT(8) | BIT(2);
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// ENET->RCR |= BIT(3); // Receive all
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ENET->TCR = BIT(2); // Full-duplex
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ENET->RCR = (1518 << 16) | MG_BIT(8) | MG_BIT(2);
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// ENET->RCR |= MG_BIT(3); // Receive all
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ENET->TCR = MG_BIT(2); // Full-duplex
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ENET->RDSR = (uint32_t) (uintptr_t) s_rxdesc;
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ENET->TDSR = (uint32_t) (uintptr_t) s_txdesc;
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ENET->MRBR[0] = ETH_PKT_SIZE; // Same size for RX/TX buffers
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@@ -114,9 +128,9 @@ static bool mg_tcpip_driver_rt1020_init(struct mg_tcpip_if *ifp) {
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ENET->PALR = (uint32_t) (ifp->mac[0] << 24U) |
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((uint32_t) ifp->mac[1] << 16U) |
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((uint32_t) ifp->mac[2] << 8U) | ifp->mac[3];
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ENET->ECR = BIT(8) | BIT(1); // Little-endian CPU, Enable
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ENET->EIMR = BIT(25); // Set interrupt mask
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ENET->RDAR = BIT(24); // Receive Descriptors have changed
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ENET->ECR = MG_BIT(8) | MG_BIT(1); // Little-endian CPU, Enable
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ENET->EIMR = MG_BIT(25); // Set interrupt mask
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ENET->RDAR = MG_BIT(24); // Receive Descriptors have changed
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return true;
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}
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@@ -126,18 +140,20 @@ static uint32_t s_txno;
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static size_t mg_tcpip_driver_rt1020_tx(const void *buf, size_t len,
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struct mg_tcpip_if *ifp) {
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if (len > sizeof(s_txbuf[ETH_DESC_CNT])) {
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MG_ERROR(("Frame too big, %ld", (long) len));
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len = 0; // fail
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} else if ((s_txdesc[s_txno].control & BIT(15))) {
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ifp->nerr++;
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MG_ERROR(("Frame too big, %ld", (long) len));
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len = (size_t) -1; // fail
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} else if ((s_txdesc[s_txno].control & MG_BIT(15))) {
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MG_ERROR(("No descriptors available"));
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len = 0; // fail
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len = 0; // retry later
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} else {
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MG_DEBUG(("sending %lu bytes, desc %u", len, s_txno));
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno].length = (uint16_t) len; // Set data len
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// Table 37-34, R, L, TC (Ready, last, transmit CRC after frame
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s_txdesc[s_txno].control |= (uint16_t) (BIT(15) | BIT(11) | BIT(10));
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ENET->TDAR = BIT(24); // Descriptor ring updated
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s_txdesc[s_txno].control |=
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(uint16_t) (MG_BIT(15) | MG_BIT(11) | MG_BIT(10));
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ENET->TDAR |= MG_BIT(24); // Descriptor ring updated
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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(void) ifp;
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@@ -145,18 +161,22 @@ static size_t mg_tcpip_driver_rt1020_tx(const void *buf, size_t len,
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}
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static bool mg_tcpip_driver_rt1020_up(struct mg_tcpip_if *ifp) {
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uint32_t bsr = eth_read_phy(PHY_ADDR, PHY_BSR);
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bool up = bsr & BIT(2) ? 1 : 0;
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struct mg_tcpip_driver_rt1020_data *d =
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(struct mg_tcpip_driver_rt1020_data *) ifp->driver_data;
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uint32_t bsr = rt10xx_phy_read(d->phy_addr, PHY_BSR);
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bool up = bsr & MG_BIT(2) ? 1 : 0;
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if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up
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uint32_t pc1r = eth_read_phy(PHY_ADDR, PHY_PC1R);
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uint32_t tcr = ENET->TCR |= BIT(2); // Full-duplex
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uint32_t rcr = ENET->RCR &= ~BIT(9); // 100M
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if ((pc1r & 3) == 1) rcr |= BIT(9); // 10M
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if ((pc1r & BIT(2)) == 0) tcr &= ~BIT(2); // Half-duplex
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uint32_t tcr = ENET->TCR |= MG_BIT(2); // Full-duplex
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uint32_t rcr = ENET->RCR &= ~MG_BIT(9); // 100M
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if (rt10xx_phy_read(d->phy_addr, PHY_ID1)) { // KSZ8081RNB ?
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uint32_t pc1r = rt10xx_phy_read(d->phy_addr, 30); // Read PC2R
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if ((pc1r & 3) == 1) rcr |= MG_BIT(9); // 10M
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if ((pc1r & MG_BIT(2)) == 0) tcr &= ~MG_BIT(2); // Half-duplex
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}
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ENET->TCR = tcr; // IRQ handler does not fiddle with these registers
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ENET->RCR = rcr;
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MG_DEBUG(("Link is %uM %s-duplex", rcr & BIT(9) ? 10 : 100,
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tcr & BIT(2) ? "full" : "half"));
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MG_DEBUG(("Link is %uM %s-duplex", rcr & MG_BIT(9) ? 10 : 100,
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tcr & MG_BIT(2) ? "full" : "half"));
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}
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return up;
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}
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@@ -164,21 +184,21 @@ static bool mg_tcpip_driver_rt1020_up(struct mg_tcpip_if *ifp) {
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void ENET_IRQHandler(void);
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static uint32_t s_rxno;
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void ENET_IRQHandler(void) {
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ENET->EIR = BIT(25); // Ack IRQ
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ENET->EIR = MG_BIT(25); // Ack IRQ
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// Frame received, loop
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for (uint32_t i = 0; i < 10; i++) { // read as they arrive but not forever
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if (s_rxdesc[s_rxno].control & BIT(15)) break; // exit when done
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if (s_rxdesc[s_rxno].control & MG_BIT(15)) break; // exit when done
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// skip partial/errored frames (Table 37-32)
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if ((s_rxdesc[s_rxno].control & BIT(11)) &&
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if ((s_rxdesc[s_rxno].control & MG_BIT(11)) &&
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!(s_rxdesc[s_rxno].control &
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(BIT(5) | BIT(4) | BIT(2) | BIT(1) | BIT(0)))) {
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(MG_BIT(5) | MG_BIT(4) | MG_BIT(2) | MG_BIT(1) | MG_BIT(0)))) {
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uint32_t len = (s_rxdesc[s_rxno].length);
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mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp);
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}
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s_rxdesc[s_rxno].control |= BIT(15);
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s_rxdesc[s_rxno].control |= MG_BIT(15);
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if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
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}
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ENET->RDAR = BIT(24); // Receive Descriptors have changed
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ENET->RDAR = MG_BIT(24); // Receive Descriptors have changed
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// If b24 == 0, descriptors were exhausted and probably frames were dropped
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}
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@@ -11,6 +11,8 @@ struct mg_tcpip_driver_rt1020_data {
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// 33 MHz 6
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// 40 MHz 7
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// 50 MHz 9
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// 66 MHz 13
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// 66 MHz 13
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int mdc_cr; // Valid values: -1 to 63
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uint8_t phy_addr; // PHY address
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};
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+3
-16
@@ -17,19 +17,6 @@ struct stm32_eth {
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#undef ETH
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#define ETH ((struct stm32_eth *) (uintptr_t) 0x40028000)
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#undef DSB
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#if defined(__CC_ARM)
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#define DSB() __dsb(0xF)
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#elif defined(__ARMCC_VERSION)
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#define DSB() __builtin_arm_dsb(0xF)
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#elif defined(__GNUC__) && defined(__arm__) && defined(__thumb__)
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#define DSB() asm("DSB 0xF")
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#elif defined(__ICCARM__)
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#define DSB() __iar_builtin_DSB()
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#else
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#define DSB()
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#endif
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#undef BIT
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#define BIT(x) ((uint32_t) 1 << (x))
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#define ETH_PKT_SIZE 1540 // Max frame size
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@@ -177,13 +164,13 @@ static size_t mg_tcpip_driver_stm32_tx(const void *buf, size_t len,
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// printf("D0 %lx SR %lx\n", (long) s_txdesc[0][0], (long) ETH->DMASR);
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len = 0; // All descriptors are busy, fail
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} else {
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][1] = (uint32_t) len; // Set data len
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][1] = (uint32_t) len; // Set data len
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s_txdesc[s_txno][0] = BIT(20) | BIT(28) | BIT(29); // Chain,FS,LS
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s_txdesc[s_txno][0] |= BIT(31); // Set OWN bit - let DMA take over
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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DSB(); // ensure descriptors have been written
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MG_DSB(); // ensure descriptors have been written
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ETH->DMASR = BIT(2) | BIT(5); // Clear any prior TBUS/TUS
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ETH->DMATPDR = 0; // and resume
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return len;
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+18
-17
@@ -172,9 +172,6 @@ static void settmout(struct mg_connection *c, uint8_t type) {
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}
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static size_t ether_output(struct mg_tcpip_if *ifp, size_t len) {
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// size_t min = 64; // Pad short frames to 64 bytes (minimum Ethernet size)
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// if (len < min) memset(ifp->tx.ptr + len, 0, min - len), len = min;
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// mg_hexdump(ifp->tx.ptr, len);
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size_t n = ifp->driver->tx(ifp->tx.ptr, len, ifp);
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if (n == len) ifp->nsent++;
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return n;
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@@ -550,8 +547,8 @@ static struct mg_connection *accept_conn(struct mg_connection *lsn,
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static size_t trim_len(struct mg_connection *c, size_t len) {
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struct mg_tcpip_if *ifp = (struct mg_tcpip_if *) c->mgr->priv;
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size_t eth_h_len = 14, ip_max_h_len = 24, tcp_max_h_len = 60, udp_h_len = 8;
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size_t max_headers_len = eth_h_len + ip_max_h_len +
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(c->is_udp ? udp_h_len : tcp_max_h_len);
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size_t max_headers_len =
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eth_h_len + ip_max_h_len + (c->is_udp ? udp_h_len : tcp_max_h_len);
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size_t min_mtu = c->is_udp ? 68 /* RFC-791 */ : max_headers_len - eth_h_len;
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// If the frame exceeds the available buffer, trim the length
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@@ -578,18 +575,21 @@ static size_t trim_len(struct mg_connection *c, size_t len) {
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long mg_io_send(struct mg_connection *c, const void *buf, size_t len) {
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struct mg_tcpip_if *ifp = (struct mg_tcpip_if *) c->mgr->priv;
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struct connstate *s = (struct connstate *) (c + 1);
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uint32_t rem_ip;
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memcpy(&rem_ip, c->rem.ip, sizeof(uint32_t));
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uint32_t dst_ip = *(uint32_t *) c->rem.ip;
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len = trim_len(c, len);
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if (c->is_udp) {
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tx_udp(ifp, s->mac, ifp->ip, c->loc.port, rem_ip, c->rem.port, buf, len);
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tx_udp(ifp, s->mac, ifp->ip, c->loc.port, dst_ip, c->rem.port, buf, len);
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} else {
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if (tx_tcp(ifp, s->mac, rem_ip, TH_PUSH | TH_ACK, c->loc.port, c->rem.port,
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mg_htonl(s->seq), mg_htonl(s->ack), buf, len) > 0) {
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size_t sent =
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tx_tcp(ifp, s->mac, dst_ip, TH_PUSH | TH_ACK, c->loc.port, c->rem.port,
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mg_htonl(s->seq), mg_htonl(s->ack), buf, len);
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if (sent == 0) {
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return MG_IO_WAIT;
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} else if (sent == (size_t) -1) {
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return MG_IO_ERR;
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} else {
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s->seq += (uint32_t) len;
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if (s->ttype == MIP_TTYPE_ACK) settmout(c, MIP_TTYPE_KEEPALIVE);
|
||||
} else {
|
||||
return MG_IO_ERR;
|
||||
}
|
||||
}
|
||||
return (long) len;
|
||||
@@ -744,12 +744,11 @@ static void rx_tcp(struct mg_tcpip_if *ifp, struct pkt *pkt) {
|
||||
}
|
||||
|
||||
static void rx_ip(struct mg_tcpip_if *ifp, struct pkt *pkt) {
|
||||
if (pkt->ip->frag & IP_MORE_FRAGS_MSK ||
|
||||
pkt->ip->frag & IP_FRAG_OFFSET_MSK) {
|
||||
if (pkt->ip->frag & IP_MORE_FRAGS_MSK || pkt->ip->frag & IP_FRAG_OFFSET_MSK) {
|
||||
if (pkt->ip->proto == 17) pkt->udp = (struct udp *) (pkt->ip + 1);
|
||||
if (pkt->ip->proto == 6) pkt->tcp = (struct tcp *) (pkt->ip + 1);
|
||||
struct mg_connection *c = getpeer(ifp->mgr, pkt, false);
|
||||
if (c) mg_error(c, "Received fragmented packet");
|
||||
if (c) mg_error(c, "Received fragmented packet");
|
||||
} else if (pkt->ip->proto == 1) {
|
||||
pkt->icmp = (struct icmp *) (pkt->ip + 1);
|
||||
if (pkt->pay.len < sizeof(*pkt->icmp)) return;
|
||||
@@ -1039,7 +1038,9 @@ bool mg_open_listener(struct mg_connection *c, const char *url) {
|
||||
static void write_conn(struct mg_connection *c) {
|
||||
long len = c->is_tls ? mg_tls_send(c, c->send.buf, c->send.len)
|
||||
: mg_io_send(c, c->send.buf, c->send.len);
|
||||
if (len > 0) {
|
||||
if (len == MG_IO_ERR) {
|
||||
mg_error(c, "tx err");
|
||||
} else if (len > 0) {
|
||||
mg_iobuf_del(&c->send, 0, (size_t) len);
|
||||
mg_call(c, MG_EV_WRITE, &len);
|
||||
}
|
||||
@@ -1100,7 +1101,7 @@ bool mg_send(struct mg_connection *c, const void *buf, size_t len) {
|
||||
mg_error(c, "net down");
|
||||
} else if (c->is_udp) {
|
||||
struct connstate *s = (struct connstate *) (c + 1);
|
||||
len = trim_len(c, len); // Trimming length if necessary
|
||||
len = trim_len(c, len); // Trimming length if necessary
|
||||
tx_udp(ifp, s->mac, ifp->ip, c->loc.port, rem_ip, c->rem.port, buf, len);
|
||||
res = true;
|
||||
} else {
|
||||
|
||||
+12
@@ -47,6 +47,18 @@ uint64_t mg_now(void); // Return milliseconds since Epoch
|
||||
#define MG_ARM_ENABLE_IRQ()
|
||||
#endif
|
||||
|
||||
#if defined(__CC_ARM)
|
||||
#define MG_DSB() __dsb(0xf)
|
||||
#elif defined(__ARMCC_VERSION)
|
||||
#define MG_DSB() __builtin_arm_dsb(0xf)
|
||||
#elif defined(__GNUC__) && defined(__arm__) && defined(__thumb__)
|
||||
#define MG_DSB() asm("DSB 0xf")
|
||||
#elif defined(__ICCARM__)
|
||||
#define MG_DSB() __iar_builtin_DSB()
|
||||
#else
|
||||
#define MG_DSB()
|
||||
#endif
|
||||
|
||||
struct mg_addr;
|
||||
int mg_check_ip_acl(struct mg_str acl, struct mg_addr *remote_ip);
|
||||
|
||||
|
||||
Reference in new issue
Block a user