wt/mongoose
1
0 Fork 0
mirror of https://github.com/cesanta/mongoose.git synced 2026-10-26 12:14:56 +00:00
Code Issues Packages Projects Releases Wiki Activity

OTA rollback nits

Browse Source
This commit is contained in:
cpq committed 2026-06-13 19:41:13 +01:00
1 parent b5b6d9c8da
commit c0723249b4
13 files changed
+507 -226
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

tutorials/stm32/nucleo-h563zi/minimal/main.c
+3 -5
View File
@@ -73,18 +73,16 @@ int main(void) {
hal_clock_init();
hal_uart_init(UART_DEBUG, UART_DEBUG_TX_PIN, UART_DEBUG_RX_PIN, 115200);
mg_log_set_fn(log_fn, UART_DEBUG);
MG_OTA_BOOT_CHECK(); // Must be called after clock init
hal_rng_init();
hal_gpio_output(LED_1);
hal_gpio_output(LED_2);
hal_gpio_output(LED_3);
hal_ethernet_init();
MG_INFO(("Initialised. CPU clock: %lu MHz", SystemCoreClock / 1000000));
// Max delay 131 seconds
MG_OTA_BOOT_CHECK(30);
struct mg_mgr mgr;
mg_mgr_init(&mgr);
mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL);
tutorials/stm32/nucleo-h563zi/minimal/mongoose/mongoose_config.h
+6 -4
View File
@@ -24,18 +24,20 @@
}
// OTA rollback timer via IWDG. PR=8 → /1024 on H563 (RM0481 §52.4.2).
// Max timeout: 4095 * 1024 / 32000 = 131 s. PVU/RVU must clear before
// writing RLR/starting, otherwise the write is ignored (RM0481 §52.4.3).
#define MG_OTA_ROLLBACK_TIMER_START(seconds) \
// Fixed 10 s hang-detection window: RLR = 10 * 32000 / 1024 = 312.
// PVU/RVU must clear before writing RLR/starting (RM0481 §52.4.3).
// mg_ota_poll() feeds the watchdog every 500ms while in MG_OTA_TESTING state.
#define MG_OTA_ROLLBACK_TIMER_START() \
do { \
IWDG->KR = 0x5555U; /* unlock */ \
IWDG->PR = 8U; /* /1024 */ \
while (IWDG->SR & IWDG_SR_PVU) (void) 0; /* wait PVU */ \
IWDG->RLR = (uint32_t) ((seconds) * 32000 / 1024); \
IWDG->RLR = 312U; /* 10 s */ \
while (IWDG->SR & IWDG_SR_RVU) (void) 0; /* wait RVU */ \
IWDG->KR = 0xCCCCU; /* start */ \
IWDG->KR = 0xAAAAU; /* reload RLR */ \
} while (0)
#define MG_OTA_ROLLBACK_TIMER_FEED() (IWDG->KR = 0xAAAAU)
// OTA state in TAMP backup register 0 (survives all resets, clears on POR).
// Requires hal_backup_domain_init() (called from hal_clock_init) to have run.
tutorials/stm32/nucleo-h723zg/minimal/main.c
+1 -2
View File
@@ -80,8 +80,7 @@ int main(void) {
MG_INFO(("Initialised. CPU clock: %lu MHz", SystemCoreClock / 1000000));
// Max delay 65 seconds
MG_OTA_BOOT_CHECK(30);
MG_OTA_BOOT_CHECK(); // Must be called after clock init
struct mg_mgr mgr;
mg_mgr_init(&mgr);
tutorials/stm32/nucleo-h723zg/minimal/mongoose/mongoose_config.h
+5 -3
View File
@@ -24,18 +24,20 @@
// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0) // Netmask
// OTA rollback timer via IWDG1. PR=7 → /512 on H723 (RM0468 §54.4.2).
// Max timeout: 4095 * 512 / 32000 = 65 s.
// Fixed 10 s hang-detection window: RLR = 10 * 32000 / 512 = 625.
// RM0468 §54.4 sequence: 0xCCCC first (starts LSI), then 0x5555 to unlock,
// write PR+RLR, wait SR=0 (PVU|RVU), then 0xAAAA to reload the counter.
#define MG_OTA_ROLLBACK_TIMER_START(seconds) \
// mg_ota_poll() feeds the watchdog every 500ms while in MG_OTA_TESTING state.
#define MG_OTA_ROLLBACK_TIMER_START() \
do { \
IWDG1->KR = 0xCCCCU; /* start/LSI */ \
IWDG1->KR = 0x5555U; /* unlock */ \
IWDG1->PR = 7U; /* /512 */ \
IWDG1->RLR = (uint32_t) ((seconds) * 32000 / 512); \
IWDG1->RLR = 625U; /* 10 s */ \
while (IWDG1->SR & (IWDG_SR_PVU | IWDG_SR_RVU)) (void) 0; /* wait SR=0 */ \
IWDG1->KR = 0xAAAAU; /* reload */ \
} while (0)
#define MG_OTA_ROLLBACK_TIMER_FEED() (IWDG1->KR = 0xAAAAU)
// OTA state in RTC backup register 0 (survives all resets, clears on POR).
// Requires hal_backup_domain_init() (called from hal_clock_init) to have run.