From c775f31ca7fb456b729acb95f4555a3d9120d2ae Mon Sep 17 00:00:00 2001 From: cpq Date: Tue, 20 Oct 2026 21:22:14 +0100 Subject: [PATCH] Add nucleo-c5a3zg --- mongoose.c | 12 +- mongoose.h | 87 +- src/arch_cube.h | 69 +- src/drivers/stm32h.c | 9 +- src/drivers/stm32h.h | 13 +- src/health.c | 2 +- src/health.h | 4 +- src/ota.h | 1 + src/ota_stm32h5.c | 2 +- .../stm32/nucleo-c5a3zg/cubemx/README.md | 9 + .../nucleo-c5a3zg/cubemx/nucleo-c5a3zg.ioc2 | 3855 +++++++++++++++++ .../stm32/nucleo-c5a3zg/minimal/Makefile | 46 + tutorials/stm32/nucleo-c5a3zg/minimal/hal.c | 141 + tutorials/stm32/nucleo-c5a3zg/minimal/hal.h | 165 + tutorials/stm32/nucleo-c5a3zg/minimal/link.ld | 37 + tutorials/stm32/nucleo-c5a3zg/minimal/main.c | 110 + .../nucleo-c5a3zg/minimal/mongoose_config.h | 32 + 17 files changed, 4448 insertions(+), 146 deletions(-) create mode 100644 tutorials/stm32/nucleo-c5a3zg/cubemx/README.md create mode 100644 tutorials/stm32/nucleo-c5a3zg/cubemx/nucleo-c5a3zg.ioc2 create mode 100644 tutorials/stm32/nucleo-c5a3zg/minimal/Makefile create mode 100644 tutorials/stm32/nucleo-c5a3zg/minimal/hal.c create mode 100644 tutorials/stm32/nucleo-c5a3zg/minimal/hal.h create mode 100644 tutorials/stm32/nucleo-c5a3zg/minimal/link.ld create mode 100644 tutorials/stm32/nucleo-c5a3zg/minimal/main.c create mode 100644 tutorials/stm32/nucleo-c5a3zg/minimal/mongoose_config.h diff --git a/mongoose.c b/mongoose.c index 3b0f1d13..bc159c28 100644 --- a/mongoose.c +++ b/mongoose.c @@ -3646,7 +3646,7 @@ struct mg_fs mg_fs_posix = {p_stat, p_list, p_open, p_close, p_read, struct mg_health mg_health_record MG_HEALTH_RAM; // STM32 H723 support. Needs the _estack symbol from the linker script -#if MG_ENABLE_HEALTH && (defined(STM32H7_DEV_ID) || defined(STM32H5)) +#if MG_ENABLE_HEALTH && (defined(STM32H7_DEV_ID) || defined(STM32H5) || defined(STM32C5)) // Fault handler body. Runs in exception context: no printf, no malloc, no // blocking calls. Copies the unwind registers and raw stack into the health // record, then resets. @@ -13275,7 +13275,7 @@ struct mg_flash *mg_flash = &s_mg_flash_stm32f; -#if MG_OTA == MG_OTA_STM32H5 +#if MG_OTA == MG_OTA_STM32H5 || MG_OTA == MG_OTA_STM32C5 static bool mg_stm32h5_write(void *, const void *, size_t); static bool mg_stm32h5_swap(void); @@ -34396,7 +34396,7 @@ static uint32_t s_rxno; #if MG_ENABLE_DRIVER_MCXN void ETHERNET_IRQHandler(void); void ETHERNET_IRQHandler(void) { -#elif MG_ENABLE_DRIVER_STM32H +#elif MG_ENABLE_DRIVER_STM32H && !MG_ENABLE_DRIVER_STM32C void ETH_IRQHandler(void); void ETH_IRQHandler(void) { #else @@ -34425,8 +34425,10 @@ void ETH1_IRQHandler(void) { } ETH->DMACSR = MG_BIT(7) | MG_BIT(8); // Clear possible RBU RPS while processing - ETH->DMACRDTPR = - (uint32_t) (uintptr_t) &s_rxdesc[ETH_DESC_CNT - 1]; // and resume RX + // Resume RX: tail is the last descriptor given back to DMA. It must differ + // from the DMA current descriptor, or some DMAs, e.g. STM32C5, stay suspended + ETH->DMACRDTPR = (uint32_t) (uintptr_t) &s_rxdesc[(s_rxno + ETH_DESC_CNT - 1) % + ETH_DESC_CNT]; } struct mg_tcpip_driver mg_tcpip_driver_stm32h = { diff --git a/mongoose.h b/mongoose.h index 251aaa20..1237c0d5 100644 --- a/mongoose.h +++ b/mongoose.h @@ -165,6 +165,7 @@ extern "C" { #if MG_ENABLE_TCPIP && !defined(MG_ENABLE_DRIVER_STM32F) && \ !defined(MG_ENABLE_DRIVER_STM32H) && !defined(MG_ENABLE_DRIVER_STM32N) && \ + !defined(MG_ENABLE_DRIVER_STM32C) && \ !defined(MG_ENABLE_DRIVER_CYW) && !defined(MG_ENABLE_DRIVER_CYW_SDIO) && \ !defined(MG_ENABLE_DRIVER_ST67W6) #if defined(STM32F1) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) @@ -173,6 +174,8 @@ extern "C" { #define MG_ENABLE_DRIVER_STM32H 1 #elif defined(STM32N6) #define MG_ENABLE_DRIVER_STM32N 1 +#elif defined(STM32C5) +#define MG_ENABLE_DRIVER_STM32C 1 #else #error Select a driver in mongoose_config.h #endif @@ -189,70 +192,8 @@ extern "C" { #define MG_OTA MG_OTA_STM32H5 #elif !defined(MG_OTA) && defined(STM32H7) #define MG_OTA MG_OTA_STM32H7 -#endif - -// OTA rollback timer via IWDG. Fixed 10 s hang-detection window (prescaler -// /1024, LSI ~32 kHz: reload = 10 * 32000 / 1024 = 312). mg_ota_poll() feeds -// the watchdog every 500 ms while in MG_OTA_TESTING state; if the event loop -// hangs for 10 s, the IWDG fires and the device rolls back. -// STM32H7 names the peripheral IWDG1; all others use IWDG. -// The total evaluation period is set by MG_OTA_ROLLBACK_TIMEOUT_SECONDS. -// STM32H7 names the watchdog peripheral IWDG1; all other families use IWDG. -#if defined(IWDG1) && !defined(IWDG) -#define MG_IWDG IWDG1 -#else -#define MG_IWDG IWDG -#endif -// PR=6 → /256 prescaler, RLR=1250 → ~10 s at LSI 32 kHz. -// Works on F4/F7/H5/H7; uses direct register writes so it is safe before HAL_Init(). -#ifndef MG_OTA_ROLLBACK_TIMER_START -#define MG_OTA_ROLLBACK_TIMER_START() \ - do { \ - MG_IWDG->KR = 0xCCCCU; /* start + LSI */ \ - MG_IWDG->KR = 0x5555U; /* unlock PR/RLR */ \ - MG_IWDG->PR = 6U; /* /256 */ \ - MG_IWDG->RLR = 1250U; /* 10 s */ \ - while (MG_IWDG->SR & (IWDG_SR_PVU | IWDG_SR_RVU)) (void) 0; \ - MG_IWDG->KR = 0xAAAAU; /* reload */ \ - } while (0) -#endif - -// Feed (reload) the IWDG. Called from mg_ota_poll() every 500 ms. -#ifndef MG_OTA_ROLLBACK_TIMER_FEED -#define MG_OTA_ROLLBACK_TIMER_FEED() (MG_IWDG->KR = 0xAAAAU) -#endif - -// OTA state in a backup register that survives warm resets but clears on POR. -// STATE_GET reads work without any setup. STATE_SET enables the RTC APB clock -// and unlocks backup domain write access via direct register writes, so it is -// safe to call from any context (before or after HAL_Init). -// H5 (TAMP->BKP0R), H7 (RTC->BKP0R), F4/F7 (RTC->BKP0R). -#ifndef MG_OTA_STATE_GET -#if defined(PWR_DBPCR_DBP) -#define MG_OTA_DBP_ENABLE() (PWR->DBPCR |= PWR_DBPCR_DBP) -#elif defined(PWR_CR1_DBP) -#define MG_OTA_DBP_ENABLE() (PWR->CR1 |= PWR_CR1_DBP) -#else -#define MG_OTA_DBP_ENABLE() (PWR->CR |= PWR_CR_DBP) -#endif - -#if defined(TAMP) -#define MG_OTA_STATE_GET() \ - (RCC->APB3ENR |= RCC_APB3ENR_RTCAPBEN, TAMP->BKP0R) -#define MG_OTA_STATE_SET(v) \ - (RCC->APB3ENR |= RCC_APB3ENR_RTCAPBEN, MG_OTA_DBP_ENABLE(), \ - (TAMP->BKP0R = (uint32_t) (v)), TAMP->BKP0R) -#elif defined(RCC_APB4ENR_RTCAPBEN) -#define MG_OTA_STATE_GET() (RTC->BKP0R) -#define MG_OTA_STATE_SET(v) \ - (RCC->APB4ENR |= RCC_APB4ENR_RTCAPBEN, MG_OTA_DBP_ENABLE(), \ - (RTC->BKP0R = (uint32_t) (v))) -#else -#define MG_OTA_STATE_GET() (RTC->BKP0R) -#define MG_OTA_STATE_SET(v) \ - (RCC->APB1ENR |= RCC_APB1ENR_PWREN, MG_OTA_DBP_ENABLE(), \ - (RTC->BKP0R = (uint32_t) (v))) -#endif +#elif !defined(MG_OTA) && defined(STM32C5) +#define MG_OTA MG_OTA_STM32C5 #endif // use HAL-defined execute-in-ram section @@ -4233,6 +4174,7 @@ extern void mg_mqtt_poll(struct mg_mgr *); #define MG_OTA_STM32H7 2 // STM32 H7 #define MG_OTA_STM32H7_DUAL_CORE 3 // STM32 H7 dual core #define MG_OTA_STM32F 4 // STM32 F7/F4/F2 +#define MG_OTA_STM32C5 5 // STM32 C5, same flash controller as H5 #define MG_OTA_CH32V307 100 // WCH CH32V307 #define MG_OTA_U2A 200 // Renesas U2A16, U2A8, U2A6 #define MG_OTA_RT1020 300 // IMXRT1020 @@ -4418,11 +4360,11 @@ void mg_ota_poll(struct mg_mgr *); #define MG_HEALTH_MAGIC {'M', 'G', 'H', '3'} // '3' is the layout version #endif -#if !defined(MG_HEALTH_RAM) && (defined(STM32H7_DEV_ID) || defined(STM32H5)) +#if !defined(MG_HEALTH_RAM) && (defined(STM32H7_DEV_ID) || defined(STM32H5) || defined(STM32C5)) #define MG_HEALTH_RAM __attribute__((section(".mg_health"))) #endif -#if !defined(MG_HEALTH_DATA_SIZE) && (defined(STM32H7_DEV_ID) || defined(STM32H5)) +#if !defined(MG_HEALTH_DATA_SIZE) && (defined(STM32H7_DEV_ID) || defined(STM32H5) || defined(STM32C5)) #define MG_HEALTH_DATA_SIZE 250 #endif @@ -5555,6 +5497,13 @@ struct mg_tcpip_driver_stm32f_data { #if !defined(MG_ENABLE_DRIVER_STM32H) #define MG_ENABLE_DRIVER_STM32H 0 #endif +#if !defined(MG_ENABLE_DRIVER_STM32C) +#define MG_ENABLE_DRIVER_STM32C 0 +#endif +#if MG_ENABLE_DRIVER_STM32C // STM32C5: STM32H5 MAC, the IRQ is ETH1 +#undef MG_ENABLE_DRIVER_STM32H +#define MG_ENABLE_DRIVER_STM32H 1 +#endif #if !defined(MG_ENABLE_DRIVER_MCXN) #define MG_ENABLE_DRIVER_MCXN 0 #endif @@ -5594,9 +5543,11 @@ struct mg_tcpip_driver_stm32h_data { #define MG_DRIVER_MDC_CR 4 #endif -#if MG_ENABLE_DRIVER_STM32H && MG_ARCH == MG_ARCH_CUBE && !defined(MG_ENABLE_ETH_IRQ) +#if MG_ENABLE_DRIVER_STM32H && !MG_ENABLE_DRIVER_STM32C && \ + MG_ARCH == MG_ARCH_CUBE && !defined(MG_ENABLE_ETH_IRQ) #define MG_ENABLE_ETH_IRQ() NVIC_EnableIRQ(ETH_IRQn) -#elif MG_ENABLE_DRIVER_STM32N && MG_ARCH == MG_ARCH_CUBE && !defined(MG_ENABLE_ETH_IRQ) +#elif (MG_ENABLE_DRIVER_STM32N || MG_ENABLE_DRIVER_STM32C) && \ + MG_ARCH == MG_ARCH_CUBE && !defined(MG_ENABLE_ETH_IRQ) #define MG_ENABLE_ETH_IRQ() NVIC_EnableIRQ(ETH1_IRQn) #elif !defined(MG_ENABLE_ETH_IRQ) #define MG_ENABLE_ETH_IRQ() diff --git a/src/arch_cube.h b/src/arch_cube.h index 6a69701e..a49c6cb9 100644 --- a/src/arch_cube.h +++ b/src/arch_cube.h @@ -32,6 +32,7 @@ #if MG_ENABLE_TCPIP && !defined(MG_ENABLE_DRIVER_STM32F) && \ !defined(MG_ENABLE_DRIVER_STM32H) && !defined(MG_ENABLE_DRIVER_STM32N) && \ + !defined(MG_ENABLE_DRIVER_STM32C) && \ !defined(MG_ENABLE_DRIVER_CYW) && !defined(MG_ENABLE_DRIVER_CYW_SDIO) && \ !defined(MG_ENABLE_DRIVER_ST67W6) #if defined(STM32F1) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) @@ -40,6 +41,8 @@ #define MG_ENABLE_DRIVER_STM32H 1 #elif defined(STM32N6) #define MG_ENABLE_DRIVER_STM32N 1 +#elif defined(STM32C5) +#define MG_ENABLE_DRIVER_STM32C 1 #else #error Select a driver in mongoose_config.h #endif @@ -56,70 +59,8 @@ #define MG_OTA MG_OTA_STM32H5 #elif !defined(MG_OTA) && defined(STM32H7) #define MG_OTA MG_OTA_STM32H7 -#endif - -// OTA rollback timer via IWDG. Fixed 10 s hang-detection window (prescaler -// /1024, LSI ~32 kHz: reload = 10 * 32000 / 1024 = 312). mg_ota_poll() feeds -// the watchdog every 500 ms while in MG_OTA_TESTING state; if the event loop -// hangs for 10 s, the IWDG fires and the device rolls back. -// STM32H7 names the peripheral IWDG1; all others use IWDG. -// The total evaluation period is set by MG_OTA_ROLLBACK_TIMEOUT_SECONDS. -// STM32H7 names the watchdog peripheral IWDG1; all other families use IWDG. -#if defined(IWDG1) && !defined(IWDG) -#define MG_IWDG IWDG1 -#else -#define MG_IWDG IWDG -#endif -// PR=6 → /256 prescaler, RLR=1250 → ~10 s at LSI 32 kHz. -// Works on F4/F7/H5/H7; uses direct register writes so it is safe before HAL_Init(). -#ifndef MG_OTA_ROLLBACK_TIMER_START -#define MG_OTA_ROLLBACK_TIMER_START() \ - do { \ - MG_IWDG->KR = 0xCCCCU; /* start + LSI */ \ - MG_IWDG->KR = 0x5555U; /* unlock PR/RLR */ \ - MG_IWDG->PR = 6U; /* /256 */ \ - MG_IWDG->RLR = 1250U; /* 10 s */ \ - while (MG_IWDG->SR & (IWDG_SR_PVU | IWDG_SR_RVU)) (void) 0; \ - MG_IWDG->KR = 0xAAAAU; /* reload */ \ - } while (0) -#endif - -// Feed (reload) the IWDG. Called from mg_ota_poll() every 500 ms. -#ifndef MG_OTA_ROLLBACK_TIMER_FEED -#define MG_OTA_ROLLBACK_TIMER_FEED() (MG_IWDG->KR = 0xAAAAU) -#endif - -// OTA state in a backup register that survives warm resets but clears on POR. -// STATE_GET reads work without any setup. STATE_SET enables the RTC APB clock -// and unlocks backup domain write access via direct register writes, so it is -// safe to call from any context (before or after HAL_Init). -// H5 (TAMP->BKP0R), H7 (RTC->BKP0R), F4/F7 (RTC->BKP0R). -#ifndef MG_OTA_STATE_GET -#if defined(PWR_DBPCR_DBP) -#define MG_OTA_DBP_ENABLE() (PWR->DBPCR |= PWR_DBPCR_DBP) -#elif defined(PWR_CR1_DBP) -#define MG_OTA_DBP_ENABLE() (PWR->CR1 |= PWR_CR1_DBP) -#else -#define MG_OTA_DBP_ENABLE() (PWR->CR |= PWR_CR_DBP) -#endif - -#if defined(TAMP) -#define MG_OTA_STATE_GET() \ - (RCC->APB3ENR |= RCC_APB3ENR_RTCAPBEN, TAMP->BKP0R) -#define MG_OTA_STATE_SET(v) \ - (RCC->APB3ENR |= RCC_APB3ENR_RTCAPBEN, MG_OTA_DBP_ENABLE(), \ - (TAMP->BKP0R = (uint32_t) (v)), TAMP->BKP0R) -#elif defined(RCC_APB4ENR_RTCAPBEN) -#define MG_OTA_STATE_GET() (RTC->BKP0R) -#define MG_OTA_STATE_SET(v) \ - (RCC->APB4ENR |= RCC_APB4ENR_RTCAPBEN, MG_OTA_DBP_ENABLE(), \ - (RTC->BKP0R = (uint32_t) (v))) -#else -#define MG_OTA_STATE_GET() (RTC->BKP0R) -#define MG_OTA_STATE_SET(v) \ - (RCC->APB1ENR |= RCC_APB1ENR_PWREN, MG_OTA_DBP_ENABLE(), \ - (RTC->BKP0R = (uint32_t) (v))) -#endif +#elif !defined(MG_OTA) && defined(STM32C5) +#define MG_OTA MG_OTA_STM32C5 #endif // use HAL-defined execute-in-ram section diff --git a/src/drivers/stm32h.c b/src/drivers/stm32h.c index f5f28399..72a2297f 100644 --- a/src/drivers/stm32h.c +++ b/src/drivers/stm32h.c @@ -2,6 +2,7 @@ #if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN || \ MG_ENABLE_DRIVER_STM32N) +// STM32C: vendor modded single-queue Synopsys v5.4, same settings as STM32H // STM32H: vendor modded single-queue Synopsys v4.2 // STM32N: dual-queue GbE Synopsys v5.2 with no hash table option, 64-bit AXI // MCXNx4x: dual-queue Synopsys v5.2 with no hash table option @@ -310,7 +311,7 @@ static uint32_t s_rxno; #if MG_ENABLE_DRIVER_MCXN void ETHERNET_IRQHandler(void); void ETHERNET_IRQHandler(void) { -#elif MG_ENABLE_DRIVER_STM32H +#elif MG_ENABLE_DRIVER_STM32H && !MG_ENABLE_DRIVER_STM32C void ETH_IRQHandler(void); void ETH_IRQHandler(void) { #else @@ -339,8 +340,10 @@ void ETH1_IRQHandler(void) { } ETH->DMACSR = MG_BIT(7) | MG_BIT(8); // Clear possible RBU RPS while processing - ETH->DMACRDTPR = - (uint32_t) (uintptr_t) &s_rxdesc[ETH_DESC_CNT - 1]; // and resume RX + // Resume RX: tail is the last descriptor given back to DMA. It must differ + // from the DMA current descriptor, or some DMAs, e.g. STM32C5, stay suspended + ETH->DMACRDTPR = (uint32_t) (uintptr_t) &s_rxdesc[(s_rxno + ETH_DESC_CNT - 1) % + ETH_DESC_CNT]; } struct mg_tcpip_driver mg_tcpip_driver_stm32h = { diff --git a/src/drivers/stm32h.h b/src/drivers/stm32h.h index 7dd5eea7..834d5377 100644 --- a/src/drivers/stm32h.h +++ b/src/drivers/stm32h.h @@ -4,6 +4,13 @@ #if !defined(MG_ENABLE_DRIVER_STM32H) #define MG_ENABLE_DRIVER_STM32H 0 #endif +#if !defined(MG_ENABLE_DRIVER_STM32C) +#define MG_ENABLE_DRIVER_STM32C 0 +#endif +#if MG_ENABLE_DRIVER_STM32C // STM32C5: STM32H5 MAC, the IRQ is ETH1 +#undef MG_ENABLE_DRIVER_STM32H +#define MG_ENABLE_DRIVER_STM32H 1 +#endif #if !defined(MG_ENABLE_DRIVER_MCXN) #define MG_ENABLE_DRIVER_MCXN 0 #endif @@ -43,9 +50,11 @@ struct mg_tcpip_driver_stm32h_data { #define MG_DRIVER_MDC_CR 4 #endif -#if MG_ENABLE_DRIVER_STM32H && MG_ARCH == MG_ARCH_CUBE && !defined(MG_ENABLE_ETH_IRQ) +#if MG_ENABLE_DRIVER_STM32H && !MG_ENABLE_DRIVER_STM32C && \ + MG_ARCH == MG_ARCH_CUBE && !defined(MG_ENABLE_ETH_IRQ) #define MG_ENABLE_ETH_IRQ() NVIC_EnableIRQ(ETH_IRQn) -#elif MG_ENABLE_DRIVER_STM32N && MG_ARCH == MG_ARCH_CUBE && !defined(MG_ENABLE_ETH_IRQ) +#elif (MG_ENABLE_DRIVER_STM32N || MG_ENABLE_DRIVER_STM32C) && \ + MG_ARCH == MG_ARCH_CUBE && !defined(MG_ENABLE_ETH_IRQ) #define MG_ENABLE_ETH_IRQ() NVIC_EnableIRQ(ETH1_IRQn) #elif !defined(MG_ENABLE_ETH_IRQ) #define MG_ENABLE_ETH_IRQ() diff --git a/src/health.c b/src/health.c index d1b7fbd2..566e79eb 100644 --- a/src/health.c +++ b/src/health.c @@ -6,7 +6,7 @@ struct mg_health mg_health_record MG_HEALTH_RAM; // STM32 H723 support. Needs the _estack symbol from the linker script -#if MG_ENABLE_HEALTH && (defined(STM32H7_DEV_ID) || defined(STM32H5)) +#if MG_ENABLE_HEALTH && (defined(STM32H7_DEV_ID) || defined(STM32H5) || defined(STM32C5)) // Fault handler body. Runs in exception context: no printf, no malloc, no // blocking calls. Copies the unwind registers and raw stack into the health // record, then resets. diff --git a/src/health.h b/src/health.h index 3304732f..67ba3fab 100644 --- a/src/health.h +++ b/src/health.h @@ -9,11 +9,11 @@ #define MG_HEALTH_MAGIC {'M', 'G', 'H', '3'} // '3' is the layout version #endif -#if !defined(MG_HEALTH_RAM) && (defined(STM32H7_DEV_ID) || defined(STM32H5)) +#if !defined(MG_HEALTH_RAM) && (defined(STM32H7_DEV_ID) || defined(STM32H5) || defined(STM32C5)) #define MG_HEALTH_RAM __attribute__((section(".mg_health"))) #endif -#if !defined(MG_HEALTH_DATA_SIZE) && (defined(STM32H7_DEV_ID) || defined(STM32H5)) +#if !defined(MG_HEALTH_DATA_SIZE) && (defined(STM32H7_DEV_ID) || defined(STM32H5) || defined(STM32C5)) #define MG_HEALTH_DATA_SIZE 250 #endif diff --git a/src/ota.h b/src/ota.h index 27359930..a54f40ca 100644 --- a/src/ota.h +++ b/src/ota.h @@ -34,6 +34,7 @@ #define MG_OTA_STM32H7 2 // STM32 H7 #define MG_OTA_STM32H7_DUAL_CORE 3 // STM32 H7 dual core #define MG_OTA_STM32F 4 // STM32 F7/F4/F2 +#define MG_OTA_STM32C5 5 // STM32 C5, same flash controller as H5 #define MG_OTA_CH32V307 100 // WCH CH32V307 #define MG_OTA_U2A 200 // Renesas U2A16, U2A8, U2A6 #define MG_OTA_RT1020 300 // IMXRT1020 diff --git a/src/ota_stm32h5.c b/src/ota_stm32h5.c index 0ad3dcab..f6ad9e1e 100644 --- a/src/ota_stm32h5.c +++ b/src/ota_stm32h5.c @@ -2,7 +2,7 @@ #include "log.h" #include "ota.h" -#if MG_OTA == MG_OTA_STM32H5 +#if MG_OTA == MG_OTA_STM32H5 || MG_OTA == MG_OTA_STM32C5 static bool mg_stm32h5_write(void *, const void *, size_t); static bool mg_stm32h5_swap(void); diff --git a/tutorials/stm32/nucleo-c5a3zg/cubemx/README.md b/tutorials/stm32/nucleo-c5a3zg/cubemx/README.md new file mode 100644 index 00000000..f887b8bf --- /dev/null +++ b/tutorials/stm32/nucleo-c5a3zg/cubemx/README.md @@ -0,0 +1,9 @@ +# Nucleo-C5A3ZI Mongoose Integration + +The `.ioc2` file in this directory is pre-configured. Note that after the +project generation, you should do the following to complete integraion: + +1. Edit the linker script `.ld` file and increase heap and stack sizes to + 0x20000 and 0x4000 respectively +2. Add Mongoose to the `main.c`, see https://mongoose.ws/docs/guides/stm32-tcpip-stack/#modify-mainc + diff --git a/tutorials/stm32/nucleo-c5a3zg/cubemx/nucleo-c5a3zg.ioc2 b/tutorials/stm32/nucleo-c5a3zg/cubemx/nucleo-c5a3zg.ioc2 new file mode 100644 index 00000000..9ad48561 --- /dev/null +++ b/tutorials/stm32/nucleo-c5a3zg/cubemx/nucleo-c5a3zg.ioc2 @@ -0,0 +1,3855 @@ +"File: .settings/application-project.store.json" = """ +{ + "cube.application-project": {} +}""" +"File: .settings/clock.store.json" = """ +{ + "userSettings": [ + { + "id": "LSE", + "value": 32768, + "isLocked": false, + "outFrequency": 32768 + }, + { + "id": "LSI", + "value": 32000, + "isLocked": false, + "outFrequency": 32000 + }, + { + "id": "HSE", + "value": 8000000, + "isLocked": false, + "outFrequency": 8000000 + }, + { + "id": "HSI", + "value": "144000000", + "isLocked": false, + "outFrequency": 144000000 + }, + { + "id": "HSE_Divider_RTC", + "value": 1, + "isLocked": false, + "outFrequency": 8000000 + }, + { + "id": "RTC_Clock_Source", + "value": "LSI_inputid", + "isLocked": false, + "outFrequency": 32000 + }, + { + "id": "RTC_Input_Clock", + "value": 32000, + "isLocked": false, + "outFrequency": 32000 + }, + { + "id": "IWDG_Input_Clock", + "value": 32000, + "isLocked": false, + "outFrequency": 32000 + }, + { + "id": "MCO1_Clock_Source", + "value": "System_Clock_Frequency_inputid", + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "MCO1_div_Clock", + "value": 1, + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "MCO1_Input_Source", + "value": 100000000, + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "MCO2_Clock_Source", + "value": "System_Clock_Frequency_inputid", + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "MCO2_div_Clock", + "value": 1, + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "MCO2_Input_Source", + "value": 100000000, + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "I2C2_Clock_Source", + "value": "PSIK_inputid", + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "I2C2_Input_Clock", + "value": 100000000, + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "I3C1_Clock_Source", + "value": "APB1_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "I3C1_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "DAC1SH_Clock_Source", + "value": "LSI_inputid", + "isLocked": false, + "outFrequency": 32000 + }, + { + "id": "DAC1SH_Input_Clock", + "value": 32000, + "isLocked": false, + "outFrequency": 32000 + }, + { + "id": "SPI1_Clock_Source", + "value": "APB2_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "SPI2_Clock_Source", + "value": "APB1_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "SPI3_Clock_Source", + "value": "APB1_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "SPI1_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "SPI2_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "SPI3_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "XSPI1_Clock_Source", + "value": "HCLK_Frequency_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "XSPI1_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "ETH1_Clock_Source", + "value": "PSI_inputid", + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "ETH1_Input_Clock", + "value": 100000000, + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "ETH1_RMII_REF", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "ETH1_REF_Clock_Source", + "value": "ETH1_RMII_REF_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "ETH1_REF_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "ETH1_PTP_Clock_Source", + "value": "AHB_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "ETH1_PTP_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "LSCO_Clock_Source", + "value": "LSI_inputid", + "isLocked": false, + "outFrequency": 32000 + }, + { + "id": "LSCO_Input_Source", + "value": 32000, + "isLocked": false, + "outFrequency": 32000 + }, + { + "id": "HSI_DIV_3", + "value": 3, + "isLocked": false, + "outFrequency": 48000000 + }, + { + "id": "HSIK", + "value": 1, + "isLocked": false, + "outFrequency": 144000000 + }, + { + "id": "System_Clock_Source", + "value": "PSI_inputid", + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "System_Clock_Frequency", + "value": 100000000, + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "PWR_Input_Clock", + "value": 100000000, + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "AHB_Clock_Divider", + "value": 2, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "HCLK_Frequency", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "AHB_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "LPTIM1_Clock_Source", + "value": "APB3_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "LPTIM1_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "LPUART_Clock_Source", + "value": "APB3_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "LPUART_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "CRS_Input_Clock", + "value": 48000000, + "isLocked": false, + "outFrequency": 48000000 + }, + { + "id": "Cortex_Divider", + "value": 8, + "isLocked": false, + "outFrequency": 6250000 + }, + { + "id": "Cortex_System_Timer", + "value": 6250000, + "isLocked": false, + "outFrequency": 6250000 + }, + { + "id": "FCLK_Cortex", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "APB1_Clock_Divider", + "value": 1, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "APB2_Clock_Divider", + "value": 1, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "APB3_Clock_Divider", + "value": 1, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "APB1_Peripheral_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "APB2_Peripheral_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "APB3_Peripheral_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "USBFS_Input_Clock", + "value": 48000000, + "isLocked": false, + "outFrequency": 48000000 + }, + { + "id": "RNG_Input_Clock", + "value": 48000000, + "isLocked": false, + "outFrequency": 48000000 + }, + { + "id": "TIMx_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "TIMx2_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "ADC_DAC_Clock_Source", + "value": "PSI_inputid", + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "ADC_Input_Clock", + "value": 25000000, + "isLocked": false, + "outFrequency": 25000000 + }, + { + "id": "DAC1_Input_Clock", + "value": 25000000, + "isLocked": false, + "outFrequency": 25000000 + }, + { + "id": "I2C1_Clock_Source", + "value": "APB1_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "I2C1_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "USART1_Clock_Source", + "value": "APB2_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "USART1_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "USART2_Clock_Source", + "value": "APB1_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "USART2_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "USART3_Clock_Source", + "value": "APB1_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "USART6_Clock_Source", + "value": "APB1_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "UART4_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "UART4_Clock_Source", + "value": "APB1_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "USART3_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "USART6_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "UART5_Clock_Source", + "value": "APB1_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "UART5_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "UART7_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "UART7_Clock_Source", + "value": "APB1_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "PSI_Clock_Mux", + "value": "HSI_DIV_18_inputid", + "isLocked": false, + "outFrequency": 8000000 + }, + { + "id": "HSI_DIV_18", + "value": 18, + "isLocked": false, + "outFrequency": 8000000 + }, + { + "id": "PSI", + "value": 100000000, + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "PSI_DIV_3", + "value": 3, + "isLocked": false, + "outFrequency": 33333333.333333332 + }, + { + "id": "PSIK", + "value": 1, + "isLocked": false, + "outFrequency": 100000000 + }, + { + "id": "Cortex_Clock_Mux", + "value": "Cortex_Divider_inputid", + "isLocked": false, + "outFrequency": 6250000 + }, + { + "id": "FDCAN_Clock_Source", + "value": "APB1_Peripheral_Clock_inputid", + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "FDCAN1_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "FDCAN2_Input_Clock", + "value": 50000000, + "isLocked": false, + "outFrequency": 50000000 + }, + { + "id": "AUDIO_Source", + "value": 4800, + "isLocked": false, + "outFrequency": 4800 + }, + { + "id": "ADCDACPRE_DIV", + "value": 4, + "isLocked": false, + "outFrequency": 25000000 + }, + { + "id": "USB_RNG_Clock_Source", + "value": "HSI_DIV_3_inputid", + "isLocked": false, + "outFrequency": 48000000 + }, + { + "id": "ETH1_CLK_Div", + "value": 1, + "isLocked": false, + "outFrequency": 100000000 + } + ] +}""" +"File: .settings/dma.store.json" = """ +{ + "version": 2, + "resourcesAllocations": [], + "resourcesNeeds": [], + "resourceReservations": [] +}""" +"File: .settings/envModelStore.store.json" = """ +{ + "envVar": { + "CORE_PROJECT_TIMEBASE": { + "name": "CORE_PROJECT_TIMEBASE", + "value": "SYSTICK", + "originator": "ddbd6b8f-2601-4b0e-9350-7900dcbfda90" + }, + "HAL_CORTEX_CORE_ENABLED": { + "name": "HAL_CORTEX_CORE_ENABLED", + "value": true, + "originator": "afd5b53f-f251-40b2-ad99-0e48c1139af5" + }, + "HAL_CORTEX_PROJECT_USE_HAL": { + "name": "HAL_CORTEX_PROJECT_USE_HAL", + "value": 2, + "originator": "sw-config-semaphore" + }, + "HAL_ICACHE_CORE_ENABLED": { + "name": "HAL_ICACHE_CORE_ENABLED", + "value": true, + "originator": "93d223f4-db9b-4dea-94d0-2ff16c085039" + }, + "HAL_ICACHE_PROJECT_USE_HAL": { + "name": "HAL_ICACHE_PROJECT_USE_HAL", + "value": 1, + "originator": "sw-config-semaphore" + }, + "HAL_RCC_PROJECT_USE_HAL": { + "name": "HAL_RCC_PROJECT_USE_HAL", + "value": 1, + "originator": "sw-config-semaphore" + }, + "SYSTEM_PROJECT_CODEGEN_STRATEGY": { + "name": "SYSTEM_PROJECT_CODEGEN_STRATEGY", + "value": "HW", + "originator": "556db68c-8974-4b5e-8151-3f0dd4dc1905" + }, + "HAL_SYSTEM_CORE_EXTI_CALLBACK_USER_DATA": { + "name": "HAL_SYSTEM_CORE_EXTI_CALLBACK_USER_DATA", + "value": false, + "originator": "556db68c-8974-4b5e-8151-3f0dd4dc1905" + }, + "HAL_GPIO_PROJECT_USE_HAL": { + "name": "HAL_GPIO_PROJECT_USE_HAL", + "value": 12, + "originator": "sw-config-semaphore" + }, + "HAL_ETH_PROJECT_USE_HAL": { + "name": "HAL_ETH_PROJECT_USE_HAL", + "value": 1, + "originator": "sw-config-semaphore" + }, + "HAL_UART_PROJECT_USE_HAL": { + "name": "HAL_UART_PROJECT_USE_HAL", + "value": 1, + "originator": "sw-config-semaphore" + }, + "HAL_RNG_PROJECT_USE_HAL": { + "name": "HAL_RNG_PROJECT_USE_HAL", + "value": 1, + "originator": "sw-config-semaphore" + } + } +}""" +"File: .settings/export-settings.store.json" = """ +{ + "layout": { + "defaultInstallationFolderBase": "misc", + "useCustomInstallPaths": true, + "customPackPaths": [ + { + "packName": "Cesanta.I-CUBE-Mongoose.7.23.2", + "folder": "middleware/Mongoose" + }, + { + "packName": "STMicroelectronics.CMSIS.6.3.0", + "folder": "arch/cmsis" + }, + { + "packName": "STMicroelectronics.stm32c5xx_dfp.2.1.0", + "folder": "stm32c5xx_dfp" + }, + { + "packName": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0", + "folder": "stm32c5xx_drivers" + }, + { + "packName": "STMicroelectronics.stm32cubemx2_templates_no_os_stm32c5.2.1.0", + "folder": "misc/STMicroelectronics.stm32cubemx2_templates_no_os_stm32c5.2.1.0" + } + ] + }, + "conflict": { + "generated": "DIFF", + "all": "OVERWRITE_WITHOUT_BACKUP", + "pack": "DIFF", + "project_file": "DIFF", + "RTE": "DIFF", + "user_code": "DIFF" + }, + "export": { + "configurations": { + "CMake": { + "outputPath": "c5_cmake", + "toolchain": "GCC", + "exportSource": "include-packs-from-local", + "removeBoard": true + } + }, + "lastUsedFormat": "CMake" + } +}""" +"File: .settings/exti.store.json" = """ +{ + "version": 2, + "resourcesAllocations": [], + "resourcesNeeds": [] +}""" +"File: .settings/global-project-components.store.json" = """ +{ + "activatedServices": [ + { + "id": "HALCore", + "name": "HAL common definitions", + "configurationId": "ddbd6b8f-2601-4b0e-9350-7900dcbfda90", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84" + }, + { + "id": "SystemInit", + "name": "HAL System Init", + "configurationId": "556db68c-8974-4b5e-8151-3f0dd4dc1905", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84" + } + ] +}""" +"File: .settings/nvic.store.json" = """ +{ + "version": 1, + "configurations": [ + { + "projectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "core": "Cortex-M33", + "context": "NON_SECURE", + "instance": "NVIC1", + "grouping": 0, + "priority_values": { + "priority": [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ], + "subpriority": [ + 0 + ] + }, + "interrupts": [ + { + "id": 9, + "name": "SysTick", + "priority": 15, + "subpriority": 0, + "used": true + } + ], + "needs": [] + } + ], + "resourceNeeds": [], + "description": { + "instances": [] + } +}""" +"File: .settings/pack-layout.store.json" = """ +{ + "layout": { + "defaultInstallationFolderBase": "misc", + "useOverrideInstallPatterns": true, + "overrideInstallPatterns": [ + { + "pattern": "(STMicroelectronics|ARM)\\\\.CMSIS-NN\\\\..*", + "folder": "arch/cmsis_nn" + }, + { + "pattern": "(STMicroelectronics|ARM)\\\\.CMSIS-Compiler\\\\..*", + "folder": "arch/cmsis_compiler" + }, + { + "pattern": "(STMicroelectronics|ARM)\\\\.CMSIS-DSP\\\\..*", + "folder": "arch/cmsis_dsp" + }, + { + "pattern": "(STMicroelectronics|ARM)\\\\.CMSIS\\\\..*", + "folder": "arch/cmsis" + }, + { + "pattern": "(STMicroelectronics|ARM)\\\\..*CMSIS.*", + "folder": "arch" + }, + { + "pattern": "STMicroelectronics\\\\.(.*)_hal_drivers.*", + "folder": "\\\\1_drivers" + }, + { + "pattern": "STMicroelectronics\\\\.(.*_dfp).*", + "folder": "\\\\1" + }, + { + "pattern": "STMicroelectronics\\\\.utility.*", + "folder": "utilities" + }, + { + "pattern": "STMicroelectronics\\\\.mw_([^.]+)\\\\..*", + "folder": "middleware/\\\\1" + }, + { + "pattern": "STMicroelectronics.filex\\\\..*", + "folder": "middleware/filex" + }, + { + "pattern": "STMicroelectronics.freertos\\\\..*", + "folder": "middleware/freertos" + }, + { + "pattern": "STMicroelectronics.levelx\\\\..*", + "folder": "middleware/levelx" + }, + { + "pattern": "STMicroelectronics.lwip\\\\..*", + "folder": "middleware/lwip" + }, + { + "pattern": "STMicroelectronics.mbedtls\\\\..*", + "folder": "middleware/mbedtls" + }, + { + "pattern": "STMicroelectronics.mcuboot\\\\..*", + "folder": "middleware/mcuboot" + }, + { + "pattern": "STMicroelectronics.stcryptolib\\\\..*", + "folder": "middleware/stcryptolib" + }, + { + "pattern": "STMicroelectronics.stfcf\\\\..*", + "folder": "middleware/stfcf" + }, + { + "pattern": "STMicroelectronics.stm32_touchsensing_library\\\\..*", + "folder": "middleware/stm32_touchsensing_library" + }, + { + "pattern": "STMicroelectronics.usbpd\\\\..*", + "folder": "middleware/usbpd" + }, + { + "pattern": "STMicroelectronics.usbx\\\\..*", + "folder": "middleware/usbx" + }, + { + "pattern": "STMicroelectronics.adv_trace\\\\..*", + "folder": "utilities/adv_trace" + }, + { + "pattern": "STMicroelectronics.basic_stdio\\\\..*", + "folder": "utilities/basic_stdio" + }, + { + "pattern": "STMicroelectronics.eeprom_emulation\\\\..*", + "folder": "utilities/eeprom_emulation" + }, + { + "pattern": "STMicroelectronics.sequencer\\\\..*", + "folder": "utilities/sequencer" + }, + { + "pattern": "STMicroelectronics.syscalls\\\\..*", + "folder": "utilities/syscalls" + }, + { + "pattern": "STMicroelectronics.thread_safe_libc\\\\..*", + "folder": "utilities/thread_safe_libc" + } + ], + "overridePackMappingRules": [ + { + "selectors": [ + { + "packVendor": "ARM" + }, + { + "packName": "*CMSIS*" + } + ], + "path": "arch/{{packName}}" + }, + { + "selectors": [ + { + "packType": "HAL" + } + ], + "path": "{{packFriendlyName}}" + }, + { + "selectors": [ + { + "packType": "DFP" + } + ], + "path": "{{packFriendlyName}}" + }, + { + "selectors": [ + { + "packType": "PARTDRV" + } + ], + "path": "{{parent}}/{{packFriendlyName}}" + }, + { + "selectors": [ + { + "packType": "MW" + } + ], + "path": "{{parent}}/{{packFriendlyName}}" + }, + { + "selectors": [ + { + "packType": "UTILITY" + } + ], + "path": "{{parent}}/{{packFriendlyName}}" + }, + { + "selectors": [ + { + "packType": "EXAMPLE" + } + ], + "path": "{{parent}}/{{layer}}/{{element}}/{{packFriendlyName}}" + }, + { + "selectors": [ + { + "packType": "HWBOARD" + } + ], + "path": "" + }, + { + "selectors": [ + { + "packType": "HWPART" + } + ], + "path": "" + }, + { + "selectors": [ + { + "packType": "TEMPLATE" + } + ], + "path": "" + }, + { + "selectors": [], + "path": "misc/{{packVendor}}.{{packName}}.{{packVersion}}" + } + ], + "overrideGeneratorMappingRules": [ + { + "selectors": [ + { + "generator": "HALCodeGen" + } + ], + "path": "{{SWprj}}/generated/hal/" + }, + { + "selectors": [ + { + "generator": "FreeRTOSCodeGen" + } + ], + "path": "{{SWprj}}/generated/middleware" + }, + { + "selectors": [ + { + "generator": "*" + }, + { + "packType": "HAL" + } + ], + "path": "{{SWprj}}/generated/hal" + }, + { + "selectors": [ + { + "generator": "*" + }, + { + "packType": "MW" + } + ], + "path": "{{SWprj}}/generated/middleware" + }, + { + "selectors": [ + { + "generator": "*" + }, + { + "packType": "PARTDRV" + } + ], + "path": "{{SWprj}}/generated/parts" + }, + { + "selectors": [ + { + "generator": "*" + }, + { + "packType": "UTILITY" + } + ], + "path": "{{SWprj}}/generated/utilities" + }, + { + "selectors": [ + { + "generator": "FreeRTOSAppCodeGen" + } + ], + "path": "{{SWprj}}/." + }, + { + "selectors": [ + { + "generator": "*AppCodeGen" + } + ], + "path": "{{SWprj}}/." + }, + { + "selectors": [ + { + "generator": "*" + } + ], + "path": "{{SWprj}}/generated/{{generatorID}}" + } + ] + } +}""" +"File: .settings/pinout.store.json" = """ +{ + "version": 10, + "pinout-configuration": { + "userConfigurations": [ + { + "pin": { + "name": "PD8", + "position": "77", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [], + "ioType": "I/O", + "ioStructure": "FT", + "index": 8, + "port": "D" + }, + "signal": { + "instance": "USART3", + "name": "USART3_TX", + "type": "alternate", + "alternateFunctionId": "AF7" + }, + "pinned": true + }, + { + "pin": { + "name": "PD9", + "position": "78", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [], + "ioType": "I/O", + "ioStructure": "FT", + "index": 9, + "port": "D" + }, + "signal": { + "instance": "USART3", + "name": "USART3_RX", + "type": "alternate", + "alternateFunctionId": "AF7" + }, + "pinned": true + } + ], + "needConfigurations": [ + { + "id": "51aca76f-47bb-485c-87c2-5799f42218d3", + "needId": "51aca76f-47bb-485c-87c2-5799f42218d3", + "pin": { + "name": "PA1", + "position": "35", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [ + "a" + ], + "ioType": "I/O", + "ioStructure": "FT", + "index": 1, + "port": "A" + }, + "signal": { + "instance": "ETH1", + "name": "ETH1_RMII_REF_CLK", + "type": "alternate", + "alternateFunctionId": "AF10" + }, + "pinned": false, + "ownedByUser": false + }, + { + "id": "a44c6644-8105-4568-b133-6f5460c4e284", + "needId": "a44c6644-8105-4568-b133-6f5460c4e284", + "pin": { + "name": "PA10", + "position": "102", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [], + "ioType": "I/O", + "ioStructure": "FT", + "index": 10, + "port": "A" + }, + "signal": { + "instance": "ETH1", + "name": "ETH1_CLK", + "type": "alternate", + "alternateFunctionId": "AF13" + }, + "pinned": false, + "ownedByUser": false + }, + { + "id": "3130abee-7578-4f30-a825-c241a4f93b31", + "needId": "3130abee-7578-4f30-a825-c241a4f93b31", + "pin": { + "name": "PA2", + "position": "36", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [ + "a" + ], + "ioType": "I/O", + "ioStructure": "FT", + "index": 2, + "port": "A" + }, + "signal": { + "instance": "USART2", + "name": "USART2_TX", + "type": "alternate", + "alternateFunctionId": "AF7" + }, + "pinned": true, + "ownedByUser": false + }, + { + "id": "c261a5df-a938-4475-96d2-440e231ac5fc", + "needId": "c261a5df-a938-4475-96d2-440e231ac5fc", + "pin": { + "name": "PC5", + "position": "45", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [ + "a" + ], + "ioType": "I/O", + "ioStructure": "FT", + "index": 5, + "port": "C" + }, + "signal": { + "instance": "ETH1", + "name": "ETH1_RMII_RXD1", + "type": "alternate", + "alternateFunctionId": "AF13" + }, + "pinned": false, + "ownedByUser": false + }, + { + "id": "1ba77734-c758-432d-9d85-dec0a00bf03e", + "pin": { + "name": "PA3", + "position": "37", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [ + "a" + ], + "ioType": "I/O", + "ioStructure": "FT", + "index": 3, + "port": "A" + }, + "signal": { + "instance": "USART2", + "name": "USART2_RX", + "type": "alternate", + "alternateFunctionId": "AF7" + }, + "needId": "1ba77734-c758-432d-9d85-dec0a00bf03e", + "pinned": true, + "ownedByUser": false + }, + { + "id": "63f2ffe7-3f41-4ab6-af6e-dcb1dd3c04bc", + "pin": { + "name": "PG12", + "position": "127", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [], + "ioType": "I/O", + "ioStructure": "FT", + "index": 12, + "port": "G" + }, + "signal": { + "instance": "ETH1", + "name": "ETH1_RMII_TXD1", + "type": "alternate", + "alternateFunctionId": "AF10" + }, + "needId": "63f2ffe7-3f41-4ab6-af6e-dcb1dd3c04bc", + "pinned": true, + "ownedByUser": false + }, + { + "id": "c8cffdd2-1e94-476a-90d2-69825b94c111", + "pin": { + "name": "PG11", + "position": "126", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [], + "ioType": "I/O", + "ioStructure": "FT", + "index": 11, + "port": "G" + }, + "signal": { + "instance": "ETH1", + "name": "ETH1_RMII_TX_EN", + "type": "alternate", + "alternateFunctionId": "AF10" + }, + "needId": "c8cffdd2-1e94-476a-90d2-69825b94c111", + "pinned": true, + "ownedByUser": false + }, + { + "id": "e76a1909-4977-4289-8139-57129d0f91db", + "pin": { + "name": "PG13", + "position": "128", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [], + "ioType": "I/O", + "ioStructure": "FT", + "index": 13, + "port": "G" + }, + "signal": { + "instance": "ETH1", + "name": "ETH1_RMII_TXD0", + "type": "alternate", + "alternateFunctionId": "AF10" + }, + "needId": "e76a1909-4977-4289-8139-57129d0f91db", + "pinned": true, + "ownedByUser": false + }, + { + "id": "329c25dd-00b0-4e04-b8cc-d4c32be7bc4d", + "pin": { + "name": "PC1", + "position": "27", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [ + "a" + ], + "ioType": "I/O", + "ioStructure": "FT", + "index": 1, + "port": "C" + }, + "signal": { + "instance": "ETH1", + "name": "ETH1_MDC", + "type": "alternate", + "alternateFunctionId": "AF10" + }, + "needId": "329c25dd-00b0-4e04-b8cc-d4c32be7bc4d", + "pinned": true, + "ownedByUser": false + }, + { + "id": "39260779-e45c-4009-a6b2-d3975febf9bc", + "pin": { + "name": "PE12", + "position": "65", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [ + "a" + ], + "ioType": "I/O", + "ioStructure": "FT", + "index": 12, + "port": "E" + }, + "signal": { + "instance": "ETH1", + "name": "ETH1_MDIO", + "type": "alternate", + "alternateFunctionId": "AF10" + }, + "needId": "39260779-e45c-4009-a6b2-d3975febf9bc", + "pinned": true, + "ownedByUser": false + }, + { + "id": "0d47429e-1e88-4897-8f7d-f576bafbfcad", + "pin": { + "name": "PD1", + "position": "115", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [], + "ioType": "I/O", + "ioStructure": "FT", + "index": 1, + "port": "D" + }, + "signal": { + "instance": "ETH1", + "name": "ETH1_RMII_CRS_DV", + "type": "alternate", + "alternateFunctionId": "AF10" + }, + "needId": "0d47429e-1e88-4897-8f7d-f576bafbfcad", + "pinned": true, + "ownedByUser": false + }, + { + "id": "5e86a142-c9fe-4265-bd92-c6b00306b9ba", + "pin": { + "name": "PC4", + "position": "44", + "type": "gpio", + "powerSource": "VDD", + "ioStructureOptions": [ + "a" + ], + "ioType": "I/O", + "ioStructure": "FT", + "index": 4, + "port": "C" + }, + "signal": { + "instance": "ETH1", + "name": "ETH1_RMII_RXD0", + "type": "alternate", + "alternateFunctionId": "AF12" + }, + "needId": "5e86a142-c9fe-4265-bd92-c6b00306b9ba", + "pinned": true, + "ownedByUser": false + } + ] + }, + "pinout-excluded-pins": [], + "pinout-labels": [], + "pinout-gpio-assignations": [], + "pinout-gpio-groups": [ + { + "id": "default_gpio_group_id", + "name": "gpio_default", + "pins": [] + } + ], + "pinout-gpio-needs": [ + { + "id": "a44c6644-8105-4568-b133-6f5460c4e284", + "needId": "a44c6644-8105-4568-b133-6f5460c4e284", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "signal": "ETH1_CLK", + "instanceName": "ETH1" + }, + { + "id": "51aca76f-47bb-485c-87c2-5799f42218d3", + "needId": "51aca76f-47bb-485c-87c2-5799f42218d3", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "signal": "ETH1_RMII_REF_CLK", + "instanceName": "ETH1" + }, + { + "id": "c261a5df-a938-4475-96d2-440e231ac5fc", + "needId": "c261a5df-a938-4475-96d2-440e231ac5fc", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "signal": "ETH1_RMII_RXD1", + "instanceName": "ETH1" + }, + { + "id": "3130abee-7578-4f30-a825-c241a4f93b31", + "needId": "3130abee-7578-4f30-a825-c241a4f93b31", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentInstanceId": "ab2835f4-2315-4ff0-a788-1ca59e8cdd6c", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:UART@2.1.0#HAL CORE GPIO DMA Init and UART", + "signal": "USART2_TX", + "instanceName": "USART2" + }, + { + "id": "1ba77734-c758-432d-9d85-dec0a00bf03e", + "needId": "1ba77734-c758-432d-9d85-dec0a00bf03e", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentInstanceId": "ab2835f4-2315-4ff0-a788-1ca59e8cdd6c", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:UART@2.1.0#HAL CORE GPIO DMA Init and UART", + "signal": "USART2_RX", + "instanceName": "USART2" + }, + { + "id": "63f2ffe7-3f41-4ab6-af6e-dcb1dd3c04bc", + "needId": "63f2ffe7-3f41-4ab6-af6e-dcb1dd3c04bc", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "signal": "ETH1_RMII_TXD1", + "instanceName": "ETH1" + }, + { + "id": "c8cffdd2-1e94-476a-90d2-69825b94c111", + "needId": "c8cffdd2-1e94-476a-90d2-69825b94c111", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "signal": "ETH1_RMII_TX_EN", + "instanceName": "ETH1" + }, + { + "id": "e76a1909-4977-4289-8139-57129d0f91db", + "needId": "e76a1909-4977-4289-8139-57129d0f91db", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "signal": "ETH1_RMII_TXD0", + "instanceName": "ETH1" + }, + { + "id": "329c25dd-00b0-4e04-b8cc-d4c32be7bc4d", + "needId": "329c25dd-00b0-4e04-b8cc-d4c32be7bc4d", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "signal": "ETH1_MDC", + "instanceName": "ETH1" + }, + { + "id": "39260779-e45c-4009-a6b2-d3975febf9bc", + "needId": "39260779-e45c-4009-a6b2-d3975febf9bc", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "signal": "ETH1_MDIO", + "instanceName": "ETH1" + }, + { + "id": "0d47429e-1e88-4897-8f7d-f576bafbfcad", + "needId": "0d47429e-1e88-4897-8f7d-f576bafbfcad", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "signal": "ETH1_RMII_CRS_DV", + "instanceName": "ETH1" + }, + { + "id": "5e86a142-c9fe-4265-bd92-c6b00306b9ba", + "needId": "5e86a142-c9fe-4265-bd92-c6b00306b9ba", + "softwareProjectId": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "signal": "ETH1_RMII_RXD0", + "instanceName": "ETH1" + } + ], + "pinout-user-settings": { + "package": { + "rotation": 0 + } + } +}""" +"File: STM32C5A3ZGT6_project/.settings/hw-composition.store.json" = """ +{ + "name": "STM32C5A3ZGT6_project", + "boards": [ + { + "type": "VIRTUAL", + "mcuUID": "STMicroelectronics.stm32c5xx_dfp.2.1.0$STMicroelectronics:13::STM32C5A3ZGT6", + "uid": "5bc36631-0504-453f-9dd1-b183bd7a9c7f" + } + ], + "version": 3, + "constraints": [] +}""" +"File: STM32C5A3ZGT6_project/STM32C5A3ZGT6_project.hw" = "{}" +"File: STM32C5A3ZGT6_project/project.cube" = """ +{ + "traits": [ + { + "id": "bf7717e6-07f3-4848-a074-f936711d9523", + "name": "hardware", + "files": [ + "STM32C5A3ZGT6_project.hw" + ] + } + ], + "children": [] +}""" +"File: c5.csolution.yml" = """ +# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/2.11.0/tools/projmgr/schemas/csolution.schema.json +solution: + output-dirs: + tmpdir: project/tmp + outdir: $SolutionDir()$/build/$Project$.$BuildType$ + generators: + base-dir: $ProjectDir()$/generated + options: + - generator: stm32c5xx_hal_mx2codegen + path: $ProjectDir()$/generated/hal + - generator: syscalls_mx2codegen + path: $ProjectDir()$/generated/utilities + - generator: basic_stdio_mx2codegen + path: $ProjectDir()$/generated/utilities + build-types: + - type: debug_GCC + compiler: GCC + - type: release_GCC + compiler: GCC + - type: debug_IAR + compiler: IAR + - type: release_IAR + compiler: IAR + - type: debug_AC6 + compiler: AC6 + - type: release_AC6 + compiler: AC6 + target-types: + - type: STM32C5A3ZGT6 + device: STM32C5A3ZGT6 + projects: + - project: project/c5.cproject.yml + packs: + - pack: Cesanta::I-CUBE-Mongoose@7.23.2 + - pack: STMicroelectronics::CMSIS@6.3.0 + - pack: STMicroelectronics::stm32c5xx_dfp@2.1.0 + - pack: STMicroelectronics::stm32c5xx_hal_drivers@2.1.0 + - pack: STMicroelectronics::stm32cubemx2_templates_no_os_stm32c5@2.1.0 +""" +"File: project.cube" = """ +{ + "traits": [ + { + "id": "96bb7bee-0b22-446f-9659-deebecd050dd", + "name": "application", + "files": [ + "c5.csolution.yml" + ] + } + ], + "children": [ + "STM32C5A3ZGT6_project/STM32C5A3ZGT6_project.hw" + ] +}""" +"File: project/.settings/middleware-utilities-resource-manager.store.json" = """ +{ + "version": 1, + "$type": "https://st.com/schema/middleware-utilities#//", + "id": "5d1a3b98-da0e-4e19-801f-0fd630ff8a7c", + "middleware": [ + "USBX", + "STFCF", + "STCryptoLib", + "Open_Bootloader", + "LwIP", + "LevelX", + "FreeRTOS", + "FileX", + "Mongoose" + ], + "utilities": [ + "Thread_Safe_LibC", + "Syscalls", + "Sequencer", + "EEPROM_Emulation", + "Basic_STDIO" + ] +}""" +"File: project/.settings/part-resource-manager.store.json" = """ +{ + "version": 1, + "$type": "https://st.com/schema/parts#//", + "id": "3070a9d7-d125-4355-9190-9d463ae623a7", + "boundList": [] +}""" +"File: project/.settings/peripherals.store.json" = """ +{ + "configuration": { + "MPU": { + "driverId": "STMicroelectronics::Device:STM32CubeMX2 Config:CORTEX MPU", + "driverConfigurationId": "afd5b53f-f251-40b2-ad99-0e48c1139af5" + }, + "ICACHE": { + "driverId": "STMicroelectronics::Device:STM32CubeMX2 Config:ICACHE", + "driverConfigurationId": "93d223f4-db9b-4dea-94d0-2ff16c085039" + }, + "RCC": { + "driverId": "STMicroelectronics::Device:STM32CubeMX2 Config:RCC", + "driverConfigurationId": "abca66f8-09d5-4866-9ba0-0b2ff018ef22" + }, + "NVIC": { + "driverId": "STMicroelectronics::Device:STM32CubeMX2 Config:CORTEX NVIC", + "driverConfigurationId": "afeed797-5f6c-45ad-8fd8-0affb43677e5" + }, + "ETH1": { + "driverId": "STMicroelectronics::Device:STM32CubeMX2 Config:ETH", + "driverConfigurationId": "e893f130-3ec1-4220-a100-81c772646223" + }, + "USART2": { + "driverId": "STMicroelectronics::Device:STM32CubeMX2 Config:UART", + "driverConfigurationId": "ab2835f4-2315-4ff0-a788-1ca59e8cdd6c", + "mode": "Async" + }, + "RNG": { + "driverConfigurationId": "fca73b1f-d8c4-4faa-a69f-3b2f381a9466", + "driverId": "STMicroelectronics::Device:STM32CubeMX2 Config:RNG" + } + } +}""" +"File: project/.settings/sw-composition.store.json" = """ +{ + "componentModel": { + "version": 2, + "$type": "http://st.com/schema/sw-composer#//SWComposition", + "id": "2f236420-2411-43f5-a4db-540139f7193e", + "components": [ + { + "$type": "http://st.com/schema/sw-composer#//SingleInstanceSWComponent", + "id": "a9f3a340-d022-4eb2-86fd-7ec30909b407", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:CORE@2.1.0#HAL Generated code", + "label": "STM32CubeMX2 Config:CORE", + "expanded": true, + "userAdded": true + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "fdd5f6e5-b882-41d8-a212-41dfd6634fd5", + "componentDescriptionId": "STMicroelectronics.CMSIS.6.3.0$STMicroelectronics::CMSIS:CORE@6.2.0#ARMv6_7_8-M Device", + "label": "CORE", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "d18a9ff3-99d7-45f8-9479-6d47d55d3789", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:UTILS@2.0.0#STM32C5", + "label": "STM32 LL:UTILS", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "e8203df6-a1b8-4f94-8d86-49dda66a723e", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Codegen:Generated Code@2.0.0#HAL Common", + "label": "STM32CubeMX2 Codegen:Generated Code", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//MultiInstanceSWComponent", + "id": "6a7563c7-cf8e-4d61-85f6-3e2b05d4963f", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:CORTEX MPU@2.1.0#HAL CORE Init and CORTEX", + "label": "STM32CubeMX2 Config:CORTEX MPU", + "expanded": true, + "userAdded": true + }, + { + "$type": "http://st.com/schema/sw-composer#//MultiInstanceSWComponent", + "id": "c73ab526-2181-48eb-b0d7-ab068fce3a62", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ICACHE@2.1.0#HAL CORE Init and ICACHE", + "label": "STM32CubeMX2 Config:ICACHE", + "expanded": true, + "userAdded": true + }, + { + "$type": "http://st.com/schema/sw-composer#//SingleInstanceSWComponent", + "id": "0c077ba3-6720-4201-b2c8-3ec9c5ea2460", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:RCC@2.1.0#HAL CORE Init GPIO and RCC", + "label": "STM32CubeMX2 Config:RCC", + "expanded": true, + "userAdded": true + }, + { + "$type": "http://st.com/schema/sw-composer#//MultiInstanceSWComponent", + "id": "64fe0f73-99e0-4d8e-9277-be25a95b1f99", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:CORTEX NVIC@2.1.0#HAL CORE Init and CORTEX", + "label": "STM32CubeMX2 Config:CORTEX NVIC", + "expanded": true, + "userAdded": true + }, + { + "$type": "http://st.com/schema/sw-composer#//SingleInstanceSWComponent", + "id": "b27137de-f5ba-4fca-bf24-997093cb7536", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:System@2.1.0#HAL System Init", + "label": "STM32CubeMX2 Config:System", + "expanded": true, + "userAdded": true + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "430ffa88-9128-41c1-8579-fb2c7ecd10f1", + "componentDescriptionId": "STMicroelectronics.stm32cubemx2_templates_no_os_stm32c5.2.1.0$STMicroelectronics::Application:stm32cubemx2_templates&no os@2.1.0#template no os dependencies", + "label": "stm32cubemx2_templates:no os", + "expanded": true, + "userAdded": true + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "096a27fc-4dce-40f6-9d43-e33aec9f35ce", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_dfp.2.1.0$STMicroelectronics::Device:Startup@2.1.0#STM32C5", + "label": "Startup", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//MultiInstanceSWComponent", + "id": "083411d2-2335-481f-80fc-bf68736b2c7f", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "label": "STM32CubeMX2 Config:ETH", + "expanded": true, + "userAdded": true + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "d98ec214-108c-4003-aab7-b6d9905b40dd", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:ETH@2.1.0#HAL CORE", + "label": "STM32 HAL:ETH", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SingleInstanceSWComponent", + "id": "1c941dce-9cdd-46f2-b21a-186dae122778", + "componentDescriptionId": "Cesanta.I-CUBE-Mongoose.7.23.2$Cesanta::Mongoose:Networking Core@7.23.2", + "label": "Networking Core", + "expanded": true, + "userAdded": true + }, + { + "$type": "http://st.com/schema/sw-composer#//MultiInstanceSWComponent", + "id": "c9cf0d9a-f93f-4f52-9408-83cd8c6a8262", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:UART@2.1.0#HAL CORE GPIO DMA Init and UART", + "label": "STM32CubeMX2 Config:UART", + "expanded": true, + "userAdded": true + }, + { + "$type": "http://st.com/schema/sw-composer#//MultiInstanceSWComponent", + "id": "7c374dbb-8db9-4f6e-a95a-9ad51def7245", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:RNG@2.1.0#HAL CORE Init and RNG", + "label": "STM32CubeMX2 Config:RNG", + "expanded": true, + "userAdded": true + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "38c37011-fb09-4644-8295-b069bad74095", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:CORTEX@2.0.0#HAL CORTEX", + "label": "STM32 HAL:CORTEX", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "27608db7-a89f-4b69-94dc-e116c8d3cda1", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:Core@2.0.0#HAL Common", + "label": "STM32 HAL:Core", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "9afabb4d-2ca6-4eb4-aaa9-bc9a07e9f883", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:DMA@2.1.0#HAL DMA", + "label": "STM32 HAL:DMA", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "190b89b9-37f2-4f71-b6ff-1474091ad3be", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:FLASH_ITF@2.1.0#HAL FLASH_ITF", + "label": "STM32 HAL:FLASH_ITF", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "65994172-2bd2-41dc-8794-9ad507481b5e", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:GPIO@2.1.0#HAL GPIO", + "label": "STM32 HAL:GPIO", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "219c587f-d074-4742-849e-cae6054dc7b9", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:ICACHE@2.1.0#HAL ICACHE", + "label": "STM32 HAL:ICACHE", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "9be92598-7de4-4f77-a1f0-06b9f556bde2", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:PWR@2.0.1#HAL PWR", + "label": "STM32 HAL:PWR", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "57c52902-beeb-47a3-ad2e-baf4d809379e", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:Q@2.0.0#HAL CORE", + "label": "STM32 HAL:Q", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "b23c3bd4-86b6-4895-9df1-b8e4eac10c90", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:RCC@2.0.0#HAL RCC", + "label": "STM32 HAL:RCC", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "fe2965eb-e419-4aa3-8452-335d61f3b726", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:RNG@2.0.0#HAL RNG", + "label": "STM32 HAL:RNG", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "426060fb-67aa-4d91-b90d-b249ab18e77e", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:UART@2.0.1#HAL UART", + "label": "STM32 HAL:UART", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "8043520a-88a3-4f73-83df-f06c56b04d73", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 HAL:timebases&SYSTICK@2.0.0#Timebase NONE", + "label": "STM32 HAL:SYSTICK", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "14ffcb0e-b048-4be5-b807-42da46486d43", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:BUS@2.0.1#LL", + "label": "STM32 LL:BUS", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "413c127a-8cd5-4df6-b4fa-3cac22f539cb", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:Common@2.0.0#CMSIS Core", + "label": "STM32 LL:Common", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "51380879-a693-45b9-80dc-7fb41980f73f", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:DMA@2.1.0#LL", + "label": "STM32 LL:DMA", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "d2f4cdc3-9dfa-40ef-b350-cee8e063ba92", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:EXTI@2.1.0#LL", + "label": "STM32 LL:EXTI", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "64ec163a-b3be-47e2-9557-98bf72ea0a7d", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:FLASH@2.1.0#LL", + "label": "STM32 LL:FLASH", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "e4f8fdf0-3c24-4667-b843-5a813c75aa5f", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:GPIO@2.1.0#LL", + "label": "STM32 LL:GPIO", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "b6b07c07-8c66-4903-9185-4c5e4faec8f7", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:ICACHE@2.0.0#LL", + "label": "STM32 LL:ICACHE", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "3c0bbbaa-a099-4059-a6fa-17058ffe0092", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:PWR@2.0.0#LL", + "label": "STM32 LL:PWR", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "cd2e76de-a229-43e9-bda6-81cf7ec5bc98", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:RCC@2.0.0#LL", + "label": "STM32 LL:RCC", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "1938714e-62f8-4abd-b9e0-18564817546c", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:RNG@2.0.0#LL", + "label": "STM32 LL:RNG", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "29c447a5-4ca0-464d-9871-88fb2743aca5", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:SBS@2.0.0#LL", + "label": "STM32 LL:SBS", + "expanded": true, + "userAdded": false + }, + { + "$type": "http://st.com/schema/sw-composer#//SWComponent", + "id": "771c17d4-6b2a-4c6e-aff5-7f4056891877", + "componentDescriptionId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:USART@2.0.0#LL", + "label": "STM32 LL:USART", + "expanded": true, + "userAdded": false + } + ] + }, + "notation": { + "version": 1, + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Diagram", + "$id": "e4a1da54-3c06-48de-be19-23f6d30472b0", + "semanticElement": { + "uri": "2f236420-2411-43f5-a4db-540139f7193e" + }, + "elements": [ + { + "$id": "efd60dc0-8739-4cfe-bcf4-888a7ef26d6f", + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Shape", + "semanticElement": { + "uri": "a9f3a340-d022-4eb2-86fd-7ec30909b407" + }, + "position": { + "x": 0, + "y": 0 + } + }, + { + "$id": "9181362a-843b-459c-bff9-48916b94ad03", + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Shape", + "semanticElement": { + "uri": "fdd5f6e5-b882-41d8-a212-41dfd6634fd5" + }, + "position": { + "x": 0, + "y": 0 + } + }, + { + "$id": "8949e044-cbb8-4070-9eba-3e844fad9b56", + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Shape", + "semanticElement": { + "uri": "d18a9ff3-99d7-45f8-9479-6d47d55d3789" + }, + "position": { + "x": 0, + "y": 0 + } + }, + { + "$id": "eec0d7d4-b037-4ed4-889b-c25ca93a2bf9", + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Shape", + "semanticElement": { + "uri": "e8203df6-a1b8-4f94-8d86-49dda66a723e" + }, + "position": { + "x": 0, + "y": 0 + } + }, + { + "$id": "09bf4d24-98f7-4e20-bb13-f4247f86a19b", + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Shape", + "semanticElement": { + "uri": "6a7563c7-cf8e-4d61-85f6-3e2b05d4963f" + }, + "position": { + "x": 0, + "y": 0 + } + }, + { + "$id": "10bbd34d-e1f8-4f3f-86be-8a42dc44b6c4", + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Shape", + "semanticElement": { + "uri": "c73ab526-2181-48eb-b0d7-ab068fce3a62" + }, + "position": { + "x": 0, + "y": 0 + } + }, + { + "$id": "cb6c1a12-576b-450a-9db4-b0af256b001f", + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Shape", + "semanticElement": { + "uri": "0c077ba3-6720-4201-b2c8-3ec9c5ea2460" + }, + "position": { + "x": 0, + "y": 0 + } + }, + { + "$id": "41167318-88af-4f46-8b02-18d18445d143", + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Shape", + "semanticElement": { + "uri": "64fe0f73-99e0-4d8e-9277-be25a95b1f99" + }, + "position": { + "x": 0, + "y": 0 + } + }, + { + "$id": "b43bf916-e915-46d8-93d1-555cd79ea27d", + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Shape", + "semanticElement": { + "uri": "b27137de-f5ba-4fca-bf24-997093cb7536" + }, + "position": { + "x": 0, + "y": 0 + } + }, + { + "$id": "df62d372-9671-4f53-bf86-de5eb16034a2", + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Shape", + "semanticElement": { + "uri": "ebb98873-deb4-4240-8bf7-586c2b78c3a6" + }, + "position": { + "x": 0, + "y": 0 + } + }, + { + "$id": "8d7ff11e-1837-4c1d-9ec6-3bdacd18fb1d", + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Shape", + "semanticElement": { + "uri": "430ffa88-9128-41c1-8579-fb2c7ecd10f1" + }, + "position": { + "x": 0, + "y": 0 + } + }, + { + "$id": "c03cf07a-b7af-4396-912d-78b0dc4153d5", + "$type": "http://www.eclipse.org/emfcloud/modelserver/notation#//Shape", + "semanticElement": { + "uri": "096a27fc-4dce-40f6-9d43-e33aec9f35ce" + }, + "position": { + "x": 0, + "y": 0 + } + } + ] + } +}""" +"File: project/.settings/sw-configuration.store.json" = """ +{ + "software": { + "model": { + "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:CORE@2.1.0#HAL Generated code": [ + { + "index": 0, + "instanceId": "ddbd6b8f-2601-4b0e-9350-7900dcbfda90", + "name": "MyCORE_1", + "entity": "globalProjectComponent", + "settings": { + "parameters": { + "common": { + "prefetch_enable": true, + "check_param": false, + "secure_check_param": false, + "check_process_state": false, + "assert_dbg_param": false, + "assert_dbg_state": false, + "hal_mutex": false, + "timebase_feature": { + "hal_timebase_selection": "SYSTICK" + } + }, + "used_components": false, + "icache_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false + }, + "rcc_feature": { + "use_hal_rcc_reset_periph_clock_management": false, + "use_hal_rcc_reset_rtc_domain": false + }, + "adc_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_adc_dma": false + }, + "aes_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "rng_recovery": true, + "use_hal_aes_suspend_resume": false, + "use_hal_aes_ccm_algo": false, + "use_hal_aes_ctr_algo": false, + "use_hal_aes_dma": false, + "use_hal_aes_ecb_cbc_algo": false, + "use_hal_aes_gcm_gmac_algo": false, + "use_hal_aes_rng_recovery": true + }, + "ccb_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "rng_recovery": true, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_ccb_rng_recovery": true + }, + "comp_feature": { + "use_register_callback": false, + "user_data": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_comp_exti": false, + "use_hal_comp_window_mode": false + }, + "cordic_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_cordic_dma": false + }, + "crc_feature": { + "user_data": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO" + }, + "crs_feature": { + "user_data": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "get_last_errors": false, + "use_register_callback": false + }, + "dac_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_dac_dma": false, + "use_hal_dac_dual_channel": false + }, + "dma_feature": { + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO" + }, + "eth_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_eth_atomic_channel_lock": false, + "use_hal_eth_max_rx_ch_nb": 1, + "use_hal_eth_max_tx_ch_nb": 1 + }, + "exti_feature": { + "use_register_callback": false, + "user_data": false + }, + "fdcan_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO" + }, + "flash_feature": { + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "use_hal_flash_ob_edata": false, + "use_hal_flash_ecc": false, + "use_hal_flash_erase_bank": false, + "use_hal_flash_erase_by_addr": false, + "use_hal_flash_erase_page": false, + "use_hal_flash_mass_erase": false, + "use_hal_flash_program_by_addr": false + }, + "gpio_feature": { + "clk_enable_model": "HAL_CLK_ENABLE_NO" + }, + "hash_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_hash_dma": false + }, + "hcd_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "use_hal_hcd_usb_double_buffer": false, + "use_hal_hcd_usb_ep_type_isoc": false, + "use_hal_hcd_max_channel_nb": 16 + }, + "i2c_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_i2c_dma": false + }, + "i2s_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "use_hal_i2s_ovr_udr_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_i2s_dma": false + }, + "i3c_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_i3c_dma": false + }, + "iwdg_feature": { + "use_register_callback": false, + "user_data": false, + "use_hal_iwdg_time_unit": "HAL_IWDG_TIME_UNIT_MS", + "use_hal_iwdg_hardware_start": false + }, + "lptim_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_lptim_dma": false + }, + "opamp_feature": { + "user_data": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_opamp_calibrate_parallel": false + }, + "pcd_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "use_hal_pcd_usb_lpm": false, + "use_hal_pcd_usb_bcd": false, + "use_hal_pcd_usb_ep_type_isoc": false, + "use_hal_pcd_usb_double_buffer": false, + "use_hal_pcd_max_endpoint_nb": 8 + }, + "pka_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "rng_recovery": true, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_pka_rng_recovery": true + }, + "rng_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO" + }, + "smartcard_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_smartcard_dma": false, + "use_hal_smartcard_fifo": false + }, + "smbus_feature": { + "use_register_callback": false, + "user_data": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "get_last_errors": false + }, + "spi_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_spi_crc": false, + "use_hal_spi_dma": false + }, + "tim_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_tim_dma": false + }, + "uart_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_uart_dma": false + }, + "usart_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_usart_dma": false, + "use_hal_usart_fifo": false + }, + "wwdg_feature": { + "use_register_callback": false, + "user_data": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_wwdg_time_unit": "HAL_WWDG_TIME_UNIT_MS", + "use_hal_wwdg_hardware_start": false + }, + "xspi_feature": { + "use_register_callback": false, + "user_data": false, + "get_last_errors": false, + "clk_enable_model": "HAL_CLK_ENABLE_NO", + "use_hal_xspi_dma": false, + "use_hal_xspi_hyperbus": false + } + } + } + } + ], + "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:CORTEX MPU@2.1.0#HAL CORE Init and CORTEX": [ + { + "index": 1, + "instanceId": "afd5b53f-f251-40b2-ad99-0e48c1139af5", + "name": "MyCORTEX_MPU_1", + "entity": "peripheral.cortex_mpu", + "settings": { + "parameters": { + "info": { + "labels": [], + "layer": "HAL", + "init_type": "called", + "note": "MPU default configuration:\\n\\nBecause the instruction cache is enabled, the MPU must be enabled with the OTP/RO data area defined as a non-cacheable read-only region (0x08FF FE00-0x08FF FFFF range cover the full area) if the region is effectively used" + }, + "basic": { + "mpu_enabled": true, + "default_map_enabled": true, + "during_hardfault": false, + "enable_mem_management_fault": true + }, + "additional": { + "attributes": [ + { + "_foreignKey": "ATTR_0", + "memory_type": "NORMAL", + "write_policy": "NCACHEABLE" + }, + { + "_foreignKey": "ATTR_1", + "memory_type": "DEVICE", + "device_attribute": "NGNRNE" + }, + { + "_foreignKey": "ATTR_2", + "memory_type": "DEVICE", + "device_attribute": "NGNRNE" + }, + { + "_foreignKey": "ATTR_3", + "memory_type": "DEVICE", + "device_attribute": "NGNRNE" + }, + { + "_foreignKey": "ATTR_4", + "memory_type": "DEVICE", + "device_attribute": "NGNRNE" + }, + { + "_foreignKey": "ATTR_5", + "memory_type": "DEVICE", + "device_attribute": "NGNRNE" + }, + { + "_foreignKey": "ATTR_6", + "memory_type": "DEVICE", + "device_attribute": "NGNRNE" + }, + { + "_foreignKey": "ATTR_7", + "memory_type": "DEVICE", + "device_attribute": "NGNRNE" + } + ], + "regions": [ + { + "_foreignKey": "REGION_0", + "access_permission": "ALL_RO", + "attribute_number": 0, + "base_address": 150986752, + "instruction_access": false, + "limit_address": 150994943, + "use_region": true + }, + { + "_foreignKey": "REGION_1", + "access_permission": "ONLY_PRIV_RW", + "attribute_number": 0, + "base_address": 0, + "instruction_access": true, + "limit_address": 31, + "use_region": false + }, + { + "_foreignKey": "REGION_2", + "access_permission": "ONLY_PRIV_RW", + "attribute_number": 0, + "base_address": 0, + "instruction_access": true, + "limit_address": 31, + "use_region": false + }, + { + "_foreignKey": "REGION_3", + "access_permission": "ONLY_PRIV_RW", + "attribute_number": 0, + "base_address": 0, + "instruction_access": true, + "limit_address": 31, + "use_region": false + }, + { + "_foreignKey": "REGION_4", + "access_permission": "ONLY_PRIV_RW", + "attribute_number": 0, + "base_address": 0, + "instruction_access": true, + "limit_address": 31, + "use_region": false + }, + { + "_foreignKey": "REGION_5", + "access_permission": "ONLY_PRIV_RW", + "attribute_number": 0, + "base_address": 0, + "instruction_access": true, + "limit_address": 31, + "use_region": false + }, + { + "_foreignKey": "REGION_6", + "access_permission": "ONLY_PRIV_RW", + "attribute_number": 0, + "base_address": 0, + "instruction_access": true, + "limit_address": 31, + "use_region": false + }, + { + "_foreignKey": "REGION_7", + "access_permission": "ONLY_PRIV_RW", + "attribute_number": 0, + "base_address": 0, + "instruction_access": true, + "limit_address": 31, + "use_region": false + } + ] + } + } + } + } + ], + "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ICACHE@2.1.0#HAL CORE Init and ICACHE": [ + { + "index": 2, + "instanceId": "93d223f4-db9b-4dea-94d0-2ff16c085039", + "name": "MyICACHE_1", + "entity": "peripheral.icache", + "settings": { + "parameters": { + "info": { + "labels": [], + "layer": "HAL", + "init_type": "called" + }, + "basic": { + "associativity_mode": "2WAYS" + }, + "additional": { + "remap_regions": [ + { + "_foreignKey": "REGION_0", + "base_address": 0, + "master_port": 1, + "output_burst": "WRAP", + "remap_address": 0, + "size": 2, + "use_region": false + }, + { + "_foreignKey": "REGION_1", + "base_address": 0, + "master_port": 1, + "output_burst": "WRAP", + "remap_address": 0, + "size": 2, + "use_region": false + }, + { + "_foreignKey": "REGION_2", + "base_address": 0, + "master_port": 1, + "output_burst": "WRAP", + "remap_address": 0, + "size": 2, + "use_region": false + }, + { + "_foreignKey": "REGION_3", + "base_address": 0, + "master_port": 1, + "output_burst": "WRAP", + "remap_address": 0, + "size": 2, + "use_region": false + } + ], + "monitors": { + "hit_monitor": false, + "miss_monitor": false + } + }, + "system": { + "nvic": { + "enable_interruption": false, + "chose_error_interrupt": { + "cache_error": false + } + } + } + } + } + } + ], + "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:RCC@2.1.0#HAL CORE Init GPIO and RCC": [ + { + "index": 3, + "instanceId": "abca66f8-09d5-4866-9ba0-0b2ff018ef22", + "name": "MyRCC_1", + "entity": "peripheral.rcc", + "settings": { + "parameters": { + "info": { + "labels": [], + "layer": "HAL", + "init_type": "called" + }, + "basic": { + "periph_clocks_init": 0, + "flash_latency": 4, + "flash_programming_delay": 2, + "hse": { + "state": "OFF", + "enable_css": false, + "startup_time": 100 + }, + "lse": { + "state": "OFF", + "drive_capability": "LOW", + "enable_css": false, + "startup_time": 5000 + }, + "system_clock_frequency": "100 MHz" + }, + "additional": { + "hsi": { + "enable_in_stop_mode": false + }, + "psi": { + "enable_in_stop_mode": false + }, + "clk_outputs": { + "lsco": false, + "mco1": false, + "mco2": false + }, + "audio_clock": { + "enable": false + } + }, + "system": { + "gpio": {}, + "exti": {}, + "nvic": {} + } + } + } + } + ], + "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:CORTEX NVIC@2.1.0#HAL CORE Init and CORTEX": [ + { + "index": 4, + "instanceId": "afeed797-5f6c-45ad-8fd8-0affb43677e5", + "name": "MyCORTEX_NVIC_1", + "entity": "peripheral.cortex_nvic", + "settings": { + "parameters": { + "info": { + "labels": [], + "layer": "HAL", + "init_type": "called" + }, + "additional": { + "enable_exception_debugmon": false + }, + "system": { + "nvic": { + "enable_exception_debugmon": false, + "enable_management_pendsv": false, + "enable_management_svc": false + } + } + } + } + } + ], + "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:System@2.1.0#HAL System Init": [ + { + "index": 5, + "instanceId": "556db68c-8974-4b5e-8151-3f0dd4dc1905", + "name": "MySystem_1", + "entity": "globalProjectComponent", + "settings": { + "parameters": { + "system_configuration": { + "icache_enable": true, + "rcc_rst": false, + "use_vdd_value": false + }, + "generated_function_calls_not_ranked": [ + { + "_foreignKey": "MPU", + "callable": true, + "generated": true, + "hw_instance": "MPU", + "layer": "HAL", + "mode": "", + "name": "mx_cortex_mpu_init", + "peripheral": "CORTEX MPU" + }, + { + "_foreignKey": "NVIC", + "callable": true, + "generated": true, + "hw_instance": "NVIC", + "layer": "HAL", + "mode": "", + "name": "mx_cortex_nvic_init", + "peripheral": "CORTEX NVIC" + }, + { + "_foreignKey": "ICACHE", + "callable": true, + "generated": true, + "hw_instance": "ICACHE", + "layer": "HAL", + "mode": "", + "name": "mx_icache_init", + "peripheral": "ICACHE" + }, + { + "_foreignKey": "RCC", + "callable": true, + "generated": true, + "hw_instance": "RCC", + "layer": "HAL", + "mode": "", + "name": "mx_rcc_init", + "peripheral": "RCC" + } + ], + "generated_function_calls": [ + { + "_foreignKey": "ETH1", + "_rank": 0, + "callable": true, + "generated": true, + "hw_instance": "ETH1", + "layer": "HAL", + "mode": "", + "name": "mx_eth1_init", + "peripheral": "ETH" + }, + { + "_foreignKey": "USART2", + "_rank": 1, + "callable": true, + "generated": true, + "hw_instance": "USART2", + "layer": "HAL", + "mode": "UART", + "name": "mx_usart2_uart_init", + "peripheral": "UART" + }, + { + "_foreignKey": "RNG", + "_rank": 2, + "callable": true, + "generated": true, + "hw_instance": "RNG", + "layer": "HAL", + "mode": "", + "name": "mx_rng_init", + "peripheral": "RNG" + } + ], + "code_generation": { + "optim_enable": true, + "strategy": "HW", + "exti_callback_user_data": false + }, + "debug": { + "assert_dbg_param": false, + "assert_dbg_state": false + } + } + } + } + ], + "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH": [ + { + "index": 6, + "instanceId": "e893f130-3ec1-4220-a100-81c772646223", + "entity": "peripheral.eth", + "settings": { + "parameters": { + "info": { + "labels": [], + "layer": "HAL", + "init_type": "called" + }, + "basic": { + "media_interface": "HAL_ETH_MEDIA_IF_RMII", + "mac_addr_auto_generation": false, + "eth_mac_config": { + "speed": "HAL_ETH_MAC_SPEED_100M", + "duplex_mode": "HAL_ETH_MAC_FULL_DUPLEX_MODE", + "loopback_mode": false + }, + "eth_kernel_clock_frequency": "100 MHz", + "eth_kernel_clock_source": "PSI", + "mac_addr": "02:03:04:05:06:07", + "max_rx_ch_nb": 1, + "max_tx_ch_nb": 1 + }, + "additional": { + "enable_wakeup_interrupt": false, + "enable_phy_interrupt": false + }, + "system": { + "gpio": { + "gpio_eth_clk": { + "needs": [ + { + "needType": "need.pinout.signals", + "projectUri": "cube:96bb7bee-0b22-446f-9659-deebecd050dd/221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "selector": "CLK", + "id": "a44c6644-8105-4568-b133-6f5460c4e284", + "owner": "ETH1", + "constraints": { + "pull": { + "allow": [ + "UP", + "NO" + ] + }, + "mode": { + "const": "ALTERNATE" + }, + "output_type": { + "const": "PUSHPULL" + }, + "speed": { + "default": "HIGH" + } + } + } + ] + }, + "gpio_eth_mdc": { + "needs": [ + { + "needType": "need.pinout.signals", + "projectUri": "cube:96bb7bee-0b22-446f-9659-deebecd050dd/221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "selector": "MDC", + "id": "329c25dd-00b0-4e04-b8cc-d4c32be7bc4d", + "owner": "ETH1", + "constraints": { + "pull": { + "allow": [ + "UP", + "NO" + ] + }, + "mode": { + "const": "ALTERNATE" + }, + "output_type": { + "const": "PUSHPULL" + }, + "speed": { + "default": "HIGH" + } + } + } + ] + }, + "gpio_eth_mdio": { + "needs": [ + { + "needType": "need.pinout.signals", + "projectUri": "cube:96bb7bee-0b22-446f-9659-deebecd050dd/221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "selector": "MDIO", + "id": "39260779-e45c-4009-a6b2-d3975febf9bc", + "owner": "ETH1", + "constraints": { + "pull": { + "allow": [ + "UP", + "NO" + ] + }, + "mode": { + "const": "ALTERNATE" + }, + "output_type": { + "const": "PUSHPULL" + }, + "speed": { + "default": "HIGH" + } + } + } + ] + }, + "gpio_rmii_crs_dv": { + "needs": [ + { + "needType": "need.pinout.signals", + "projectUri": "cube:96bb7bee-0b22-446f-9659-deebecd050dd/221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "selector": "RMII_CRS_DV", + "id": "0d47429e-1e88-4897-8f7d-f576bafbfcad", + "owner": "ETH1", + "constraints": { + "pull": { + "allow": [ + "UP", + "NO" + ] + }, + "mode": { + "const": "ALTERNATE" + }, + "output_type": { + "const": "PUSHPULL" + }, + "speed": { + "default": "HIGH" + } + } + } + ] + }, + "gpio_rmii_ref_clk": { + "needs": [ + { + "needType": "need.pinout.signals", + "projectUri": "cube:96bb7bee-0b22-446f-9659-deebecd050dd/221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "selector": "RMII_REF_CLK", + "id": "51aca76f-47bb-485c-87c2-5799f42218d3", + "owner": "ETH1", + "constraints": { + "pull": { + "allow": [ + "UP", + "NO" + ] + }, + "mode": { + "const": "ALTERNATE" + }, + "output_type": { + "const": "PUSHPULL" + }, + "speed": { + "default": "HIGH" + } + } + } + ] + }, + "gpio_rmii_rxd0": { + "needs": [ + { + "needType": "need.pinout.signals", + "projectUri": "cube:96bb7bee-0b22-446f-9659-deebecd050dd/221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "selector": "RMII_RXD0", + "id": "5e86a142-c9fe-4265-bd92-c6b00306b9ba", + "owner": "ETH1", + "constraints": { + "pull": { + "allow": [ + "UP", + "NO" + ] + }, + "mode": { + "const": "ALTERNATE" + }, + "output_type": { + "const": "PUSHPULL" + }, + "speed": { + "default": "HIGH" + } + } + } + ] + }, + "gpio_rmii_rxd1": { + "needs": [ + { + "needType": "need.pinout.signals", + "projectUri": "cube:96bb7bee-0b22-446f-9659-deebecd050dd/221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "selector": "RMII_RXD1", + "id": "c261a5df-a938-4475-96d2-440e231ac5fc", + "owner": "ETH1", + "constraints": { + "pull": { + "allow": [ + "UP", + "NO" + ] + }, + "mode": { + "const": "ALTERNATE" + }, + "output_type": { + "const": "PUSHPULL" + }, + "speed": { + "default": "HIGH" + } + } + } + ] + }, + "gpio_rmii_tx_en": { + "needs": [ + { + "needType": "need.pinout.signals", + "projectUri": "cube:96bb7bee-0b22-446f-9659-deebecd050dd/221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "selector": "RMII_TX_EN", + "id": "c8cffdd2-1e94-476a-90d2-69825b94c111", + "owner": "ETH1", + "constraints": { + "pull": { + "allow": [ + "UP", + "NO" + ] + }, + "mode": { + "const": "ALTERNATE" + }, + "output_type": { + "const": "PUSHPULL" + }, + "speed": { + "default": "HIGH" + } + } + } + ] + }, + "gpio_rmii_txd0": { + "needs": [ + { + "needType": "need.pinout.signals", + "projectUri": "cube:96bb7bee-0b22-446f-9659-deebecd050dd/221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "selector": "RMII_TXD0", + "id": "e76a1909-4977-4289-8139-57129d0f91db", + "owner": "ETH1", + "constraints": { + "pull": { + "allow": [ + "UP", + "NO" + ] + }, + "mode": { + "const": "ALTERNATE" + }, + "output_type": { + "const": "PUSHPULL" + }, + "speed": { + "default": "HIGH" + } + } + } + ] + }, + "gpio_rmii_txd1": { + "needs": [ + { + "needType": "need.pinout.signals", + "projectUri": "cube:96bb7bee-0b22-446f-9659-deebecd050dd/221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0#HAL CORE GPIO Init and ETH", + "componentInstanceId": "e893f130-3ec1-4220-a100-81c772646223", + "selector": "RMII_TXD1", + "id": "63f2ffe7-3f41-4ab6-af6e-dcb1dd3c04bc", + "owner": "ETH1", + "constraints": { + "pull": { + "allow": [ + "UP", + "NO" + ] + }, + "mode": { + "const": "ALTERNATE" + }, + "output_type": { + "const": "PUSHPULL" + }, + "speed": { + "default": "HIGH" + } + } + } + ] + } + }, + "exti": {}, + "nvic": { + "enable_global_interrupt": false + } + }, + "eth_rx_channels": [ + { + "_foreignKey": 0, + "use_channel": true, + "additional": { + "dma_channel_config": { + "rx_dma_burst_length": "HAL_ETH_DMA_RX_BLEN_4_BEAT" + }, + "mtl_queue_config": { + "queue_size_byte": "HAL_ETH_MTL_RX_QUEUE_SZ_2048_BYTE", + "receive_queue_mode": "HAL_ETH_MTL_RX_Q_STORE_AND_FORWARD", + "drop_tcp_ip_csum_error_pkt": true, + "fwd_error_pkt": false, + "fwd_undersized_good_pkt": true + } + }, + "basic": { + "max_app_buffers_num": 4, + "event_mode": "HAL_ETH_FIFO_EVENT_ALWAYS", + "rx_buffer_len_byte": 1528 + }, + "labels": [] + } + ], + "eth_tx_channels": [ + { + "_foreignKey": 0, + "use_channel": true, + "additional": { + "dma_channel_config": { + "tx_dma_burst_length": "HAL_ETH_DMA_TX_BLEN_4_BEAT", + "tx_pbl_x8_mode": false, + "tx_second_pkt_operate": true + }, + "mtl_queue_config": { + "queue_size_byte": "HAL_ETH_MTL_TX_QUEUE_SZ_2048_BYTE", + "transmit_queue_mode": "HAL_ETH_MTL_TX_Q_STORE_AND_FORWARD" + } + }, + "basic": { + "max_app_buffers_num": 4, + "event_mode": "HAL_ETH_FIFO_EVENT_ALWAYS" + }, + "labels": [] + } + ] + } + } + } + ], + "Cesanta.I-CUBE-Mongoose.7.23.2$Cesanta::Mongoose:Networking Core@7.23.2": [ + { + "index": 7, + "instanceId": "5ad405e9-fc54-4262-a8d4-016aa2770014", + "entity": "unknown", + "settings": { + "parameters": { + "info": { + "description": "Mongoose networking library: TCP/IP, TLS, HTTP, WebSocket, MQTT, OTA. Edit mongoose_config.h to configure it." + } + } + } + } + ], + "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:UART@2.1.0#HAL CORE GPIO DMA Init and UART": [ + { + "index": 8, + "instanceId": "ab2835f4-2315-4ff0-a788-1ca59e8cdd6c", + "entity": "peripheral.usart", + "settings": { + "parameters": { + "info": { + "labels": [], + "layer": "HAL", + "init_type": "called", + "function_type": "UART" + }, + "basic": { + "mode": "async", + "baud_rate": 115200, + "word_length": "8", + "parity": "NONE", + "stop_bit": "1", + "direction": "TX_RX", + "hw_flow_ctl": "NONE" + }, + "additional": { + "over_sampling": "16", + "one_bit_sampling": false, + "clock_prescaler": 1, + "enable_stop_mode": false, + "enable_tx_pin_level_invert": false, + "enable_rx_pin_level_invert": false, + "enable_data_invert": false, + "enable_tx_rx_swap": false, + "enable_msb_first": false, + "enable_dma_stop_on_rx_error": false, + "enable_fifo_mode": false, + "enable_receiver_timeout": false, + "enable_rs485_mode": false, + "rx_over_run_detection": true, + "set_config_auto_baud_rate": "DISABLE" + }, + "system": { + "gpio": { + "gpio_rx": { + "needs": [ + { + "needType": "need.pinout.signals", + "projectUri": "cube:96bb7bee-0b22-446f-9659-deebecd050dd/221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:UART@2.1.0#HAL CORE GPIO DMA Init and UART", + "componentInstanceId": "ab2835f4-2315-4ff0-a788-1ca59e8cdd6c", + "selector": "RX", + "id": "1ba77734-c758-432d-9d85-dec0a00bf03e", + "owner": "USART2", + "constraints": { + "mode": { + "const": "ALTERNATE" + } + } + } + ] + }, + "gpio_tx": { + "needs": [ + { + "needType": "need.pinout.signals", + "projectUri": "cube:96bb7bee-0b22-446f-9659-deebecd050dd/221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "componentId": "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:UART@2.1.0#HAL CORE GPIO DMA Init and UART", + "componentInstanceId": "ab2835f4-2315-4ff0-a788-1ca59e8cdd6c", + "selector": "TX", + "id": "3130abee-7578-4f30-a825-c241a4f93b31", + "owner": "USART2", + "constraints": { + "mode": { + "const": "ALTERNATE" + } + } + } + ] + } + }, + "dma": { + "enable_dma_rx": false, + "enable_dma_tx": false + }, + "nvic": { + "enable_interruption": false + } + } + } + } + } + ], + "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32CubeMX2 Config:RNG@2.1.0#HAL CORE Init and RNG": [ + { + "index": 9, + "instanceId": "fca73b1f-d8c4-4faa-a69f-3b2f381a9466", + "entity": "peripheral.rng", + "settings": { + "parameters": { + "info": { + "labels": [], + "layer": "HAL", + "init_type": "called" + }, + "basic": { + "rng_standard": 1, + "rng_cand_nist_cr": 1048832, + "rng_cand_nist_htcr": 43719, + "rng_cand_nist_nscr": 511 + }, + "additional": { + "enable_clock_error_detection": false, + "enable_auto_reset": false + }, + "system": { + "nvic": { + "enable_interruption": false + } + } + } + } + } + ], + "STMicroelectronics.stm32c5xx_hal_drivers.2.1.0$STMicroelectronics::Device:STM32 LL:GPIO@2.1.0#LL": [ + { + "index": 0, + "needId": "a44c6644-8105-4568-b133-6f5460c4e284", + "rootId": "e893f130-3ec1-4220-a100-81c772646223", + "needType": "need.pinout.signals", + "parentId": "e893f130-3ec1-4220-a100-81c772646223", + "settings": { + "label_name": [], + "basic": { + "mode": "ALTERNATE", + "pull": "NO", + "enable_exti": false, + "output_type": "PUSHPULL", + "speed": "HIGH" + } + } + }, + { + "index": 1, + "needId": "329c25dd-00b0-4e04-b8cc-d4c32be7bc4d", + "rootId": "e893f130-3ec1-4220-a100-81c772646223", + "needType": "need.pinout.signals", + "parentId": "e893f130-3ec1-4220-a100-81c772646223", + "settings": { + "label_name": [], + "basic": { + "mode": "ALTERNATE", + "pull": "NO", + "enable_exti": false, + "output_type": "PUSHPULL", + "speed": "HIGH" + } + } + }, + { + "index": 2, + "needId": "39260779-e45c-4009-a6b2-d3975febf9bc", + "rootId": "e893f130-3ec1-4220-a100-81c772646223", + "needType": "need.pinout.signals", + "parentId": "e893f130-3ec1-4220-a100-81c772646223", + "settings": { + "label_name": [], + "basic": { + "mode": "ALTERNATE", + "pull": "NO", + "enable_exti": false, + "output_type": "PUSHPULL", + "speed": "HIGH" + } + } + }, + { + "index": 3, + "needId": "0d47429e-1e88-4897-8f7d-f576bafbfcad", + "rootId": "e893f130-3ec1-4220-a100-81c772646223", + "needType": "need.pinout.signals", + "parentId": "e893f130-3ec1-4220-a100-81c772646223", + "settings": { + "label_name": [], + "basic": { + "mode": "ALTERNATE", + "pull": "NO", + "enable_exti": false, + "output_type": "PUSHPULL", + "speed": "HIGH" + } + } + }, + { + "index": 4, + "needId": "51aca76f-47bb-485c-87c2-5799f42218d3", + "rootId": "e893f130-3ec1-4220-a100-81c772646223", + "needType": "need.pinout.signals", + "parentId": "e893f130-3ec1-4220-a100-81c772646223", + "settings": { + "label_name": [], + "basic": { + "mode": "ALTERNATE", + "pull": "NO", + "enable_exti": false, + "output_type": "PUSHPULL", + "speed": "HIGH" + } + } + }, + { + "index": 5, + "needId": "5e86a142-c9fe-4265-bd92-c6b00306b9ba", + "rootId": "e893f130-3ec1-4220-a100-81c772646223", + "needType": "need.pinout.signals", + "parentId": "e893f130-3ec1-4220-a100-81c772646223", + "settings": { + "label_name": [], + "basic": { + "mode": "ALTERNATE", + "pull": "NO", + "enable_exti": false, + "output_type": "PUSHPULL", + "speed": "HIGH" + } + } + }, + { + "index": 6, + "needId": "c261a5df-a938-4475-96d2-440e231ac5fc", + "rootId": "e893f130-3ec1-4220-a100-81c772646223", + "needType": "need.pinout.signals", + "parentId": "e893f130-3ec1-4220-a100-81c772646223", + "settings": { + "label_name": [], + "basic": { + "mode": "ALTERNATE", + "pull": "NO", + "enable_exti": false, + "output_type": "PUSHPULL", + "speed": "HIGH" + } + } + }, + { + "index": 7, + "needId": "c8cffdd2-1e94-476a-90d2-69825b94c111", + "rootId": "e893f130-3ec1-4220-a100-81c772646223", + "needType": "need.pinout.signals", + "parentId": "e893f130-3ec1-4220-a100-81c772646223", + "settings": { + "label_name": [], + "basic": { + "mode": "ALTERNATE", + "pull": "NO", + "enable_exti": false, + "output_type": "PUSHPULL", + "speed": "HIGH" + } + } + }, + { + "index": 8, + "needId": "e76a1909-4977-4289-8139-57129d0f91db", + "rootId": "e893f130-3ec1-4220-a100-81c772646223", + "needType": "need.pinout.signals", + "parentId": "e893f130-3ec1-4220-a100-81c772646223", + "settings": { + "label_name": [], + "basic": { + "mode": "ALTERNATE", + "pull": "NO", + "enable_exti": false, + "output_type": "PUSHPULL", + "speed": "HIGH" + } + } + }, + { + "index": 9, + "needId": "63f2ffe7-3f41-4ab6-af6e-dcb1dd3c04bc", + "rootId": "e893f130-3ec1-4220-a100-81c772646223", + "needType": "need.pinout.signals", + "parentId": "e893f130-3ec1-4220-a100-81c772646223", + "settings": { + "label_name": [], + "basic": { + "mode": "ALTERNATE", + "pull": "NO", + "enable_exti": false, + "output_type": "PUSHPULL", + "speed": "HIGH" + } + } + }, + { + "index": 10, + "needId": "1ba77734-c758-432d-9d85-dec0a00bf03e", + "rootId": "ab2835f4-2315-4ff0-a788-1ca59e8cdd6c", + "needType": "need.pinout.signals", + "parentId": "ab2835f4-2315-4ff0-a788-1ca59e8cdd6c", + "settings": { + "label_name": [], + "basic": { + "mode": "ALTERNATE", + "pull": "NO", + "enable_exti": false, + "output_type": "PUSHPULL", + "speed": "LOW" + } + } + }, + { + "index": 11, + "needId": "3130abee-7578-4f30-a825-c241a4f93b31", + "rootId": "ab2835f4-2315-4ff0-a788-1ca59e8cdd6c", + "needType": "need.pinout.signals", + "parentId": "ab2835f4-2315-4ff0-a788-1ca59e8cdd6c", + "settings": { + "label_name": [], + "basic": { + "mode": "ALTERNATE", + "pull": "NO", + "enable_exti": false, + "output_type": "PUSHPULL", + "speed": "LOW" + } + } + } + ] + }, + "version": 2 + } +}""" +"File: project/c5.cproject.yml" = """ +# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/2.11.0/tools/projmgr/schemas/cproject.schema.json +project: + processor: + trustzone: off + dsp: on + rte: + base-dir: $ProjectDir()$/user_modifiable + generators: + base-dir: generated + output: + base-name: $Project$ + type: + - elf + - bin + - hex + setups: + - setup: release_IAR + misc: + - C: + - --debug + - -Ohz + - --dlib_config DLib_Config_Full.h + - --no_wrap_diagnostics + - --vla + - --enable_restrict + - -e + - --require_prototypes + CPP: + - --debug + - -Ohz + - --dlib_config DLib_Config_Full.h + - --no_wrap_diagnostics + - --vla + - --enable_restrict + - -e + - --require_prototypes + for-compiler: IAR + Link-C: + - --skip_dynamic_initialization + - --inline + - --map=$Project$.$BuildType$+$TargetType$.map + for-context: + - .release_IAR + - setup: release_GCC + misc: + - ASM: + - --specs=nano.specs + - --specs=nosys.specs + C: + - -Os + - -fdata-sections + - -ffunction-sections + - -std=gnu11 + - -Wall + - -fstack-usage + - --specs=nano.specs + - --specs=nosys.specs + - -g + - -Werror=implicit-function-declaration + CPP: + - -Os + - -fdata-sections + - -ffunction-sections + - -fno-cxa-atexit + - -fno-rtti + - -fno-exceptions + - -std=gnu++14 + - -Wall + - -fstack-usage + - --specs=nano.specs + - --specs=nosys.specs + - -g + - -Werror=implicit-function-declaration + for-compiler: GCC + Link-C: + - -Wl,-Map=$OutDir()$/$Project$.map + - -Wl,--gc-sections + - -Wl,--start-group -lc -lm -Wl,--end-group + - -static + - --specs=nano.specs + - --specs=nosys.specs + Link-CPP: + - -Wl,-Map=$OutDir()$/$Project$.map + - -Wl,--gc-sections + - -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group + - -static + - --specs=nano.specs + - --specs=nosys.specs + for-context: + - .release_GCC + - setup: debug_GCC + misc: + - ASM: + - -g3 + - --specs=nano.specs + - --specs=nosys.specs + C: + - -g3 + - -O0 + - -fdata-sections + - -ffunction-sections + - -std=gnu11 + - -Wall + - -fstack-usage + - --specs=nano.specs + - --specs=nosys.specs + - -Werror=implicit-function-declaration + CPP: + - -g3 + - -O0 + - -fdata-sections + - -ffunction-sections + - -fno-cxa-atexit + - -fno-rtti + - -fno-exceptions + - -std=gnu++14 + - -Wall + - -fstack-usage + - --specs=nano.specs + - --specs=nosys.specs + - -Werror=implicit-function-declaration + for-compiler: GCC + Link-C: + - -Wl,-Map=$OutDir()$/$Project$.map + - -Wl,--gc-sections + - -Wl,--start-group -lc -lm -Wl,--end-group + - -static + - --specs=nano.specs + - --specs=nosys.specs + Link-CPP: + - -Wl,-Map=$OutDir()$/$Project$.map + - -Wl,--gc-sections + - -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group + - -static + - --specs=nano.specs + - --specs=nosys.specs + for-context: + - .debug_GCC + - setup: release_AC6 + misc: + - ASM: + - -Oz + - -g + C: + - -Oz + - -std=gnu11 + - -fno-exceptions + - -fno-rtti + - -funsigned-char + - -g + - -Wmissing-prototypes + CPP: + - -Oz + - -std=gnu++14 + - -fno-exceptions + - -fno-rtti + - -funsigned-char + - -g + - -Wmissing-prototypes + for-compiler: AC6 + Link-C: + - --map + - --library_type=microlib + - --symbols + - --show_full_path + - --inline + - --any_contingency + Link-CPP: + - --library_type=microlib + - --symbols + - --map + - --show_full_path + - --inline + - --any_contingency + for-context: + - .release_AC6 + - setup: debug_AC6 + misc: + - ASM: + - -g + - -O0 + C: + - -g + - -O0 + - -std=gnu11 + - -fno-exceptions + - -fno-rtti + - -funsigned-char + - -Wmissing-prototypes + CPP: + - -g + - -O0 + - -std=gnu++14 + - -fno-exceptions + - -fno-rtti + - -funsigned-char + - -Wmissing-prototypes + for-compiler: AC6 + Link-C: + - --map + - --library_type=microlib + - --symbols + - --show_full_path + - --inline + - --any_contingency + Link-CPP: + - --library_type=microlib + - --symbols + - --map + - --show_full_path + - --inline + - --any_contingency + for-context: + - .debug_AC6 + - setup: debug_IAR + misc: + - C: + - --debug + - -On + - --dlib_config DLib_Config_Full.h + - --no_wrap_diagnostics + - --vla + - --enable_restrict + - -e + - --require_prototypes + CPP: + - --debug + - -On + - --dlib_config DLib_Config_Full.h + - --no_wrap_diagnostics + - --vla + - --enable_restrict + - -e + - --require_prototypes + for-compiler: IAR + Link-C: + - --skip_dynamic_initialization + - --inline + - --map=$Project$.$BuildType$+$TargetType$.map + for-context: + - .debug_IAR + components: + - component: Cesanta::Mongoose:Networking Core@7.23.2 + - component: STMicroelectronics::Application:stm32cubemx2_templates&no os@2.1.0 + - component: STMicroelectronics::CMSIS:CORE@6.2.0 + - component: STMicroelectronics::Device:Startup@2.1.0 + - component: STMicroelectronics::Device:STM32 HAL:Core@2.0.0 + - component: STMicroelectronics::Device:STM32 HAL:CORTEX@2.0.0 + - component: STMicroelectronics::Device:STM32 HAL:DMA@2.1.0 + - component: STMicroelectronics::Device:STM32 HAL:ETH@2.1.0 + - component: STMicroelectronics::Device:STM32 HAL:FLASH_ITF@2.1.0 + - component: STMicroelectronics::Device:STM32 HAL:GPIO@2.1.0 + - component: STMicroelectronics::Device:STM32 HAL:ICACHE@2.1.0 + - component: STMicroelectronics::Device:STM32 HAL:PWR@2.0.1 + - component: STMicroelectronics::Device:STM32 HAL:Q@2.0.0 + - component: STMicroelectronics::Device:STM32 HAL:RCC@2.0.0 + - component: STMicroelectronics::Device:STM32 HAL:RNG@2.0.0 + - component: STMicroelectronics::Device:STM32 HAL:timebases&SYSTICK@2.0.0 + - component: STMicroelectronics::Device:STM32 HAL:UART@2.0.1 + - component: STMicroelectronics::Device:STM32 LL:BUS@2.0.1 + - component: STMicroelectronics::Device:STM32 LL:Common@2.0.0 + - component: STMicroelectronics::Device:STM32 LL:DMA@2.1.0 + - component: STMicroelectronics::Device:STM32 LL:EXTI@2.1.0 + - component: STMicroelectronics::Device:STM32 LL:FLASH@2.1.0 + - component: STMicroelectronics::Device:STM32 LL:GPIO@2.1.0 + - component: STMicroelectronics::Device:STM32 LL:ICACHE@2.0.0 + - component: STMicroelectronics::Device:STM32 LL:PWR@2.0.0 + - component: STMicroelectronics::Device:STM32 LL:RCC@2.0.0 + - component: STMicroelectronics::Device:STM32 LL:RNG@2.0.0 + - component: STMicroelectronics::Device:STM32 LL:SBS@2.0.0 + - component: STMicroelectronics::Device:STM32 LL:USART@2.0.0 + - component: STMicroelectronics::Device:STM32 LL:UTILS@2.0.0 + - component: STMicroelectronics::Device:STM32CubeMX2 Codegen:Generated Code@2.0.0 + - component: STMicroelectronics::Device:STM32CubeMX2 Config:CORE@2.1.0 + - component: STMicroelectronics::Device:STM32CubeMX2 Config:CORTEX MPU@2.1.0 + - component: STMicroelectronics::Device:STM32CubeMX2 Config:CORTEX NVIC@2.1.0 + - component: STMicroelectronics::Device:STM32CubeMX2 Config:ETH@2.1.0 + - component: STMicroelectronics::Device:STM32CubeMX2 Config:ICACHE@2.1.0 + - component: STMicroelectronics::Device:STM32CubeMX2 Config:RCC@2.1.0 + - component: STMicroelectronics::Device:STM32CubeMX2 Config:RNG@2.1.0 + - component: STMicroelectronics::Device:STM32CubeMX2 Config:System@2.1.0 + - component: STMicroelectronics::Device:STM32CubeMX2 Config:UART@2.1.0 +""" +"File: project/project.cube" = """ +{ + "traits": [ + { + "id": "221b8ddd-b2b7-4a03-94c0-e5989cd20a84", + "name": "component", + "files": [ + "c5.cproject.yml" + ] + } + ], + "children": [] +}""" + +["Project Description"] +workingAreaId = "50b35702-3fcd-40ea-a923-c04282badfbe" +version = "1" +mx2Version = "1.1.2" diff --git a/tutorials/stm32/nucleo-c5a3zg/minimal/Makefile b/tutorials/stm32/nucleo-c5a3zg/minimal/Makefile new file mode 100644 index 00000000..042ab464 --- /dev/null +++ b/tutorials/stm32/nucleo-c5a3zg/minimal/Makefile @@ -0,0 +1,46 @@ +# Copyright (c) 2026 Cesanta Software Limited +# Environment setup: https://mongoose.ws/docs/getting-started/build-environment/ + +MGDIR = ../../../.. + +CFLAGS = -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion +CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion +CFLAGS += -g3 -Os -ffunction-sections -fdata-sections +CFLAGS += -I. -I$(MGDIR) -Icmsis_core/CMSIS/Core/Include -Icmsis_c5/Include -DSTM32C5A3xx +CFLAGS += -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard $(CFLAGS_EXTRA) +LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections + +SOURCES = main.c hal.c +SOURCES += cmsis_c5/Source/startup_stm32c5a3xx.c +SOURCES += $(MGDIR)/mongoose.c + +all build example: firmware.bin + +firmware.elf: cmsis_core cmsis_c5 hal.h link.ld Makefile $(SOURCES) $(MGDIR)/mongoose.h mongoose_config.h + arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(CFLAGS_EXTRA) $(LDFLAGS) -o $@ + +firmware.bin: firmware.elf + arm-none-eabi-objcopy -O binary $< $@ + @echo + @echo "To flash, run 'make flash', or use STM32CubeProgrammer" + +firmware.signed.bin: firmware.bin + test -f private.pem || node $(MGDIR)/resources/sign.js keygen + node $(MGDIR)/resources/sign.js sign firmware.bin + +# Show all symbols sorted by size +show_symbols_sorted_by_size: firmware.bin + arm-none-eabi-readelf -sW firmware.elf | sed 1,3d | sed 's,^.*: ,,' | tr -s ' ' | cut -d ' ' -f 2,7 | sort -nk1 | grep -v '^0 ' + +# If the board gets stuck: STM32_Programmer_CLI -c port=swd -e all mode=UR +flash: firmware.bin + STM32_Programmer_CLI -c port=swd -w firmware.elf mode=UR -rst + +cmsis_core: + git clone -q -c advice.detachedHead=false --depth 1 -b v6.4.0 https://github.com/ARM-software/CMSIS_6 $@ + +cmsis_c5: + git clone -q -c advice.detachedHead=false --depth 1 -b 2.1.0 https://github.com/STMicroelectronics/stm32c5xx-dfp $@ + +clean: + rm -rf firmware.* cmsis_* diff --git a/tutorials/stm32/nucleo-c5a3zg/minimal/hal.c b/tutorials/stm32/nucleo-c5a3zg/minimal/hal.c new file mode 100644 index 00000000..64ee7e7a --- /dev/null +++ b/tutorials/stm32/nucleo-c5a3zg/minimal/hal.c @@ -0,0 +1,141 @@ +// Copyright (c) 2026 Cesanta Software Limited +// All rights reserved + +#include "hal.h" + +// Added to minimise the bin size: avoid pulling printf and friends +void __assert_func(const char *s, int line, const char *fn, const char *expr) { + (void) s, (void) line, (void) fn, (void) expr; + for (;;) (void) 0; // or trigger the fault handler +} + +bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now) { + uint64_t diff = now - *t; // Wrap-safe elapsed time since last expiry + if (period == 0) return false; // Avoid division by zero + if (diff < period) return false; // Period has not elapsed yet + *t += (diff / period) * period; // Preserve cadence, skip missed periods + return true; +} + +static volatile uint64_t s_ticks; // Milliseconds since boot +void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms + s_ticks++; +} + +uint64_t hal_get_tick(void) { + return s_ticks; +}; + +uint32_t SystemCoreClock = 160000000; +void SystemInit(void) { // Called automatically by startup code + hal_system_init(); // Enable FPU + hal_clock_init(); + SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms +} + +void ExitRun0Mode(void) { +} + +// C library entry, called by the CMSIS startup code after it copies .data +// and clears .bss. See __cmsis_start() in cmsis_gcc_m.h +extern int main(void); +extern void __libc_init_array(void); +__attribute__((noreturn)) void _start(void) { + __libc_init_array(); + main(); + for (;;) (void) 0; +} + +struct stat; +__attribute__((weak)) int _fstat(int fd, struct stat *st) { + (void) fd, (void) st; + return -1; +} + +extern unsigned char _end[]; // End of data section, start of heap. See link.ld +static unsigned char *s_current_heap_end = _end; + +size_t hal_ram_used(void) { + return (size_t) (s_current_heap_end - _end); +} + +size_t hal_ram_free(void) { + unsigned char endofstack; + return (size_t) (&endofstack - s_current_heap_end); +} + +void *_sbrk(int incr) { + unsigned char *prev_heap; + unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256); + prev_heap = s_current_heap_end; + // Check how much space we got from the heap end to the stack end + if (s_current_heap_end + incr > heap_end) return (void *) -1; + s_current_heap_end += incr; + return prev_heap; +} + +__attribute__((weak)) int _open(const char *path) { + (void) path; + return -1; +} + +__attribute__((weak)) int _close(int fd) { + (void) fd; + return -1; +} + +__attribute__((weak)) int _isatty(int fd) { + (void) fd; + return 1; +} + +__attribute__((weak)) int _lseek(int fd, int ptr, int dir) { + (void) fd, (void) ptr, (void) dir; + return 0; +} + +__attribute__((weak)) void _exit(int status) { + (void) status; + for (;;) asm volatile("BKPT #0"); +} + +__attribute__((weak)) void _kill(int pid, int sig) { + (void) pid, (void) sig; +} + +__attribute__((weak)) int _getpid(void) { + return -1; +} + +__attribute__((weak)) int _write(int fd, char *ptr, int len) { + (void) fd, (void) ptr, (void) len; + return -1; +} + +__attribute__((weak)) int _read(int fd, char *ptr, int len) { + (void) fd, (void) ptr, (void) len; + return -1; +} + +__attribute__((weak)) int _link(const char *a, const char *b) { + (void) a, (void) b; + return -1; +} + +__attribute__((weak)) int _unlink(const char *a) { + (void) a; + return -1; +} + +__attribute__((weak)) int _stat(const char *path, struct stat *st) { + (void) path, (void) st; + return -1; +} + +__attribute__((weak)) int mkdir(const char *path, int mode) { + (void) path, (void) mode; + return -1; +} + +__attribute__((weak)) void _init(void) { +} diff --git a/tutorials/stm32/nucleo-c5a3zg/minimal/hal.h b/tutorials/stm32/nucleo-c5a3zg/minimal/hal.h new file mode 100644 index 00000000..048aa95a --- /dev/null +++ b/tutorials/stm32/nucleo-c5a3zg/minimal/hal.h @@ -0,0 +1,165 @@ +// Copyright (c) 2013-2026 Cesanta Software Limited +// Datasheet: RM0522, devboard manual: UM3616 +// https://www.st.com/resource/en/reference_manual/rm0522-stm32c5-series-armbased-32bit-mcus-stmicroelectronics.pdf +// https://www.st.com/resource/en/user_manual/um3616-stm32c5-nucleo144-board-mb2310-stmicroelectronics.pdf + +#pragma once + +#include + +#include +#include +#include +#include + +extern bool hal_timer_expired(volatile uint64_t *t, uint64_t prd, uint64_t now); +extern uint64_t hal_get_tick(void); +extern size_t hal_ram_free(void); +extern size_t hal_ram_used(void); +extern uint32_t SystemCoreClock; + +#define BIT(x) (1UL << (x)) +#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set)) +#define PIN(bank, num) ((((bank) - 'A') << 8) | (num)) +#define PINNO(pin) (pin & 255) +#define PINBANK(pin) (pin >> 8) + +// Ethernet RMII pins and their alternate functions. UM3616 7.11, Table 9 +#define HAL_ETH_PINS \ + {PIN('A', 1), 10}, /* REF_CLK */ \ + {PIN('C', 1), 10}, /* MDC */ \ + {PIN('E', 12), 10}, /* MDIO */ \ + {PIN('D', 1), 10}, /* CRS_DV */ \ + {PIN('C', 4), 12}, /* RXD0 */ \ + {PIN('C', 5), 13}, /* RXD1 */ \ + {PIN('G', 11), 10}, /* TX_EN */ \ + {PIN('G', 13), 10}, /* TXD0 */ \ + {PIN('G', 12), 10} /* TXD1 */ + +// System clock (9.4.2, 9.4.8). HSI runs at 144 MHz, the maximum system clock: +// SYSCLK = HSIS, no PLL. hclk = SYSCLK, APB clocks = hclk. After reset, the +// system runs on HSIDIV3, 48 MHz. Flash latency for 144 MHz: 6.3.6, Table 20 +#define SYS_FREQUENCY 144000000 +#define AHB_FREQUENCY SYS_FREQUENCY +#define APB2_FREQUENCY AHB_FREQUENCY +#define APB1_FREQUENCY AHB_FREQUENCY +#define HAL_FLASH_LATENCY (4 | FLASH_ACR_WRHIGHFREQ_1) // 4 WS, WRHIGHFREQ 2 + +enum { HAL_GPIO_MODE_INPUT, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_MODE_AF, HAL_GPIO_MODE_ANALOG }; +enum { HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_OTYPE_OPEN_DRAIN }; +enum { HAL_GPIO_SPEED_LOW, HAL_GPIO_SPEED_MEDIUM, HAL_GPIO_SPEED_HIGH, HAL_GPIO_SPEED_INSANE }; +enum { HAL_GPIO_PULL_NONE, HAL_GPIO_PULL_UP, HAL_GPIO_PULL_DOWN }; + +#define HAL_GPIO(N) ((GPIO_TypeDef *) (GPIOA_BASE + 0x400 * (N))) + +static GPIO_TypeDef *hal_gpio_bank(uint16_t pin) { + return HAL_GPIO(PINBANK(pin)); +} +static inline void hal_gpio_toggle(uint16_t pin) { + GPIO_TypeDef *gpio = hal_gpio_bank(pin); + uint32_t mask = BIT(PINNO(pin)); + gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0); +} +static inline int hal_gpio_read(uint16_t pin) { + return hal_gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0; +} +static inline void hal_gpio_write(uint16_t pin, bool val) { + GPIO_TypeDef *gpio = hal_gpio_bank(pin); + gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16); +} +static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type, + uint8_t speed, uint8_t pull, uint8_t af) { + GPIO_TypeDef *gpio = hal_gpio_bank(pin); + uint8_t n = (uint8_t) (PINNO(pin)); + RCC->AHB2ENR |= BIT(PINBANK(pin)); // Enable GPIO clock + CLRSET(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n); + CLRSET(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2)); + CLRSET(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2)); + CLRSET(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4), + ((uint32_t) af) << ((n & 7) * 4)); + CLRSET(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2)); +} +static inline void hal_gpio_input(uint16_t pin) { + hal_gpio_init(pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, + HAL_GPIO_PULL_NONE, 0); +} +static inline void hal_gpio_output(uint16_t pin) { + hal_gpio_init(pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, + HAL_GPIO_PULL_NONE, 0); +} + +// USART1 kernel clock defaults to pclk2 (APB2), USART2,3 default to pclk1 +// (APB1), see RCC_CCIPR1 +static inline void hal_uart_init(USART_TypeDef *uart, uint16_t tx, + uint16_t rx, unsigned long baud) { + uint8_t af = 7; // Alternate function + uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1 + + if (uart == USART1) freq = APB2_FREQUENCY, RCC->APB2ENR |= RCC_APB2ENR_USART1EN; + if (uart == USART2) freq = APB1_FREQUENCY, RCC->APB1LENR |= RCC_APB1LENR_USART2EN; + if (uart == USART3) freq = APB1_FREQUENCY, RCC->APB1LENR |= RCC_APB1LENR_USART3EN; + + hal_gpio_init(tx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af); + hal_gpio_init(rx, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, af); + uart->CR1 = 0; // Disable this UART + uart->BRR = freq / baud; // Set baud rate + uart->CR1 = BIT(0) | BIT(2) | BIT(3); // Set UE, RE, TE +} +static inline void hal_uart_write_byte(USART_TypeDef *uart, uint8_t byte) { + uart->TDR = byte; + while ((uart->ISR & USART_ISR_TXE_TXFNF) == 0) (void) 0; +} +static inline void hal_uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) { + while (len-- > 0) hal_uart_write_byte(uart, *(uint8_t *) buf++); +} +static inline int hal_uart_read_ready(USART_TypeDef *uart) { + return uart->ISR & BIT(5); // If RXNE bit is set, data is ready +} +static inline uint8_t hal_uart_read_byte(USART_TypeDef *uart) { + return (uint8_t) (uart->RDR & 255); +} + +// RNG clock (rng_clk) is CK48, which is disabled after reset. Use HSIDIV3, +// 48 MHz. It stays enabled after the system clock switches to HSIS +static inline void hal_rng_init(void) { + CLRSET(RCC->CCIPR2, RCC_CCIPR2_CK48SEL_Msk, RCC_CCIPR2_CK48SEL_1); + RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; // Enable RNG AHB clock + RNG->CR |= RNG_CR_RNGEN; // Enable RNG +} + +static inline uint32_t hal_rng_read(void) { + while ((RNG->SR & RNG_SR_DRDY) == 0) (void) 0; + return RNG->DR; +} + +static inline void hal_ethernet_init(void) { + // Initialise Ethernet. Enable MAC GPIO pins, see UM3616 Table 9 + uint16_t pins[][2] = {HAL_ETH_PINS}; + for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) { + hal_gpio_init(pins[i][0], HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_INSANE, + HAL_GPIO_PULL_NONE, (uint8_t) pins[i][1]); + } + NVIC_EnableIRQ(ETH1_IRQn); // Setup Ethernet IRQ handler + RCC->APB3ENR |= RCC_APB3ENR_SBSEN; // Enable SBS clock + CLRSET(SBS->PMCR, SBS_PMCR_ETH1_SEL_PHY_Msk, SBS_PMCR_ETH1_SEL_PHY_2); // RMII + RCC->AHB1ENR |= RCC_AHB1ENR_ETH1CKEN | RCC_AHB1ENR_ETH1EN | + RCC_AHB1ENR_ETH1TXEN | RCC_AHB1ENR_ETH1RXEN; +} + +static inline void hal_clock_init(void) { + CLRSET(FLASH->ACR, FLASH_ACR_LATENCY_Msk | FLASH_ACR_WRHIGHFREQ_Msk, + HAL_FLASH_LATENCY); + while ((FLASH->ACR & FLASH_ACR_LATENCY_Msk) != (HAL_FLASH_LATENCY & 15)) (void) 0; + RCC->CR1 |= RCC_CR1_HSISON; // Enable HSIS, 144 MHz + while ((RCC->CR1 & RCC_CR1_HSISRDY) == 0) (void) 0; // Wait until ready + CLRSET(RCC->CFGR1, RCC_CFGR1_SW_Msk, RCC_CFGR1_SW_0); // SYSCLK = HSIS + while ((RCC->CFGR1 & RCC_CFGR1_SWS_Msk) != RCC_CFGR1_SWS_0) (void) 0; + SystemCoreClock = SYS_FREQUENCY; // Update SystemCoreClock global var + SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms +} + +static inline void hal_system_init(void) { + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU + __DSB(); + __ISB(); +} diff --git a/tutorials/stm32/nucleo-c5a3zg/minimal/link.ld b/tutorials/stm32/nucleo-c5a3zg/minimal/link.ld new file mode 100644 index 00000000..217c6178 --- /dev/null +++ b/tutorials/stm32/nucleo-c5a3zg/minimal/link.ld @@ -0,0 +1,37 @@ +ENTRY(Reset_Handler); +MEMORY { + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1024k + sram(rwx) : ORIGIN = 0x20000000, LENGTH = 256k - 1k + health(rw) : ORIGIN = 0x2003fc00, LENGTH = 1k /* Retained health record */ +} +__StackTop = ORIGIN(sram) + LENGTH(sram); /* End of RAM. stack points here */ +_estack = __StackTop; /* Used by the health fault handler */ +__StackLimit = __StackTop - 16384; /* Stack limit, MSPLIM. TLS needs > 4 KB */ + +SECTIONS { + .vectors : { KEEP(*(.vectors)) } > flash + .text : { *(.text* .text.*) } > flash + .rodata : { *(.rodata*) } > flash + + /* Copy and zero tables for the CMSIS startup code, see __cmsis_start() */ + .copy.table : { + __copy_table_start__ = .; + LONG(LOADADDR(.data)) LONG(ADDR(.data)) LONG(SIZEOF(.data) / 4) + __copy_table_end__ = .; + } > flash + .zero.table : { + __zero_table_start__ = .; + LONG(ADDR(.bss)) LONG(SIZEOF(.bss) / 4) + __zero_table_end__ = .; + } > flash + + /* Note the .iram section, for functions copied to RAM. Required for MG_IRAM OTA support */ + .data : { _sdata = .; *(.first_data) *(.iram .iram* .iram.*) *(.data SORT(.data.*)) . = ALIGN(4); _edata = .; } > sram AT > flash + _sidata = LOADADDR(.data); + + .bss : { _sbss = .; *(.bss SORT(.bss.*) COMMON) . = ALIGN(4); _ebss = .; } > sram + _end = ALIGN(_ebss, 8); /* Heap starts after .bss */ + + /* Retained health record. Startup code must neither copy nor clear it. */ + .mg_health (NOLOAD) : { KEEP(*(.mg_health .mg_health*)) } > health +} diff --git a/tutorials/stm32/nucleo-c5a3zg/minimal/main.c b/tutorials/stm32/nucleo-c5a3zg/minimal/main.c new file mode 100644 index 00000000..1264442a --- /dev/null +++ b/tutorials/stm32/nucleo-c5a3zg/minimal/main.c @@ -0,0 +1,110 @@ +// Copyright (c) 2026 Cesanta Software Limited +// All rights reserved + +#include "hal.h" +#include "mongoose.h" + +#define UART_DEBUG USART2 // ST-LINK virtual COM port, UM3616 7.12 +#define UART_DEBUG_TX_PIN PIN('A', 2) +#define UART_DEBUG_RX_PIN PIN('A', 3) + +#define LED1 PIN('A', 5) // Green, on when high. UM3616 7.8 +#define LED2 PIN('G', 1) // Red, on when low +#define LED3 PIN('G', 2) // Blue, on when low + +static void log_fn(char ch, void *param) { + hal_uart_write_buf(param, &ch, 1); +} + +static void blink_task(void) { + static uint64_t blink_timer = 0; + if (hal_timer_expired(&blink_timer, 500, hal_get_tick())) { + hal_gpio_toggle(LED2); + } +} + +uint64_t mg_millis(void) { + return hal_get_tick(); +} + +bool mg_random(void *buf, size_t len) { + for (size_t n = 0; n < len; n += sizeof(uint32_t)) { + uint32_t r = hal_rng_read(); + memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r)); + } + return true; +} + +// Self-signed P-256 certificate and key for the HTTPS listener. Created by: +// openssl ecparam -genkey -name prime256v1 -noout -out key.pem +// openssl req -x509 -key key.pem -out cert.pem -days 3650 -subj /CN=mg +#define TLS_CERT \ + "-----BEGIN CERTIFICATE-----\n" \ + "MIIBgjCCASegAwIBAgIUIJOq77Qn7lHbH6WseMemeqorR50wCgYIKoZIzj0EAwIw\n" \ + "FjEUMBIGA1UEAwwLbnVjbGVvLWg3MjMwHhcNMjYxMDEyMTUwMjE5WhcNMzYxMDA5\n" \ + "MTUwMjE5WjAWMRQwEgYDVQQDDAtudWNsZW8taDcyMzBZMBMGByqGSM49AgEGCCqG\n" \ + "SM49AwEHA0IABB6IQJNmzrsdQL+2BnZYS7GYOaj7sz8f6cjBmz3n8D9Em19XodlU\n" \ + "uy4ybIvyhr766lL0ERoTmMUivb/lGmzx9C+jUzBRMB0GA1UdDgQWBBQqxMuc4gj7\n" \ + "MTMzreWlRMNI3QMqTzAfBgNVHSMEGDAWgBQqxMuc4gj7MTMzreWlRMNI3QMqTzAP\n" \ + "BgNVHRMBAf8EBTADAQH/MAoGCCqGSM49BAMCA0kAMEYCIQDY4xaJpuxq6b3rHK3b\n" \ + "lOIQyfkQX+orCRqQUkseplqpqwIhAKswZFNn+2zUNRRNY8+cHmdIwmdpsmxtoWYP\n" \ + "BCjX++LI\n" \ + "-----END CERTIFICATE-----\n" + +#define TLS_KEY \ + "-----BEGIN EC PRIVATE KEY-----\n" \ + "MHcCAQEEIJ/GBl0TlD52q9PMg1KWaNIdXqp8b/HyIsABmBpqC+O1oAoGCCqGSM49\n" \ + "AwEHoUQDQgAEHohAk2bOux1Av7YGdlhLsZg5qPuzPx/pyMGbPefwP0SbX1eh2VS7\n" \ + "LjJsi/KGvvrqUvQRGhOYxSK9v+UabPH0Lw==\n" \ + "-----END EC PRIVATE KEY-----\n" + +static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) { + if (ev == MG_EV_ACCEPT && c->is_tls) { // Accepted on the https:// listener + struct mg_tls_opts opts = {.cert = mg_str(TLS_CERT), + .key = mg_str(TLS_KEY)}; + mg_tls_init(c, &opts); + } else if (ev == MG_EV_HTTP_MSG) { + struct mg_http_message *hm = (struct mg_http_message *) ev_data; + if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) { + mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), hal_get_tick()); + } else if (mg_match(hm->uri, mg_str("/api/crash"), NULL)) { + __asm volatile("udf #0"); // Trigger HardFault + } else { + mg_http_reply(c, 200, "", + "Hi from Mongoose!\n" + "tick: %llu\n" + "ram used: %zu\n" + "ram free: %zu\n", + hal_get_tick(), hal_ram_used(), hal_ram_free()); + } + } +} + +int main(void) { + MG_HEALTH_INIT(); + + hal_clock_init(); + hal_uart_init(UART_DEBUG, UART_DEBUG_TX_PIN, UART_DEBUG_RX_PIN, 115200); + mg_log_set_fn(log_fn, UART_DEBUG); + hal_rng_init(); + hal_ethernet_init(); + hal_gpio_output(LED1); + hal_gpio_output(LED2); + hal_gpio_output(LED3); + + struct mg_mgr mgr; + mg_mgr_init(&mgr); + mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL); + mg_http_listen(&mgr, "https://0.0.0.0", http_ev_handler, NULL); + + MG_INFO(("Initialised. CPU clock: %lu MHz", SystemCoreClock / 1000000)); + MG_INFO(("RAM used: %zu, free: %zu", hal_ram_used(), hal_ram_free())); + MG_INFO(("Crash record: %M", mg_print_crash_record)); + + for (;;) { + mg_mgr_poll(&mgr, 0); + blink_task(); + } + + return 0; +} diff --git a/tutorials/stm32/nucleo-c5a3zg/minimal/mongoose_config.h b/tutorials/stm32/nucleo-c5a3zg/minimal/mongoose_config.h new file mode 100644 index 00000000..7ec05890 --- /dev/null +++ b/tutorials/stm32/nucleo-c5a3zg/minimal/mongoose_config.h @@ -0,0 +1,32 @@ +#pragma once +#include "hal.h" + +// See https://mongoose.ws/docs/getting-started/build-environment/ +#define MG_ARCH MG_ARCH_ARMGCC +#define MG_TLS MG_TLS_BUILTIN +#define MG_OTA MG_OTA_STM32C5 + +#define MG_ENABLE_TCPIP 1 +#define MG_ENABLE_CUSTOM_MILLIS 1 +#define MG_ENABLE_CUSTOM_RANDOM 1 +#define MG_ENABLE_DRIVER_STM32C 1 + +// Construct MAC address from the MCU unique ID +#define MGUID ((uint32_t *) UID_BASE) +#define MG_SET_MAC_ADDRESS(mac) \ + do { \ + mac[0] = 2; \ + mac[1] = MGUID[0] & 255; \ + mac[2] = (MGUID[0] >> 10) & 255; \ + mac[3] = (MGUID[0] >> 19) & 255; \ + mac[4] = MGUID[1] & 255; \ + mac[5] = MGUID[2] & 255; \ + } while (0) + +// Crash report support. Health record lives in the .mg_health region, see link.ld +#define MG_ENABLE_HEALTH 1 + +// mdash.net device management service support +#define MG_ENABLE_MDASH 0 +#define MG_MDASH_KEY "..." // Set this - mDash device token +#define MG_FIRMWARE_VERSION "c5a3.1.0.0"