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Add driver init to mg_mgr_init()
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Sergio R. Caprile committed
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9f498d2eea
commit
c8fd3d6d25
29 files changed
+455
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@@ -5,4 +5,13 @@
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#include "Driver_ETH_MAC.h" // keep this include
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#include "Driver_ETH_PHY.h" // keep this include
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#ifndef MG_MAC_ADDRESS
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#define MG_MAC_ADDRESS MG_MAC_ADDRESS_RANDOM
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#endif
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#define MG_TCPIP_DRIVER_DATA int driver_data;
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#define MG_TCPIP_DRIVER_CODE &mg_tcpip_driver_cmsis
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#define MG_TCPIP_DRIVER_NAME "cmsis"
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#endif
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+1
-1
@@ -1,4 +1,4 @@
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#include "tcpip.h"
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#include "net_builtin.h"
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT) && MG_ENABLE_DRIVER_IMXRT
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struct imxrt_enet {
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@@ -1,5 +1,7 @@
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#pragma once
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT) && MG_ENABLE_DRIVER_IMXRT
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struct mg_tcpip_driver_imxrt_data {
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// MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk),
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// must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz
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@@ -16,3 +18,26 @@ struct mg_tcpip_driver_imxrt_data {
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uint8_t phy_addr; // PHY address
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};
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#ifndef MG_MAC_ADDRESS
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#define MG_MAC_ADDRESS MG_MAC_ADDRESS_RANDOM
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#endif
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#ifndef MG_TCPIP_PHY_ADDR
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#define MG_TCPIP_PHY_ADDR 2
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#endif
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#ifndef MG_DRIVER_MDC_CR
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#define MG_DRIVER_MDC_CR 24
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#endif
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#define MG_TCPIP_DRIVER_DATA \
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static struct mg_tcpip_driver_imxrt_data driver_data = { \
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.mdc_cr = MG_DRIVER_MDC_CR, \
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.phy_addr = MG_TCPIP_PHY_ADDR, \
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};
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#define MG_TCPIP_DRIVER_CODE &mg_tcpip_driver_imxrt
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#define MG_TCPIP_DRIVER_NAME "imxrt"
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#endif
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@@ -1,8 +1,41 @@
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#pragma once
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_RA) && MG_ENABLE_DRIVER_RA
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struct mg_tcpip_driver_ra_data {
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// MDC clock "divider". MDC clock is software generated,
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uint32_t clock; // core clock frequency in Hz
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uint16_t irqno; // IRQn, R_ICU->IELSR[irqno]
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uint8_t phy_addr; // PHY address
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};
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#undef MG_ENABLE_TCPIP_DRIVER_INIT
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#define MG_ENABLE_TCPIP_DRIVER_INIT 0 // TODO(): needs SystemCoreClock
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#if 0
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#ifndef MG_MAC_ADDRESS
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#define MG_MAC_ADDRESS MG_MAC_ADDRESS_RANDOM
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#endif
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#ifndef MG_TCPIP_PHY_ADDR
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#define MG_TCPIP_PHY_ADDR 1
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#endif
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#ifndef MG_DRIVER_RA_CLOCK
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#define MG_DRIVER_RA_CLOCK
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#endif
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#ifndef MG_DRIVER_RA_IRQNO
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#define MG_DRIVER_RA_IRQNO 0
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#endif
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#define MG_TCPIP_DRIVER_DATA \
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static struct mg_tcpip_driver_ra_data driver_data = { \
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.clock = MG_DRIVER_RA_CLOCK, \
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.irqno = MG_DRIVER_RA_CLOCK, \
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.phy_addr = MG_TCPIP_PHY_ADDR, \
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};
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#define MG_TCPIP_DRIVER_CODE &mg_tcpip_driver_ra
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#define MG_TCPIP_DRIVER_NAME "ra"
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#endif
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#endif
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@@ -1,6 +1,7 @@
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#include "tcpip.h"
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#include "net_builtin.h"
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_SAME54) && MG_ENABLE_DRIVER_SAME54
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#if defined(MG_ENABLE_DRIVER_SAME54) && MG_ENABLE_DRIVER_SAME54
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#include <sam.h>
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#define ETH_PKT_SIZE 1536 // Max frame size
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@@ -1,5 +1,25 @@
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#pragma once
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_SAME54) && MG_ENABLE_DRIVER_SAME54
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struct mg_tcpip_driver_same54_data {
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int mdc_cr;
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};
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#ifndef MG_MAC_ADDRESS
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#define MG_MAC_ADDRESS MG_MAC_ADDRESS_RANDOM
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#endif
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#ifndef MG_DRIVER_MDC_CR
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#define MG_DRIVER_MDC_CR 5
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#endif
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#define MG_TCPIP_DRIVER_DATA \
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static struct mg_tcpip_driver_same54_data driver_data = { \
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.mdc_cr = MG_DRIVER_MDC_CR, \
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};
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#define MG_TCPIP_DRIVER_CODE &mg_tcpip_driver_same54
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#define MG_TCPIP_DRIVER_NAME "same54"
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#endif
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@@ -1,5 +1,8 @@
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#pragma once
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_STM32F) && \
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MG_ENABLE_DRIVER_STM32F
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struct mg_tcpip_driver_stm32f_data {
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// MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz
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// HCLK range DIVIDER mdc_cr VALUE
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@@ -16,3 +19,26 @@ struct mg_tcpip_driver_stm32f_data {
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uint8_t phy_addr; // PHY address
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};
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#ifndef MG_MAC_ADDRESS
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#define MG_MAC_ADDRESS MG_MAC_ADDRESS_RANDOM
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#endif
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#ifndef MG_TCPIP_PHY_ADDR
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#define MG_TCPIP_PHY_ADDR 0
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#endif
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#ifndef MG_DRIVER_MDC_CR
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#define MG_DRIVER_MDC_CR 4
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#endif
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#define MG_TCPIP_DRIVER_DATA \
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static struct mg_tcpip_driver_stm32f_data driver_data = { \
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.mdc_cr = MG_DRIVER_MDC_CR, \
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.phy_addr = MG_TCPIP_PHY_ADDR, \
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};
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#define MG_TCPIP_DRIVER_CODE &mg_tcpip_driver_stm32f
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#define MG_TCPIP_DRIVER_NAME "stm32f"
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#endif
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@@ -1,5 +1,8 @@
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#pragma once
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_STM32H) && \
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MG_ENABLE_DRIVER_STM32H
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struct mg_tcpip_driver_stm32h_data {
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// MDC clock divider. MDC clock is derived from HCLK, must not exceed 2.5MHz
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// HCLK range DIVIDER mdc_cr VALUE
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@@ -14,3 +17,21 @@ struct mg_tcpip_driver_stm32h_data {
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// 110, 111 Reserved
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int mdc_cr; // Valid values: -1, 0, 1, 2, 3, 4, 5
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};
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#ifndef MG_MAC_ADDRESS
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#define MG_MAC_ADDRESS MG_MAC_ADDRESS_RANDOM
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#endif
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#ifndef MG_DRIVER_MDC_CR
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#define MG_DRIVER_MDC_CR 4
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#endif
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#define MG_TCPIP_DRIVER_DATA \
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static struct mg_tcpip_driver_stm32h_data driver_data = { \
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.mdc_cr = MG_DRIVER_MDC_CR, \
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};
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#define MG_TCPIP_DRIVER_CODE &mg_tcpip_driver_stm32h
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#define MG_TCPIP_DRIVER_NAME "stm32h"
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#endif
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+1
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@@ -1,4 +1,4 @@
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#include "tcpip.h"
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#include "net_builtin.h"
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_TM4C) && MG_ENABLE_DRIVER_TM4C
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struct tm4c_emac {
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@@ -1,5 +1,7 @@
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#pragma once
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_TM4C) && MG_ENABLE_DRIVER_TM4C
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struct mg_tcpip_driver_tm4c_data {
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// MDC clock divider. MDC clock is derived from SYSCLK, must not exceed 2.5MHz
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// SYSCLK range DIVIDER mdc_cr VALUE
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@@ -12,3 +14,22 @@ struct mg_tcpip_driver_tm4c_data {
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// 0x4-0xF Reserved
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int mdc_cr; // Valid values: -1, 0, 1, 2, 3
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};
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#ifndef MG_MAC_ADDRESS
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#define MG_MAC_ADDRESS MG_MAC_ADDRESS_RANDOM
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#endif
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#ifndef MG_DRIVER_MDC_CR
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#define MG_DRIVER_MDC_CR 1
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#endif
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#define MG_TCPIP_DRIVER_DATA \
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static struct mg_tcpip_driver_tm4c_data driver_data = { \
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.mdc_cr = MG_DRIVER_MDC_CR, \
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};
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#define MG_TCPIP_DRIVER_CODE &mg_tcpip_driver_tm4c
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#define MG_TCPIP_DRIVER_NAME "tm4c"
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#endif
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+2
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@@ -1,6 +1,6 @@
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#include "tcpip.h"
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#include "net_builtin.h"
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#if MG_ENABLE_TCPIP
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_W5500) && MG_ENABLE_DRIVER_W5500
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enum { W5500_CR = 0, W5500_S0 = 1, W5500_TX0 = 2, W5500_RX0 = 3 };
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