mirror of
https://github.com/cesanta/mongoose.git
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Add nucleo-h563zi/minimal-lfs
This commit is contained in:
cpq
@@ -0,0 +1,66 @@
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# Copyright (c) 2026 Cesanta Software Limited
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# Environment setup: https://mongoose.ws/docs/getting-started/build-environment/
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CFLAGS = -W -Wall -Wextra -Wundef -Wshadow -Wdouble-promotion
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CFLAGS += -Wformat-truncation -fno-common -Wconversion -Wno-sign-conversion
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CFLAGS += -g3 -Os -ffunction-sections -fdata-sections
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CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_h5/Include -Imongoose
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CFLAGS += -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard $(CFLAGS_EXTRA)
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LDFLAGS ?= -Tlink.ld -nostdlib -nostartfiles --specs nosys.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map
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SOURCES = main.c hal.c
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SOURCES += littlefs/lfs.c littlefs/lfs_util.c
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SOURCES += cmsis_h5/Source/Templates/gcc/startup_stm32h563xx.s
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SOURCES += mongoose/mongoose.c
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# Disabled for littlefs/lfs.c
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CFLAGS += -Wno-conversion -Wno-shadow
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CFLAGS += -DMG_ENABLE_LFS=1
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all build example: firmware.bin
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mongoose/mongoose.c mongoose/mongoose.h:
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cp ../../../../mongoose.[ch] mongoose/
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firmware.elf: cmsis_core cmsis_h5 littlefs hal.h link.ld Makefile $(SOURCES) mongoose/mongoose.h
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arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(CFLAGS_EXTRA) $(LDFLAGS) -o $@
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firmware.bin: firmware.elf
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arm-none-eabi-objcopy -O binary $< $@
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@echo
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@echo "To flash, run 'make flash', or use STM32CubeProgrammer"
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flash: firmware.bin
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STM32_Programmer_CLI -c port=swd mode=UR -w firmware.elf -hardRst
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gdb: firmware.elf
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arm-none-eabi-gdb -q $^ -ex='set confirm off' -ex 'target remote :61234'
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# Directory where STM32_Programmer_CLI binary lives
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CUBEPROG_DIR ?= $(dir $(shell which STM32_Programmer_CLI))
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gdb_server:
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ST-LINK_gdbserver --port-number 61234 --log-level 1 --swd --verify --stm32cubeprogrammer-path $(CUBEPROG_DIR) --apid 1 --initialize-reset
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cmsis_core:
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git clone -q -c advice.detachedHead=false --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@
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cmsis_h5:
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git clone -q -c advice.detachedHead=false --depth 1 -b v1.6.0 https://github.com/STMicroelectronics/cmsis-device-h5 $@
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littlefs/lfs.c littlefs/lfs_util.c: littlefs
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littlefs:
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git clone -q -c advice.detachedHead=false --depth 1 -b v2.11.3 https://github.com/littlefs-project/littlefs $@
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clean:
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rm -rf firmware.* cmsis_* littlefs/ mongoose/mongoose.*
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# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/
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DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/11
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update: firmware.bin
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$<
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test update: CFLAGS_EXTRA = -DUART_DEBUG=USART1
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test: update
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curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt
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grep 'READY, IP:' /tmp/output.txt # Check for network init
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@@ -0,0 +1,125 @@
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// Copyright (c) 2026 Cesanta Software Limited
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// All rights reserved
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#include "hal.h"
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bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now) {
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uint64_t diff = now - *t; // Wrap-safe elapsed time since last expiry
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if (period == 0) return false; // Avoid division by zero
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if (diff < period) return false; // Period has not elapsed yet
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*t += (diff / period) * period; // Preserve cadence, skip missed periods
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return true;
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}
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static volatile uint64_t s_ticks; // Milliseconds since boot
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void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms
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s_ticks++;
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}
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uint64_t hal_get_tick(void) {
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return s_ticks;
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};
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uint32_t SystemCoreClock = 160000000;
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void SystemInit(void) { // Called automatically by startup code
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hal_system_init(); // Enable FPU
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hal_clock_init();
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SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms
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}
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void ExitRun0Mode(void) {
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}
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struct stat;
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__attribute__((weak)) int _fstat(int fd, struct stat *st) {
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(void) fd, (void) st;
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return -1;
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}
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extern unsigned char _end[]; // End of data section, start of heap. See link.ld
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static unsigned char *s_current_heap_end = _end;
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size_t hal_ram_used(void) {
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return (size_t) (s_current_heap_end - _end);
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}
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size_t hal_ram_free(void) {
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unsigned char endofstack;
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return (size_t) (&endofstack - s_current_heap_end);
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}
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void *_sbrk(int incr) {
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unsigned char *prev_heap;
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unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256);
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prev_heap = s_current_heap_end;
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// Check how much space we got from the heap end to the stack end
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if (s_current_heap_end + incr > heap_end) return (void *) -1;
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s_current_heap_end += incr;
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return prev_heap;
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}
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__attribute__((weak)) int _open(const char *path) {
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(void) path;
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return -1;
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}
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__attribute__((weak)) int _close(int fd) {
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(void) fd;
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return -1;
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}
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__attribute__((weak)) int _isatty(int fd) {
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(void) fd;
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return 1;
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}
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__attribute__((weak)) int _lseek(int fd, int ptr, int dir) {
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(void) fd, (void) ptr, (void) dir;
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return 0;
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}
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__attribute__((weak)) void _exit(int status) {
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(void) status;
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for (;;) asm volatile("BKPT #0");
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}
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__attribute__((weak)) void _kill(int pid, int sig) {
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(void) pid, (void) sig;
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}
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__attribute__((weak)) int _getpid(void) {
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return -1;
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}
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__attribute__((weak)) int _write(int fd, char *ptr, int len) {
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(void) fd, (void) ptr, (void) len;
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return -1;
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}
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__attribute__((weak)) int _read(int fd, char *ptr, int len) {
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(void) fd, (void) ptr, (void) len;
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return -1;
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}
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__attribute__((weak)) int _link(const char *a, const char *b) {
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(void) a, (void) b;
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return -1;
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}
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__attribute__((weak)) int _unlink(const char *a) {
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(void) a;
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return -1;
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}
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__attribute__((weak)) int _stat(const char *path, struct stat *st) {
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(void) path, (void) st;
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return -1;
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}
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__attribute__((weak)) int mkdir(const char *path, int mode) {
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(void) path, (void) mode;
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return -1;
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}
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__attribute__((weak)) void _init(void) {
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}
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@@ -0,0 +1,212 @@
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// Copyright (c) 2022-2026 Cesanta Software Limited
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// All rights reserved
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//
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// Datasheet: RM0481, devboard manual: UM3115
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// https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf
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// Alternate functions: https://www.st.com/resource/en/datasheet/stm32h563vi.pdf
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#pragma once
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#include <stm32h563xx.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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void hal_init(void);
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size_t hal_ram_free(void);
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size_t hal_ram_used(void);
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bool hal_timer_expired(volatile uint64_t *t, uint64_t prd, uint64_t now);
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uint64_t hal_get_tick(void);
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#define BIT(x) (1UL << (x))
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#define CLRSET(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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#define HAL_ETH_PINS \
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PIN('A', 1), /* ETH_REF_CLK */ \
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PIN('A', 2), /* ETH_MDIO */ \
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PIN('A', 7), /* ETH_CRS_DV */ \
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PIN('B', 15), /* ETH_TXD1 */ \
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PIN('C', 1), /* ETH_MDC */ \
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PIN('C', 4), /* ETH_RXD0 */ \
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PIN('C', 5), /* ETH_RXD1 */ \
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PIN('G', 11), /* ETH_TX_EN */ \
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PIN('G', 13) /* ETH_TXD0 */
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// System clock (11.4, Figure 48; 11.4.5, Figure 51; 11.4.8
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// SYS_FREQUENCY <= 250 MHz; (CLOCK_FREQUENCY / HPRE) ; hclk = SYS_FREQUENCY
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// APB clocks <= 250 MHz. Configure flash latency (WS) in accordance to hclk
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// freq (7.3.4, Table 37)
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enum {
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HAL_HPRE = 7, // register value, divisor value = BIT(value - 7) = / 1
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HAL_PPRE1 = 4, // register values, divisor value = BIT(value - 3) = / 2
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HAL_PPRE2 = 4,
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HAL_PPRE3 = 4,
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};
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// Make sure your chip package uses the internal LDO, otherwise set PLL1_N = 200
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enum { PLL1_HSI = 64, PLL1_M = 32, PLL1_N = 250, PLL1_P = 2 };
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#define SYS_FREQUENCY \
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((PLL1_HSI * PLL1_N / PLL1_M / PLL1_P / (BIT(HAL_HPRE - 7))) * 1000000)
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#define AHB_FREQUENCY SYS_FREQUENCY
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#define APB2_FREQUENCY (AHB_FREQUENCY / (BIT(HAL_PPRE2 - 3)))
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#define APB1_FREQUENCY (AHB_FREQUENCY / (BIT(HAL_PPRE1 - 3)))
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static inline void spin(volatile uint32_t n) {
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while (n--) (void) 0;
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}
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enum { HAL_GPIO_MODE_INPUT, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_MODE_AF, HAL_GPIO_MODE_ANALOG };
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enum { HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_OTYPE_OPEN_DRAIN };
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enum { HAL_GPIO_SPEED_LOW, HAL_GPIO_SPEED_MEDIUM, HAL_GPIO_SPEED_HIGH, HAL_GPIO_SPEED_INSANE };
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enum { HAL_GPIO_PULL_NONE, HAL_GPIO_PULL_UP, HAL_GPIO_PULL_DOWN };
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#define HAL_GPIO(N) ((GPIO_TypeDef *) ((GPIOA_BASE_NS) + 0x400 * (N)))
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static GPIO_TypeDef *hal_gpio_bank(uint16_t pin) {
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return HAL_GPIO(PINBANK(pin));
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}
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static inline void hal_gpio_toggle(uint16_t pin) {
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GPIO_TypeDef *gpio = hal_gpio_bank(pin);
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uint32_t mask = BIT(PINNO(pin));
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gpio->BSRR = mask << (gpio->ODR & mask ? 16 : 0);
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}
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static inline int hal_gpio_read(uint16_t pin) {
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return hal_gpio_bank(pin)->IDR & BIT(PINNO(pin)) ? 1 : 0;
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}
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static inline void hal_gpio_write(uint16_t pin, bool val) {
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GPIO_TypeDef *gpio = hal_gpio_bank(pin);
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gpio->BSRR = BIT(PINNO(pin)) << (val ? 0 : 16);
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}
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static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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GPIO_TypeDef *gpio = hal_gpio_bank(pin);
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uint8_t n = (uint8_t) (PINNO(pin));
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RCC->AHB2ENR |= BIT(PINBANK(pin)); // Enable GPIO clock
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CLRSET(gpio->OTYPER, 1UL << n, ((uint32_t) type) << n);
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CLRSET(gpio->OSPEEDR, 3UL << (n * 2), ((uint32_t) speed) << (n * 2));
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CLRSET(gpio->PUPDR, 3UL << (n * 2), ((uint32_t) pull) << (n * 2));
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CLRSET(gpio->AFR[n >> 3], 15UL << ((n & 7) * 4),
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((uint32_t) af) << ((n & 7) * 4));
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CLRSET(gpio->MODER, 3UL << (n * 2), ((uint32_t) mode) << (n * 2));
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}
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static inline void hal_gpio_input(uint16_t pin) {
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hal_gpio_init(pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH,
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HAL_GPIO_PULL_NONE, 0);
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}
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static inline void hal_gpio_output(uint16_t pin) {
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hal_gpio_init(pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH,
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HAL_GPIO_PULL_NONE, 0);
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}
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||||
|
||||
static inline bool hal_uart_init(USART_TypeDef *uart, uint16_t tx_pin,
|
||||
uint16_t rx_pin, unsigned long baud) {
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uint32_t freq = 0; // Bus frequency. UART1 is on APB2, rest on APB1
|
||||
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||||
if (uart == USART1) {
|
||||
freq = APB2_FREQUENCY, RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
|
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} else if (uart == USART2) {
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freq = APB1_FREQUENCY, RCC->APB1LENR |= RCC_APB1LENR_USART2EN;
|
||||
} else if (uart == USART3) {
|
||||
freq = APB1_FREQUENCY, RCC->APB1LENR |= RCC_APB1LENR_USART3EN;
|
||||
} else {
|
||||
return false;
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}
|
||||
hal_gpio_init(tx_pin, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, 7U);
|
||||
hal_gpio_init(rx_pin, HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_HIGH, 0, 7U);
|
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uart->CR1 = 0; // Disable UART
|
||||
uart->BRR = freq / baud; // Set baud rate
|
||||
uart->CR1 = USART_CR1_RE | USART_CR1_TE; // Set mode to TX & RX
|
||||
uart->CR1 |= USART_CR1_UE; // Enable UART
|
||||
return true;
|
||||
}
|
||||
static inline void hal_uart_write_byte(USART_TypeDef *uart, uint8_t byte) {
|
||||
uart->TDR = byte;
|
||||
while ((uart->ISR & BIT(7)) == 0) spin(1);
|
||||
}
|
||||
static inline void hal_uart_write_buf(USART_TypeDef *uart, char *buf, size_t len) {
|
||||
while (len-- > 0) hal_uart_write_byte(uart, *(uint8_t *) buf++);
|
||||
}
|
||||
static inline int hal_uart_read_ready(USART_TypeDef *uart) {
|
||||
return uart->ISR & BIT(5); // If RXNE bit is set, data is ready
|
||||
}
|
||||
static inline uint8_t hal_uart_read_byte(USART_TypeDef *uart) {
|
||||
return (uint8_t) (uart->RDR & 255);
|
||||
}
|
||||
|
||||
static inline void hal_rng_init(void) {
|
||||
RCC->CCIPR5 |= RCC_CCIPR5_RNGSEL_0; // RNG clock source pll1_q_ck
|
||||
RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; // Enable RNG clock
|
||||
RNG->CR |= RNG_CR_RNGEN; // Enable RNG
|
||||
}
|
||||
static inline uint32_t hal_rng_read(void) {
|
||||
while ((RNG->SR & RNG_SR_DRDY) == 0) spin(1);
|
||||
return RNG->DR;
|
||||
}
|
||||
|
||||
static inline bool hal_ldo_is_on(void) {
|
||||
return (PWR->SCCR & PWR_SCCR_LDOEN) == PWR_SCCR_LDOEN;
|
||||
}
|
||||
|
||||
// Hw pull-ups on PHY RXD0,1,DV to enable autonegotiation
|
||||
static inline void hal_ethernet_init(void) {
|
||||
// Initialise Ethernet. Enable MAC GPIO pins, see UM3115 section 10.7
|
||||
uint16_t pins[] = {HAL_ETH_PINS};
|
||||
for (size_t i = 0; i < sizeof(pins) / sizeof(pins[0]); i++) {
|
||||
hal_gpio_init(pins[i], HAL_GPIO_MODE_AF, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_INSANE,
|
||||
HAL_GPIO_PULL_NONE, 11); // 11 is the Ethernet function
|
||||
}
|
||||
NVIC_EnableIRQ(ETH_IRQn); // Setup Ethernet IRQ handler
|
||||
RCC->APB3ENR |= RCC_APB3ENR_SBSEN; // Enable SBS clock
|
||||
CLRSET(SBS->PMCR, SBS_PMCR_ETH_SEL_PHY, SBS_PMCR_ETH_SEL_PHY_2); // RMII
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_ETHEN | RCC_AHB1ENR_ETHRXEN | RCC_AHB1ENR_ETHTXEN;
|
||||
}
|
||||
|
||||
#define UUID ((uint32_t *) UID_BASE) // Unique 96-bit chip ID. TRM 59.1
|
||||
|
||||
// Helper macro for MAC generation, byte reads not allowed
|
||||
#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
|
||||
{ \
|
||||
2, UUID[0] & 255, (UUID[0] >> 10) & 255, (UUID[0] >> 19) & 255, \
|
||||
UUID[1] & 255, UUID[2] & 255 \
|
||||
}
|
||||
|
||||
static inline void hal_system_init(void) {
|
||||
SCB->CPACR |= ((3UL << 20U) | (3UL << 22U)); // Enable FPU
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
static inline void hal_clock_init(void) {
|
||||
// Set flash latency. RM0481, section 7.11.1, section 7.3.4 table 37
|
||||
CLRSET(FLASH->ACR, (FLASH_ACR_WRHIGHFREQ_Msk | FLASH_ACR_LATENCY_Msk),
|
||||
FLASH_ACR_LATENCY_5WS | FLASH_ACR_WRHIGHFREQ_1);
|
||||
|
||||
if (hal_ldo_is_on()) {
|
||||
PWR->VOSCR = PWR_VOSCR_VOS_0 | PWR_VOSCR_VOS_1; // Select VOS0
|
||||
} else {
|
||||
PWR->VOSCR = PWR_VOSCR_VOS_1; // Select VOS1
|
||||
}
|
||||
uint32_t f = PWR->VOSCR; // fake read to wait for bus clocking
|
||||
while ((PWR->VOSSR & PWR_VOSSR_ACTVOSRDY) == 0) spin(1);
|
||||
(void) f;
|
||||
RCC->CR = RCC_CR_HSION; // Clear HSI clock divisor
|
||||
while ((RCC->CR & RCC_CR_HSIRDY) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR2 = (HAL_PPRE3 << 12) | (HAL_PPRE2 << 8) | (HAL_PPRE1 << 4) | (HAL_HPRE << 0);
|
||||
RCC->PLL1DIVR =
|
||||
((PLL1_P - 1) << 9) | ((PLL1_N - 1) << 0); // Set PLL1_P PLL1_N
|
||||
// Enable P and Q divider outputs; set PLL1_M, select HSI as source,
|
||||
// !PLL1VCOSEL, PLL1RGE=0
|
||||
RCC->PLL1CFGR =
|
||||
RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1PEN | (PLL1_M << 8) | (1 << 0);
|
||||
RCC->CR |= RCC_CR_PLL1ON; // Enable PLL1
|
||||
while ((RCC->CR & RCC_CR_PLL1RDY) == 0) spin(1); // Wait until done
|
||||
RCC->CFGR1 |= (3 << 0); // Set clock source to PLL1
|
||||
while ((RCC->CFGR1 & (7 << 3)) != (3 << 3)) spin(1); // Wait until done
|
||||
|
||||
SystemCoreClock = SYS_FREQUENCY;
|
||||
}
|
||||
@@ -0,0 +1,31 @@
|
||||
ENTRY(Reset_Handler);
|
||||
MEMORY {
|
||||
flash(rx) : ORIGIN = 0x08000000, LENGTH = 2048k
|
||||
sram(rwx) : ORIGIN = 0x20000000, LENGTH = 640k
|
||||
}
|
||||
_estack = ORIGIN(sram) + LENGTH(sram); /* End of RAM. stack points here */
|
||||
_sstack = _estack - 4098;
|
||||
|
||||
SECTIONS {
|
||||
.vectors : { KEEP(*(.isr_vector)) } > flash
|
||||
.text : { *(.text* .text.*) } > flash
|
||||
.rodata : { *(.rodata*) } > flash
|
||||
|
||||
.data : {
|
||||
_sdata = .;
|
||||
*(.first_data)
|
||||
*(.ram)
|
||||
*(.data SORT(.data.*))
|
||||
_edata = .;
|
||||
} > sram AT > flash
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
.bss : {
|
||||
_sbss = .;
|
||||
*(.bss SORT(.bss.*) COMMON)
|
||||
_ebss = .;
|
||||
} > sram
|
||||
|
||||
. = ALIGN(8);
|
||||
_end = .;
|
||||
}
|
||||
@@ -0,0 +1,89 @@
|
||||
// Copyright (c) 2026 Cesanta Software Limited
|
||||
// All rights reserved
|
||||
|
||||
#include "hal.h"
|
||||
#include "mongoose.h"
|
||||
|
||||
#ifndef UART_DEBUG
|
||||
#define UART_DEBUG USART3
|
||||
#define UART_DEBUG_TX_PIN PIN('D', 8)
|
||||
#define UART_DEBUG_RX_PIN PIN('D', 9)
|
||||
#else
|
||||
#define UART_DEBUG_TX_PIN PIN('A', 9)
|
||||
#define UART_DEBUG_RX_PIN PIN('A', 10)
|
||||
#endif
|
||||
|
||||
#define LED_1 PIN('B', 0) // On-board LED pin (green)
|
||||
#define LED_2 PIN('F', 4) // On-board LED pin (yellow)
|
||||
#define LED_3 PIN('G', 4) // On-board LED pin (red)
|
||||
|
||||
#define LFS_SIZE (64 * 1024)
|
||||
|
||||
static void blink_task(void) {
|
||||
static uint64_t blink_timer = 0;
|
||||
if (hal_timer_expired(&blink_timer, 500, hal_get_tick())) {
|
||||
hal_gpio_toggle(LED_1);
|
||||
}
|
||||
}
|
||||
|
||||
uint64_t mg_millis(void) {
|
||||
return hal_get_tick();
|
||||
}
|
||||
|
||||
bool mg_random(void *buf, size_t len) {
|
||||
for (size_t n = 0; n < len; n += sizeof(uint32_t)) {
|
||||
uint32_t r = hal_rng_read();
|
||||
memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r));
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static void http_ev_handler(struct mg_connection *c, int ev, void *ev_data) {
|
||||
if (ev == MG_EV_HTTP_MSG) { // New HTTP request received
|
||||
struct mg_http_message *hm = (struct mg_http_message *) ev_data;
|
||||
if (mg_match(hm->uri, mg_str("/api/tick"), NULL)) {
|
||||
mg_http_reply(c, 200, "", "{%m:%llu}\n", MG_ESC("tick"), hal_get_tick());
|
||||
} else {
|
||||
mg_http_reply(c, 200, "", "Hi from Mongoose, tick %llu\n", hal_get_tick());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void log_fn(char ch, void *param) {
|
||||
hal_uart_write_buf(param, &ch, 1);
|
||||
}
|
||||
|
||||
int main(void) {
|
||||
hal_uart_init(UART_DEBUG, UART_DEBUG_TX_PIN, UART_DEBUG_RX_PIN, 115200);
|
||||
mg_log_set_fn(log_fn, UART_DEBUG);
|
||||
hal_rng_init();
|
||||
hal_gpio_output(LED_1);
|
||||
hal_gpio_output(LED_2);
|
||||
hal_gpio_output(LED_3);
|
||||
|
||||
hal_ethernet_init();
|
||||
|
||||
// Start a minimal web server
|
||||
struct mg_mgr mgr;
|
||||
mg_mgr_init(&mgr);
|
||||
mg_http_listen(&mgr, "http://0.0.0.0", http_ev_handler, NULL);
|
||||
|
||||
// Initialise LFS, which enables stdio fopen/fwrite/...
|
||||
if (mg_lfs_init(LFS_SIZE)) {
|
||||
char buf[20] = "";
|
||||
FILE *fp = fopen("a.txt", "r");
|
||||
if (fp != NULL) fread(buf, 1, sizeof(buf) - 1, fp), fclose(fp);
|
||||
MG_INFO(("BOOT COUNT: %s", buf));
|
||||
fp = fopen("a.txt", "w+");
|
||||
if (fp != NULL) fprintf(fp, "%d", atoi(buf) + 1), fclose(fp);
|
||||
} else {
|
||||
MG_ERROR(("LFS init failed"));
|
||||
}
|
||||
|
||||
for (;;) {
|
||||
mg_mgr_poll(&mgr, 0);
|
||||
blink_task();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,45 @@
|
||||
#pragma once
|
||||
|
||||
// See https://mongoose.ws/documentation/#build-options
|
||||
#define MG_ARCH MG_ARCH_ARMGCC
|
||||
#define MG_OTA MG_OTA_STM32H5
|
||||
#define MG_TLS MG_TLS_BUILTIN
|
||||
#define MG_IO_SIZE 2048
|
||||
|
||||
#define MG_ENABLE_POSIX_FS 1
|
||||
#define MG_ENABLE_TCPIP 1
|
||||
#define MG_ENABLE_CUSTOM_MILLIS 1
|
||||
#define MG_ENABLE_CUSTOM_RANDOM 1
|
||||
#define MG_ENABLE_PACKED_FS 1
|
||||
#define MG_ENABLE_DRIVER_STM32H 1
|
||||
|
||||
// #define MG_DRIVER_MDC_CR 4 // RMII MDC clock divider, from 0 to 4
|
||||
// #define MG_TCPIP_PHY_ADDR 0 // PHY address
|
||||
|
||||
// For static IP configuration, define MG_TCPIP_{IP,MASK,GW}
|
||||
// By default, those are set to zero, meaning that DHCP is used
|
||||
//
|
||||
// #define MG_TCPIP_IP MG_IPV4(192, 168, 0, 10)
|
||||
// #define MG_TCPIP_GW MG_IPV4(192, 168, 0, 1)
|
||||
// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0)
|
||||
|
||||
// Set custom MAC address. By default, it is randomly generated
|
||||
// Using a build-time constant:
|
||||
// #define MG_SET_MAC_ADDRESS(mac) do { mac[0] = 2; mac[1] = 3; mac[2] = 4; mac[3] = 5; mac[4] = 6; mac[5] = 7; } while (0)
|
||||
//
|
||||
// Using custom function:
|
||||
// extern void my_function(unsigned char *mac);
|
||||
// #define MG_SET_MAC_ADDRESS(mac) my_function(mac)
|
||||
|
||||
// Construct MAC address from the MCU unique ID. It is defined in the
|
||||
// ST CMSIS header as UID_BASE
|
||||
#define MGUID ((uint32_t *) 0x08fff800) // Unique 96-bit chip ID
|
||||
#define MG_SET_MAC_ADDRESS(mac) \
|
||||
do { \
|
||||
mac[0] = 2; \
|
||||
mac[1] = MGUID[0] & 255; \
|
||||
mac[2] = (MGUID[0] >> 10) & 255; \
|
||||
mac[3] = (MGUID[0] >> 19) & 255; \
|
||||
mac[4] = MGUID[1] & 255; \
|
||||
mac[5] = MGUID[2] & 255; \
|
||||
} while (0)
|
||||
Reference in New Issue
Block a user