diff --git a/resources/downloads/Makefile b/resources/downloads/Makefile
index 06a4f70d..18b8ca78 100644
--- a/resources/downloads/Makefile
+++ b/resources/downloads/Makefile
@@ -1,6 +1,6 @@
 TOP ?= ../..
 ST_TARGETS = nucleo_h723zg nucleo_f756zg nucleo_h563zi
-#ST_TARGETS = $(subst .ioc,,$(wildcard *.ioc))
+# ST_TARGETS = $(subst .ioc,,$(wildcard *.ioc))
 PROJECTS = full minimal
 TARGETS = desktop $(ST_TARGETS)
 MX ?= /Applications/STM32CubeMX.app/Contents/MacOs/STM32CubeMX
@@ -23,13 +23,17 @@ $(DESKTOP_DIRS): desktop_%:
 	sed -i ""  "s,../../..,.," $@/Makefile
 
 define ST_RULE
-$(1)_$(2): $(1).ioc
+$(1): $(1).ioc    # This creates MX-generated baseline project
 	mkdir -p $$@
 	cp $(1).ioc $$@
 	echo config load `pwd`/$$@/$(1).ioc > gen.mx
 	echo project generate >> gen.mx
 	echo exit >> gen.mx
-	test -d $$@/Core || $(MX) -q `pwd`/gen.mx
+	$(MX) -q `pwd`/gen.mx
+
+$(1)_$(2): $(1)
+	mkdir -p $$@
+	test -d $$@/$(1).ioc || cp -r $(1)/* $$@/
 	grep mongoose.h $$@/Core/Src/main.c || sed -i '' '/BEGIN Includes/r patch_include.c' $$@/Core/Src/main.c
 	grep '^int _write' $$@/Core/Src/main.c || sed -i '' '/USER CODE BEGIN 0 /r patch_write.c' $$@/Core/Src/main.c
 	grep 'mg_dash_init' $$@/Core/Src/main.c || sed -i '' '/USER CODE BEGIN WHILE/,/USER CODE END WHILE/{//!d;};' $$@/Core/Src/main.c
@@ -49,4 +53,4 @@ upload: $(ZIPS)
 	scp $(ZIPS) h1:/data/downloads/
 
 clean:
-	rm -rf $(DIRS) $(ZIPS) gen.mx
+	rm -rf $(DIRS) $(ST_TARGETS) $(ZIPS) gen.mx
diff --git a/resources/downloads/nucleo_f756zg.ioc b/resources/downloads/nucleo_f756zg.ioc
index 5db31993..a68d75dd 100644
--- a/resources/downloads/nucleo_f756zg.ioc
+++ b/resources/downloads/nucleo_f756zg.ioc
@@ -118,7 +118,7 @@ ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.17.4
 ProjectManager.FreePins=false
 ProjectManager.FreePinsContext=
 ProjectManager.HalAssertFull=false
-ProjectManager.HeapSize=0x200
+ProjectManager.HeapSize=0x10000
 ProjectManager.KeepUserCode=true
 ProjectManager.LastFirmware=true
 ProjectManager.LibraryCopy=1
@@ -130,7 +130,7 @@ ProjectManager.ProjectFileName=nucleo_f756zg.ioc
 ProjectManager.ProjectName=nucleo_f756zg
 ProjectManager.ProjectStructure=
 ProjectManager.RegisterCallBack=
-ProjectManager.StackSize=0x400
+ProjectManager.StackSize=0x2000
 ProjectManager.TargetToolchain=CMake
 ProjectManager.ToolChainLocation=
 ProjectManager.UAScriptAfterPath=
diff --git a/resources/downloads/nucleo_h563zi.ioc b/resources/downloads/nucleo_h563zi.ioc
index 7a339218..4be777e7 100644
--- a/resources/downloads/nucleo_h563zi.ioc
+++ b/resources/downloads/nucleo_h563zi.ioc
@@ -137,7 +137,7 @@ ProjectManager.FirmwarePackage=STM32Cube FW_H5 V1.6.0
 ProjectManager.FreePins=false
 ProjectManager.FreePinsContext=
 ProjectManager.HalAssertFull=false
-ProjectManager.HeapSize=0x200
+ProjectManager.HeapSize=0x10000
 ProjectManager.KeepUserCode=true
 ProjectManager.LastFirmware=true
 ProjectManager.LibraryCopy=1
@@ -149,7 +149,7 @@ ProjectManager.ProjectFileName=nucleo_h563zi.ioc
 ProjectManager.ProjectName=nucleo_h563zi
 ProjectManager.ProjectStructure=
 ProjectManager.RegisterCallBack=
-ProjectManager.StackSize=0x400
+ProjectManager.StackSize=0x2000
 ProjectManager.TargetToolchain=CMake
 ProjectManager.ToolChainLocation=
 ProjectManager.UAScriptAfterPath=
diff --git a/resources/downloads/nucleo_h723zg.ioc b/resources/downloads/nucleo_h723zg.ioc
index b30b78d4..8301a31b 100644
--- a/resources/downloads/nucleo_h723zg.ioc
+++ b/resources/downloads/nucleo_h723zg.ioc
@@ -115,7 +115,7 @@ ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.13.0
 ProjectManager.FreePins=false
 ProjectManager.FreePinsContext=
 ProjectManager.HalAssertFull=false
-ProjectManager.HeapSize=0x200
+ProjectManager.HeapSize=0x10000
 ProjectManager.KeepUserCode=true
 ProjectManager.LastFirmware=true
 ProjectManager.LibraryCopy=1
@@ -127,7 +127,7 @@ ProjectManager.ProjectFileName=h723.ioc
 ProjectManager.ProjectName=h723
 ProjectManager.ProjectStructure=
 ProjectManager.RegisterCallBack=
-ProjectManager.StackSize=0x400
+ProjectManager.StackSize=0x2000
 ProjectManager.TargetToolchain=CMake
 ProjectManager.ToolChainLocation=
 ProjectManager.UAScriptAfterPath=
diff --git a/resources/downloads/nucleo_n657x0_q.ioc b/resources/downloads/nucleo_n657x0_q.ioc
new file mode 100644
index 00000000..a9ff01ff
--- /dev/null
+++ b/resources/downloads/nucleo_n657x0_q.ioc
@@ -0,0 +1,895 @@
+#MicroXplorer Configuration settings - do not modify
+Appli.IPs=CORTEX_M55_S,GPDMA1,HPDMA1,LINKEDLIST,RCC,SAU,GPIO,NVIC1\:I
+CAD.formats=
+CAD.pinconfig=
+CAD.provider=
+Cesanta.I-CUBE-Mongoose.7.21.5_ExtMemLoader.IPParameters=MongooseJjNetworkingOoCore,MongooseJjWebOoDeviceOoDashboard
+Cesanta.I-CUBE-Mongoose.7.21.5_ExtMemLoader.MongooseJjNetworkingOoCore=true
+Cesanta.I-CUBE-Mongoose.7.21.5_ExtMemLoader.MongooseJjNetworkingOoCore_Checked=true
+Cesanta.I-CUBE-Mongoose.7.21.5_ExtMemLoader.MongooseJjWebOoDeviceOoDashboard=true
+Cesanta.I-CUBE-Mongoose.7.21.5_ExtMemLoader.MongooseJjWebOoDeviceOoDashboard_Checked=true
+Cesanta.I-CUBE-Mongoose.7.21.5_ExtMemLoader_SwParameter=MongooseJjNetworkingOoCore\:true;MongooseJjWebOoDeviceOoDashboard\:true;MongooseJjMQTTOoClient\:true;
+ETH1.IPParameters=MediaInterface
+ETH1.MediaInterface=HAL_ETH_RMII_MODE
+ExtMemLoader.IPs=EXTMEM_LOADER,EXTMEM_MANAGER,RCC\:I,GPIO,Cesanta.I-CUBE-Mongoose.7.21.5_ExtMemLoader\:I
+FSBL.IPs=CORTEX_M55_FSBL,GPDMA1\:I,HDP,HPDMA1\:I,LINKEDLIST,RCC,GPIO\:I,NVIC\:I,RIF,RNG,USART1,ETH1
+FSBL.Pins=PG0,PG10,PG8
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=false
+Mcu.CPN=STM32N657X0H3Q
+Mcu.Context0=FSBL
+Mcu.Context1=Appli
+Mcu.Context2=ExtMemLoader
+Mcu.ContextNb=3
+Mcu.ContextProject=FullSecure
+Mcu.Family=STM32N6
+Mcu.IP0=CORTEX_M55_FSBL
+Mcu.IP1=CORTEX_M55_S
+Mcu.IP2=ETH1
+Mcu.IP3=NVIC1
+Mcu.IP4=NVIC
+Mcu.IP5=RCC
+Mcu.IP6=RIF
+Mcu.IP7=RNG
+Mcu.IP8=USART1
+Mcu.IPNb=9
+Mcu.Name=STM32N657X0HxQ
+Mcu.Package=VFBGA264
+Mcu.Pin0=PE5
+Mcu.Pin1=PE6
+Mcu.Pin10=PG0
+Mcu.Pin11=PF12
+Mcu.Pin12=PG10
+Mcu.Pin13=PG8
+Mcu.Pin14=PG11
+Mcu.Pin15=VP_RIF_VS_RIF1
+Mcu.Pin16=VP_RNG_VS_RNG
+Mcu.Pin17=VP_Cesanta.I-CUBE-Mongoose_ExtMemLoader_VS_MongooseJjNetworkingOoCore_7.21.5_7.21.5
+Mcu.Pin18=VP_Cesanta.I-CUBE-Mongoose_ExtMemLoader_VS_MongooseJjWebOoDeviceOoDashboard_7.21.5_7.21.5
+Mcu.Pin2=PF4
+Mcu.Pin3=PF10
+Mcu.Pin4=PF7
+Mcu.Pin5=PF5
+Mcu.Pin6=PF15
+Mcu.Pin7=PF14
+Mcu.Pin8=PF11
+Mcu.Pin9=PF13
+Mcu.PinsNb=19
+Mcu.ThirdParty0=Cesanta.I-CUBE-Mongoose.7.21.5
+Mcu.ThirdParty0_ContextShortName=ExtMemLoader
+Mcu.ThirdParty0_Instance=Cesanta.I-CUBE-Mongoose.7.21.5_ExtMemLoader
+Mcu.ThirdPartyNb=1
+Mcu.UserConstants=
+Mcu.UserName=STM32N657X0HxQ
+MxCube.Version=6.17.0
+MxDb.Version=DB.6.0.170
+NVIC.BFHFNMINS=0
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PRIS=0
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.SecureFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.BFHFNMINS=0
+NVIC1.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.ForceEnableDMAVector=true
+NVIC1.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.PRIS=0
+NVIC1.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC1.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.SecureFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC1.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
+NVIC1.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+PCC.Checker=false
+PCC.Display=Plot\: All Steps
+PCC.Line=STM32N6x7
+PCC.MCU=STM32N657X0HxQ
+PCC.PartNumber=STM32N657X0HxQ
+PCC.Series=STM32N6
+PCC.Temperature=25
+PCC.Vdd=1.8
+PE5.GPIOParameters=PinAttribute
+PE5.Locked=true
+PE5.Mode=Asynchronous
+PE5.PinAttribute=FSBL
+PE5.Signal=USART1_TX
+PE6.GPIOParameters=PinAttribute
+PE6.Mode=Asynchronous
+PE6.PinAttribute=FSBL
+PE6.Signal=USART1_RX
+PF10.GPIOParameters=PinAttribute
+PF10.Mode=RMII
+PF10.PinAttribute=FSBL
+PF10.Signal=ETH1_RMII_CRS_DV
+PF11.GPIOParameters=PinAttribute
+PF11.Mode=RMII
+PF11.PinAttribute=FSBL
+PF11.Signal=ETH1_RMII_TX_EN
+PF12.GPIOParameters=PinAttribute
+PF12.Mode=RMII
+PF12.PinAttribute=FSBL
+PF12.Signal=ETH1_RMII_TXD0
+PF13.GPIOParameters=PinAttribute
+PF13.Mode=RMII
+PF13.PinAttribute=FSBL
+PF13.Signal=ETH1_RMII_TXD1
+PF14.GPIOParameters=PinAttribute
+PF14.Mode=RMII
+PF14.PinAttribute=FSBL
+PF14.Signal=ETH1_RMII_RXD0
+PF15.GPIOParameters=PinAttribute
+PF15.Mode=RMII
+PF15.PinAttribute=FSBL
+PF15.Signal=ETH1_RMII_RXD1
+PF4.GPIOParameters=PinAttribute
+PF4.Locked=true
+PF4.Mode=RMII
+PF4.PinAttribute=FSBL
+PF4.Signal=ETH1_MDIO
+PF5.GPIOParameters=PinAttribute
+PF5.Mode=RMII
+PF5.PinAttribute=FSBL
+PF5.Signal=ETH1_CLK
+PF7.GPIOParameters=PinAttribute
+PF7.Mode=RMII
+PF7.PinAttribute=FSBL
+PF7.Signal=ETH1_RMII_REF_CLK
+PG0.ContextOwner=FSBL
+PG0.GPIOParameters=PinAttribute
+PG0.Locked=true
+PG0.PinAttribute=FSBL
+PG0.Signal=GPIO_Output
+PG10.ContextOwner=FSBL
+PG10.GPIOParameters=PinAttribute
+PG10.Locked=true
+PG10.PinAttribute=FSBL
+PG10.Signal=GPIO_Output
+PG11.GPIOParameters=PinAttribute
+PG11.Locked=true
+PG11.Mode=RMII
+PG11.PinAttribute=FSBL
+PG11.Signal=ETH1_MDC
+PG8.ContextOwner=FSBL
+PG8.GPIOParameters=PinAttribute
+PG8.Locked=true
+PG8.PinAttribute=FSBL
+PG8.Signal=GPIO_Output
+PinOutPanel.CurrentBGAView=Top
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerLinker=GCC
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32N657X0HxQ
+ProjectManager.FirmwarePackage=STM32Cube FW_N6 V1.3.0
+ProjectManager.FreePins=false
+ProjectManager.FreePinsContext=FSBL
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=FSBL-0x8000,Appli-0x200,ExtMemLoader-0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=STM32CubeIDE
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=nucleo_n657x0_q.ioc
+ProjectManager.ProjectName=nucleo_n657x0_q
+ProjectManager.ProjectStructure=FSBL\:FSBL\:true;Appli\:Appli\:false;ExtMemLoader\:ExtMemLoader\:false;
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=FSBL-0x2000,Appli-0x800,ExtMemLoader-0x800
+ProjectManager.TargetToolchain=STM32CubeIDE
+ProjectManager.ToolChainLocation=
+ProjectManager.UAScriptAfterPath=
+ProjectManager.UAScriptBeforePath=
+ProjectManager.UnderRoot=true
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false-FSBL,2-MX_GPIO_Init-GPIO-false-HAL-true-FSBL,3-MX_ETH1_Init-ETH1-false-HAL-true-FSBL,4-MX_RNG_Init-RNG-false-HAL-true-FSBL,5-MX_USART1_UART_Init-USART1-false-HAL-true-FSBL,6-SystemIsolation_Config-RIF-false-HAL-true-FSBL,0-MX_CORTEX_M55_FSBL_Init-CORTEX_M55_FSBL-false-HAL-true-FSBL,0-MX_CORTEX_M55_S_Init-CORTEX_M55_S-false-HAL-true-Appli
+RCC.ADC12Freq_Value=100000000
+RCC.ADFFreq_Value=100000000
+RCC.AHB1234Freq_Value=100000000
+RCC.AHBFreq_Value=8000000
+RCC.APB1Freq_Value=100000000
+RCC.APB2Freq_Value=100000000
+RCC.APB4Freq_Value=100000000
+RCC.APB5Freq_Value=100000000
+RCC.AXIClockFreq_Value=400000000
+RCC.CKPERFreq_Value=64000000
+RCC.CortexFreq_Value=8000000
+RCC.CpuClockFreq_Value=64000000
+RCC.DCMIPPFreq_Value=100000000
+RCC.ETH1Freq_Value=100000000
+RCC.FDCANFreq_Value=100000000
+RCC.FMCFreq_Value=100000000
+RCC.FOUTPOSTDIV1Freq_Value=1600000000
+RCC.FOUTPOSTDIV2Freq_Value=1600000000
+RCC.FOUTPOSTDIV3Freq_Value=1600000000
+RCC.FOUTPOSTDIV4Freq_Value=1600000000
+RCC.FamilyName=M
+RCC.HPRE_Div=RCC_HCLK_DIV4
+RCC.HSE_VALUE=48000000
+RCC.HSI_VALUE=64000000
+RCC.I2C1Freq_Value=100000000
+RCC.I2C2Freq_Value=100000000
+RCC.I2C3Freq_Value=100000000
+RCC.I2C4Freq_Value=100000000
+RCC.I3C1Freq_Value=100000000
+RCC.I3C2Freq_Value=100000000
+RCC.IC10Freq_VALUE=1600000000
+RCC.IC11Freq_VALUE=400000000
+RCC.IC12Freq_VALUE=1600000000
+RCC.IC13Freq_VALUE=1600000000
+RCC.IC14Freq_VALUE=1600000000
+RCC.IC15Freq_VALUE=1600000000
+RCC.IC16Freq_VALUE=1600000000
+RCC.IC17Freq_VALUE=1600000000
+RCC.IC18Freq_VALUE=1600000000
+RCC.IC19Freq_VALUE=1600000000
+RCC.IC1Freq_VALUE=533333333.3333333
+RCC.IC20Freq_VALUE=1600000000
+RCC.IC2Freq_VALUE=400000000
+RCC.IC3Freq_VALUE=1600000000
+RCC.IC4Freq_VALUE=1600000000
+RCC.IC5Freq_VALUE=1600000000
+RCC.IC6Freq_VALUE=400000000
+RCC.IC7Freq_VALUE=1600000000
+RCC.IC8Freq_VALUE=1600000000
+RCC.IC9Freq_VALUE=1600000000
+RCC.IPParameters=ADC12Freq_Value,ADFFreq_Value,AHB1234Freq_Value,AHBFreq_Value,APB1Freq_Value,APB2Freq_Value,APB4Freq_Value,APB5Freq_Value,AXIClockFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,DCMIPPFreq_Value,ETH1Freq_Value,FDCANFreq_Value,FMCFreq_Value,FOUTPOSTDIV1Freq_Value,FOUTPOSTDIV2Freq_Value,FOUTPOSTDIV3Freq_Value,FOUTPOSTDIV4Freq_Value,FamilyName,HPRE_Div,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I3C1Freq_Value,I3C2Freq_Value,IC10Freq_VALUE,IC11Freq_VALUE,IC12Freq_VALUE,IC13Freq_VALUE,IC14Freq_VALUE,IC15Freq_VALUE,IC16Freq_VALUE,IC17Freq_VALUE,IC18Freq_VALUE,IC19Freq_VALUE,IC1Freq_VALUE,IC20Freq_VALUE,IC2Freq_VALUE,IC3Freq_VALUE,IC4Freq_VALUE,IC5Freq_VALUE,IC6Freq_VALUE,IC7Freq_VALUE,IC8Freq_VALUE,IC9Freq_VALUE,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPTIM4Freq_Value,LPTIM5Freq_Value,LPUART1Freq_Value,LSE_VALUE,LSI_VALUE,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,MDFFreq_Value,MSI_VALUE,OTGHS1Freq_Value,OTGHS2Freq_Value,OTGPHY1Freq_Value,OTGPHY2Freq_Value,PLL1FRACV,PLL2FRACV,PLL3FRACV,PLL4FRACV,PSSIFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1Freq_Value,SDMMC2Freq_Value,SPDIFRX1Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SPI5Freq_Value,SPI6Freq_Value,SYSBCLKFreq_VALUE,SYSBCLKSource,SYSCCLKFreq_VALUE,SYSDCLKFreq_VALUE,TIMGFreq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,UART9Freq_Value,USART10Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCO4OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInput4Freq_Value,XSPI1Freq_Value,XSPI2Freq_Value,XSPI3Freq_Value
+RCC.LPTIM1Freq_Value=100000000
+RCC.LPTIM2Freq_Value=100000000
+RCC.LPTIM3Freq_Value=100000000
+RCC.LPTIM4Freq_Value=100000000
+RCC.LPTIM5Freq_Value=100000000
+RCC.LPUART1Freq_Value=100000000
+RCC.LSE_VALUE=32768
+RCC.LSI_VALUE=32000
+RCC.LTDCFreq_Value=100000000
+RCC.MCO1PinFreq_Value=64000000
+RCC.MCO2PinFreq_Value=64000000
+RCC.MDFFreq_Value=100000000
+RCC.MSI_VALUE=16000000
+RCC.OTGHS1Freq_Value=24000000
+RCC.OTGHS2Freq_Value=24000000
+RCC.OTGPHY1Freq_Value=24000000
+RCC.OTGPHY2Freq_Value=24000000
+RCC.PLL1FRACV=0
+RCC.PLL2FRACV=0
+RCC.PLL3FRACV=0
+RCC.PLL4FRACV=0
+RCC.PSSIFreq_Value=100000000
+RCC.RTCFreq_Value=32000
+RCC.SAI1Freq_Value=100000000
+RCC.SAI2Freq_Value=100000000
+RCC.SDMMC1Freq_Value=100000000
+RCC.SDMMC2Freq_Value=100000000
+RCC.SPDIFRX1Freq_Value=100000000
+RCC.SPI1Freq_Value=100000000
+RCC.SPI2Freq_Value=100000000
+RCC.SPI3Freq_Value=100000000
+RCC.SPI4Freq_Value=100000000
+RCC.SPI5Freq_Value=100000000
+RCC.SPI6Freq_Value=100000000
+RCC.SYSBCLKFreq_VALUE=400000000
+RCC.SYSBCLKSource=RCC_SYSCLKSOURCE_IC2_IC6_IC11
+RCC.SYSCCLKFreq_VALUE=400000000
+RCC.SYSDCLKFreq_VALUE=400000000
+RCC.TIMGFreq_Value=400000000
+RCC.UART4Freq_Value=100000000
+RCC.UART5Freq_Value=100000000
+RCC.UART7Freq_Value=100000000
+RCC.UART8Freq_Value=100000000
+RCC.UART9Freq_Value=100000000
+RCC.USART10Freq_Value=100000000
+RCC.USART1Freq_Value=100000000
+RCC.USART2Freq_Value=100000000
+RCC.USART3Freq_Value=100000000
+RCC.USART6Freq_Value=100000000
+RCC.VCO1OutputFreq_Value=1600000000
+RCC.VCO2OutputFreq_Value=1600000000
+RCC.VCO3OutputFreq_Value=1600000000
+RCC.VCO4OutputFreq_Value=1600000000
+RCC.VCOInput1Freq_Value=64000000
+RCC.VCOInput2Freq_Value=64000000
+RCC.VCOInput3Freq_Value=64000000
+RCC.VCOInput4Freq_Value=64000000
+RCC.XSPI1Freq_Value=100000000
+RCC.XSPI2Freq_Value=100000000
+RCC.XSPI3Freq_Value=100000000
+RIF.DCMIPP_CID_RIMU=0
+RIF.DMA2D_CID_RIMU=0
+RIF.ETH1_CID_RIMU=1
+RIF.ETR_CID_RIMU=0
+RIF.GPU_CID_RIMU=0
+RIF.IPParameters=ETR_CID_RIMU,SDMMC1_CID_RIMU,SDMMC2_CID_RIMU,OTG1_CID_RIMU,OTG2_CID_RIMU,ETH1_CID_RIMU,GPU_CID_RIMU,DMA2D_CID_RIMU,DCMIPP_CID_RIMU,LTDC_L1_CID_RIMU,LTDC_L2_CID_RIMU,VENC_CID_RIMU
+RIF.LTDC_L1_CID_RIMU=0
+RIF.LTDC_L2_CID_RIMU=0
+RIF.OTG1_CID_RIMU=0
+RIF.OTG2_CID_RIMU=0
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 0\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 0\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 0\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 1\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 1\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 1\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 10\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 10\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 10\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 11\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 11\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 11\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 12\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 12\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 12\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 13\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 13\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 13\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 14\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 14\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 14\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 15\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 15\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 15\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 2\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 2\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 2\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 3\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 3\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 3\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 4\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 4\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 4\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 5\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 5\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 5\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 6\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 6\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 6\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 7\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 7\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 7\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 8\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 8\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 8\ Secure=false
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 9\ Cid=-
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 9\ Privilege=true
+RIF.RIFAWARE.GPDMA1\ Feature\ GPDMA1\ channel\ 9\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA0\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA0\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA1\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA1\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA10\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA10\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA11\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA11\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA12\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA12\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA2\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA2\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA3\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA3\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA4\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA4\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA5\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA5\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA6\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA6\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA7\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA7\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA8\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA8\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PA9\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PA9\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB0\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB0\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB1\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB1\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB10\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB10\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB11\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB11\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB12\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB12\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB13\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB13\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB14\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB14\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB15\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB15\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB2\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB2\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB3\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB3\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB6\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB6\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB7\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB7\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB8\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB8\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PB9\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PB9\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC0\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC0\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC1\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC1\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC10\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC10\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC11\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC11\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC12\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC12\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC13\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC13\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC2\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC2\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC3\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC3\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC4\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC4\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC5\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC5\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC6\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC6\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC7\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC7\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC8\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC8\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PC9\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PC9\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD0\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD0\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD1\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD1\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD10\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD10\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD11\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD11\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD12\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD12\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD13\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD13\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD14\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD14\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD15\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD15\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD2\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD2\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD3\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD3\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD4\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD4\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD5\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD5\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD6\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD6\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD7\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD7\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD8\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD8\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PD9\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PD9\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE0\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE0\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE1\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE1\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE10\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE10\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE11\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE11\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE12\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE12\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE13\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE13\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE14\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE14\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE15\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE15\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE2\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE2\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE3\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE3\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE4\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE4\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE5\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PE5\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PE5\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PE6\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PE6\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PE6\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PE7\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE7\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE8\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE8\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PE9\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PE9\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PF0\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PF0\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PF1\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PF1\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PF10\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PF10\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PF10\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PF11\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PF11\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PF11\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PF12\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PF12\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PF12\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PF13\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PF13\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PF13\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PF14\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PF14\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PF14\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PF15\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PF15\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PF15\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PF2\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PF2\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PF3\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PF3\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PF4\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PF4\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PF4\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PF5\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PF5\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PF5\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PF6\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PF6\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PF7\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PF7\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PF7\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PF8\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PF8\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PF9\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PF9\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PG0\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PG0\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PG0\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PG1\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PG1\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PG10\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PG10\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PG10\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PG11\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PG11\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PG11\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PG12\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PG12\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PG13\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PG13\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PG14\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PG14\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PG15\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PG15\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PG2\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PG2\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PG3\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PG3\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PG4\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PG4\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PG5\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PG5\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PG6\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PG6\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PG7\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PG7\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PG8\ Cid=1
+RIF.RIFAWARE.GPIO\ Feature\ PG8\ FSBL=true
+RIF.RIFAWARE.GPIO\ Feature\ PG8\ Secure=true
+RIF.RIFAWARE.GPIO\ Feature\ PG9\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PG9\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PH2\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PH2\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PH3\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PH3\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PH4\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PH4\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PH5\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PH5\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PH6\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PH6\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PH7\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PH7\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PH8\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PH8\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PH9\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PH9\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN0\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN0\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN1\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN1\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN10\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN10\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN11\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN11\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN12\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN12\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN2\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN2\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN3\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN3\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN4\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN4\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN5\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN5\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN6\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN6\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN7\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN7\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN8\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN8\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PN9\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PN9\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PO0\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PO0\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PO1\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PO1\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PO2\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PO2\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PO3\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PO3\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PO4\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PO4\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PO5\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PO5\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP0\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP0\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP1\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP1\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP10\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP10\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP11\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP11\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP12\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP12\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP13\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP13\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP14\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP14\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP15\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP15\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP2\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP2\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP3\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP3\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP4\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP4\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP5\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP5\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP6\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP6\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP7\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP7\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP8\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP8\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PP9\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PP9\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PQ0\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PQ0\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PQ1\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PQ1\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PQ2\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PQ2\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PQ3\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PQ3\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PQ4\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PQ4\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PQ5\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PQ5\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PQ6\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PQ6\ Secure=false
+RIF.RIFAWARE.GPIO\ Feature\ PQ7\ Cid=-
+RIF.RIFAWARE.GPIO\ Feature\ PQ7\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 0\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 0\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 0\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 1\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 1\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 1\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 10\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 10\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 10\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 11\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 11\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 11\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 12\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 12\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 12\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 13\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 13\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 13\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 14\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 14\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 14\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 15\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 15\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 15\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 2\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 2\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 2\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 3\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 3\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 3\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 4\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 4\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 4\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 5\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 5\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 5\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 6\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 6\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 6\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 7\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 7\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 7\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 8\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 8\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 8\ Secure=false
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 9\ Cid=-
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 9\ Privilege=true
+RIF.RIFAWARE.HPDMA1\ Feature\ HPDMA1\ channel\ 9\ Secure=false
+RIF.RIFAWARE.LTDC\ Feature\ LTDC_L1\ Cid=-
+RIF.RIFAWARE.LTDC\ Feature\ LTDC_L1\ Secure=false
+RIF.RIFAWARE.LTDC\ Feature\ LTDC_L2\ Cid=-
+RIF.RIFAWARE.LTDC\ Feature\ LTDC_L2\ Secure=false
+RIF.RIFAWARE.PWR\ Feature\ Backup\ domain\ protection\ Cid=-
+RIF.RIFAWARE.PWR\ Feature\ Backup\ domain\ protection\ Secure=false
+RIF.RIFAWARE.PWR\ Feature\ CPU\ power\ control\ protection\ Cid=-
+RIF.RIFAWARE.PWR\ Feature\ CPU\ power\ control\ protection\ Secure=false
+RIF.RIFAWARE.PWR\ Feature\ I-TCM,\ D-TCM,\ and\ I-TCM\ FLEXMEM\ low\ power\ control\ protection\ Cid=-
+RIF.RIFAWARE.PWR\ Feature\ I-TCM,\ D-TCM,\ and\ I-TCM\ FLEXMEM\ low\ power\ control\ protection\ Secure=false
+RIF.RIFAWARE.PWR\ Feature\ Peripheral\ voltage\ monitor\ protection\ Cid=-
+RIF.RIFAWARE.PWR\ Feature\ Peripheral\ voltage\ monitor\ protection\ Secure=false
+RIF.RIFAWARE.PWR\ Feature\ Programmable\ voltage\ detector\ protection\ Cid=-
+RIF.RIFAWARE.PWR\ Feature\ Programmable\ voltage\ detector\ protection\ Secure=false
+RIF.RIFAWARE.PWR\ Feature\ System\ supply\ configuration\ protection\ Cid=-
+RIF.RIFAWARE.PWR\ Feature\ System\ supply\ configuration\ protection\ Secure=false
+RIF.RIFAWARE.PWR\ Feature\ VDDCORE\ monitor\ protection\ Cid=-
+RIF.RIFAWARE.PWR\ Feature\ VDDCORE\ monitor\ protection\ Secure=false
+RIF.RIFAWARE.PWR\ Feature\ Voltage\ scaling\ selection\ protection\ Cid=-
+RIF.RIFAWARE.PWR\ Feature\ Voltage\ scaling\ selection\ protection\ Secure=false
+RIF.RIFAWARE.PWR\ Feature\ WKUP1\ pin\ protection\ Cid=-
+RIF.RIFAWARE.PWR\ Feature\ WKUP1\ pin\ protection\ Secure=false
+RIF.RIFAWARE.PWR\ Feature\ WKUP2\ pin\ protection\ Cid=-
+RIF.RIFAWARE.PWR\ Feature\ WKUP2\ pin\ protection\ Secure=false
+RIF.RIFAWARE.PWR\ Feature\ WKUP3\ pin\ protection\ Cid=-
+RIF.RIFAWARE.PWR\ Feature\ WKUP3\ pin\ protection\ Secure=false
+RIF.RIFAWARE.PWR\ Feature\ WKUP4\ pin\ protection\ Cid=-
+RIF.RIFAWARE.PWR\ Feature\ WKUP4\ pin\ protection\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ BUS\ system\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ BUS\ system\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ DFT\ system\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ DFT\ system\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC1\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC1\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC10\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC10\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC11\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC11\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC12\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC12\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC13\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC13\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC14\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC14\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC15\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC15\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC16\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC16\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC17\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC17\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC18\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC18\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC19\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC19\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC2\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC2\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC20\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC20\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC3\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC3\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC4\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC4\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC5\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC5\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC6\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC6\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC7\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC7\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC8\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC8\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC9\ divider\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ IC9\ divider\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ INT\ system\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ INT\ system\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ MOD\ system\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ MOD\ system\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PER\ system\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PER\ system\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL1\ configuration\ bits\u200B\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL1\ configuration\ bits\u200B\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL2\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL2\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL3\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL3\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL4\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ PLL4\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ RST\ system\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ RST\ system\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ SYS\ system\ configuration\ bit\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ Protection\ of\ SYS\ system\ configuration\ bit\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKN\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKN\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKNC\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ ACLKNC\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB1\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB1\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB2\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB2\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB3\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB3\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB4\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB4\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB5\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHB5\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHBM\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ AHBM\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB1\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB1\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB2\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB2\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB3\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB3\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB4\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB4\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB5\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ APB5\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ NOC\ bus\ configuration\ bits\ Cid=-
+RIF.RIFAWARE.RCC\ Feature\ protection\ of\ NOC\ bus\ configuration\ bits\ Secure=false
+RIF.RIFAWARE.RTC\ Feature\ Alarm\ A\ and\ SSR\ underflow\ protection\u200B\ Cid=-
+RIF.RIFAWARE.RTC\ Feature\ Alarm\ A\ and\ SSR\ underflow\ protection\u200B\ Secure=false
+RIF.RIFAWARE.RTC\ Feature\ Alarm\ B\ protection\ Cid=-
+RIF.RIFAWARE.RTC\ Feature\ Alarm\ B\ protection\ Secure=false
+RIF.RIFAWARE.RTC\ Feature\ Initialization\ protection\ Cid=-
+RIF.RIFAWARE.RTC\ Feature\ Initialization\ protection\ Secure=false
+RIF.RIFAWARE.RTC\ Feature\ RTC\ global\ protection\ Cid=-
+RIF.RIFAWARE.RTC\ Feature\ RTC\ global\ protection\ Secure=false
+RIF.RIFAWARE.RTC\ Feature\ Shift\ register,\ daylight\ saving,\ calibration\ and\ reference\ clock\ protection\ Cid=-
+RIF.RIFAWARE.RTC\ Feature\ Shift\ register,\ daylight\ saving,\ calibration\ and\ reference\ clock\ protection\ Secure=false
+RIF.RIFAWARE.RTC\ Feature\ Timestamp\ protection\ Cid=-
+RIF.RIFAWARE.RTC\ Feature\ Timestamp\ protection\ Secure=false
+RIF.RIFAWARE.RTC\ Feature\ Wake-up\ timer\ protection\ Cid=-
+RIF.RIFAWARE.RTC\ Feature\ Wake-up\ timer\ protection\ Secure=false
+RIF.RISUP.ETH1.Privilege=true
+RIF.SDMMC1_CID_RIMU=0
+RIF.SDMMC2_CID_RIMU=0
+RIF.VENC_CID_RIMU=0
+RIF.default_config=false
+USART1.IPParameters=VirtualMode-Asynchronous
+USART1.VirtualMode-Asynchronous=VM_ASYNC
+VP_Cesanta.I-CUBE-Mongoose_ExtMemLoader_VS_MongooseJjNetworkingOoCore_7.21.5_7.21.5.Mode=MongooseJjNetworkingOoCore
+VP_Cesanta.I-CUBE-Mongoose_ExtMemLoader_VS_MongooseJjNetworkingOoCore_7.21.5_7.21.5.Signal=Cesanta.I-CUBE-Mongoose_ExtMemLoader_VS_MongooseJjNetworkingOoCore_7.21.5_7.21.5
+VP_Cesanta.I-CUBE-Mongoose_ExtMemLoader_VS_MongooseJjWebOoDeviceOoDashboard_7.21.5_7.21.5.Mode=MongooseJjWebOoDeviceOoDashboard
+VP_Cesanta.I-CUBE-Mongoose_ExtMemLoader_VS_MongooseJjWebOoDeviceOoDashboard_7.21.5_7.21.5.Signal=Cesanta.I-CUBE-Mongoose_ExtMemLoader_VS_MongooseJjWebOoDeviceOoDashboard_7.21.5_7.21.5
+VP_RIF_VS_RIF1.Mode=RISUP
+VP_RIF_VS_RIF1.Signal=RIF_VS_RIF1
+VP_RNG_VS_RNG.Mode=RNG_Activate
+VP_RNG_VS_RNG.Signal=RNG_VS_RNG
+board=custom