From f4eac6e4fc20fcea2d63f4070b7847e698f77f54 Mon Sep 17 00:00:00 2001 From: "Sergio R. Caprile" Date: Tue, 1 Oct 2024 18:22:18 -0300 Subject: [PATCH] move to Wizard --- .github/workflows/nightly.yml | 74 +++- .github/workflows/quicktest.yml | 80 +++- .../Makefile | 62 +-- .../README.md | 1 + .../frdm-mcxn947-make-baremetal-builtin/hal.c | 187 -------- .../frdm-mcxn947-make-baremetal-builtin/hal.h | 223 ---------- .../link.ld | 30 -- .../main.c | 32 -- .../mongoose.c | 1 - .../mongoose.h | 1 - .../mongoose_config.h | 25 -- .../frdm-mcxn947-make-baremetal-builtin/net.c | 1 - .../frdm-mcxn947-make-baremetal-builtin/net.h | 1 - .../packed_fs.c | 1 - .../startup.c | 411 ------------------ .../FreeRTOSConfig.h | 44 -- .../Makefile | 71 +-- .../README.md | 1 + .../frdm-mcxn947-make-freertos-builtin/hal.c | 184 -------- .../frdm-mcxn947-make-freertos-builtin/hal.h | 223 ---------- .../link.ld | 30 -- .../frdm-mcxn947-make-freertos-builtin/main.c | 42 -- .../mongoose.c | 1 - .../mongoose.h | 1 - .../mongoose_config.h | 26 -- .../frdm-mcxn947-make-freertos-builtin/net.c | 1 - .../frdm-mcxn947-make-freertos-builtin/net.h | 1 - .../packed_fs.c | 1 - .../startup.c | 411 ------------------ .../Makefile | 84 +--- .../README.md | 1 + .../rt1020-evk-make-baremetal-builtin/dcd.h | 91 ---- .../flash_image.c | 61 --- .../rt1020-evk-make-baremetal-builtin/hal.h | 337 -------------- .../rt1020-evk-make-baremetal-builtin/link.ld | 24 - .../rt1020-evk-make-baremetal-builtin/main.c | 71 --- .../mongoose.c | 1 - .../mongoose.h | 1 - .../mongoose_config.h | 14 - .../rt1020-evk-make-baremetal-builtin/net.c | 1 - .../rt1020-evk-make-baremetal-builtin/net.h | 1 - .../packed_fs.c | 1 - .../syscalls.c | 98 ----- .../sysinit.c | 82 ---- .../Makefile | 84 +--- .../README.md | 1 + .../rt1060-evk-make-baremetal-builtin/dcd.h | 95 ---- .../flash_image.c | 61 --- .../rt1060-evk-make-baremetal-builtin/hal.h | 356 --------------- .../rt1060-evk-make-baremetal-builtin/link.ld | 24 - .../rt1060-evk-make-baremetal-builtin/main.c | 72 --- .../mongoose.c | 1 - .../mongoose.h | 1 - .../mongoose_config.h | 14 - .../rt1060-evk-make-baremetal-builtin/net.c | 1 - .../rt1060-evk-make-baremetal-builtin/net.h | 1 - .../packed_fs.c | 1 - .../syscalls.c | 98 ----- .../sysinit.c | 79 ---- 59 files changed, 192 insertions(+), 3732 deletions(-) create mode 100644 examples/nxp/frdm-mcxn947-make-baremetal-builtin/README.md delete mode 100644 examples/nxp/frdm-mcxn947-make-baremetal-builtin/hal.c delete mode 100644 examples/nxp/frdm-mcxn947-make-baremetal-builtin/hal.h delete mode 100644 examples/nxp/frdm-mcxn947-make-baremetal-builtin/link.ld delete mode 100644 examples/nxp/frdm-mcxn947-make-baremetal-builtin/main.c delete mode 120000 examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose.c delete mode 120000 examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose.h delete mode 100644 examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose_config.h delete mode 120000 examples/nxp/frdm-mcxn947-make-baremetal-builtin/net.c delete mode 120000 examples/nxp/frdm-mcxn947-make-baremetal-builtin/net.h delete mode 120000 examples/nxp/frdm-mcxn947-make-baremetal-builtin/packed_fs.c delete mode 100644 examples/nxp/frdm-mcxn947-make-baremetal-builtin/startup.c delete mode 100644 examples/nxp/frdm-mcxn947-make-freertos-builtin/FreeRTOSConfig.h create mode 100644 examples/nxp/frdm-mcxn947-make-freertos-builtin/README.md delete mode 100644 examples/nxp/frdm-mcxn947-make-freertos-builtin/hal.c delete mode 100644 examples/nxp/frdm-mcxn947-make-freertos-builtin/hal.h delete mode 100644 examples/nxp/frdm-mcxn947-make-freertos-builtin/link.ld delete mode 100644 examples/nxp/frdm-mcxn947-make-freertos-builtin/main.c delete mode 120000 examples/nxp/frdm-mcxn947-make-freertos-builtin/mongoose.c delete mode 120000 examples/nxp/frdm-mcxn947-make-freertos-builtin/mongoose.h delete mode 100644 examples/nxp/frdm-mcxn947-make-freertos-builtin/mongoose_config.h delete mode 120000 examples/nxp/frdm-mcxn947-make-freertos-builtin/net.c delete mode 120000 examples/nxp/frdm-mcxn947-make-freertos-builtin/net.h delete mode 120000 examples/nxp/frdm-mcxn947-make-freertos-builtin/packed_fs.c delete mode 100644 examples/nxp/frdm-mcxn947-make-freertos-builtin/startup.c create mode 100644 examples/nxp/rt1020-evk-make-baremetal-builtin/README.md delete mode 100644 examples/nxp/rt1020-evk-make-baremetal-builtin/dcd.h delete mode 100644 examples/nxp/rt1020-evk-make-baremetal-builtin/flash_image.c delete mode 100644 examples/nxp/rt1020-evk-make-baremetal-builtin/hal.h delete mode 100644 examples/nxp/rt1020-evk-make-baremetal-builtin/link.ld delete mode 100644 examples/nxp/rt1020-evk-make-baremetal-builtin/main.c delete mode 120000 examples/nxp/rt1020-evk-make-baremetal-builtin/mongoose.c delete mode 120000 examples/nxp/rt1020-evk-make-baremetal-builtin/mongoose.h delete mode 100644 examples/nxp/rt1020-evk-make-baremetal-builtin/mongoose_config.h delete mode 120000 examples/nxp/rt1020-evk-make-baremetal-builtin/net.c delete mode 120000 examples/nxp/rt1020-evk-make-baremetal-builtin/net.h delete mode 120000 examples/nxp/rt1020-evk-make-baremetal-builtin/packed_fs.c delete mode 100644 examples/nxp/rt1020-evk-make-baremetal-builtin/syscalls.c delete mode 100644 examples/nxp/rt1020-evk-make-baremetal-builtin/sysinit.c create mode 100644 examples/nxp/rt1060-evk-make-baremetal-builtin/README.md delete mode 100644 examples/nxp/rt1060-evk-make-baremetal-builtin/dcd.h delete mode 100644 examples/nxp/rt1060-evk-make-baremetal-builtin/flash_image.c delete mode 100644 examples/nxp/rt1060-evk-make-baremetal-builtin/hal.h delete mode 100644 examples/nxp/rt1060-evk-make-baremetal-builtin/link.ld delete mode 100644 examples/nxp/rt1060-evk-make-baremetal-builtin/main.c delete mode 120000 examples/nxp/rt1060-evk-make-baremetal-builtin/mongoose.c delete mode 120000 examples/nxp/rt1060-evk-make-baremetal-builtin/mongoose.h delete mode 100644 examples/nxp/rt1060-evk-make-baremetal-builtin/mongoose_config.h delete mode 120000 examples/nxp/rt1060-evk-make-baremetal-builtin/net.c delete mode 120000 examples/nxp/rt1060-evk-make-baremetal-builtin/net.h delete mode 120000 examples/nxp/rt1060-evk-make-baremetal-builtin/packed_fs.c delete mode 100644 examples/nxp/rt1060-evk-make-baremetal-builtin/syscalls.c delete mode 100644 examples/nxp/rt1060-evk-make-baremetal-builtin/sysinit.c diff --git a/.github/workflows/nightly.yml b/.github/workflows/nightly.yml index 1cc29c4e..a16b0cca 100644 --- a/.github/workflows/nightly.yml +++ b/.github/workflows/nightly.yml @@ -305,7 +305,59 @@ jobs: - run: make -C examples/arduino clean - generic_examples: +# wizard_examples: +# runs-on: ubuntu-latest +# strategy: +# fail-fast: false +# matrix: +# example: +# - path: esp32/esp32-idf +# name: ${{ matrix.example.path }} +# env: +# GO: 0 +# steps: +# - uses: actions/checkout@v4 +# with: { fetch-depth: 2 } +# - run: echo # nothing specific to install or do +# fi +# - run: make -C examples/${{ matrix.example.path }} build + +wizard_examples_arm: + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + example: + - path: nxp/frdm-mcxn947-make-baremetal-builtin + - path: nxp/frdm-mcxn947-make-freertos-builtin + - path: nxp/rt1020-evk-make-baremetal-builtin + - path: nxp/rt1060-evk-make-baremetal-builtin + - path: nxp/rt1170-evk-make-baremetal-builtin + - path: stm32/nucleo-f429zi-make-baremetal-builtin + - path: stm32/nucleo-f429zi-make-freertos-builtin + - path: stm32/nucleo-f746zg-make-baremetal-builtin + - path: stm32/nucleo-f746zg-make-freertos-builtin + - path: stm32/nucleo-h563zi-make-baremetal-builtin + - path: stm32/nucleo-h563zi-make-freertos-builtin + - path: stm32/nucleo-h723zg-make-baremetal-builtin + - path: stm32/nucleo-h723zg-make-freertos-builtin + - path: stm32/nucleo-h743zi-make-baremetal-builtin + - path: stm32/nucleo-h743zi-make-freertos-builtin + - path: stm32/stm32h573i-dk-make-baremetal-builtin + - path: stm32/stm32h573i-dk-make-freertos-builtin + - path: ti/ek-tm4c1294xl-make-baremetal-builtin + - path: ti/ek-tm4c1294xl-make-freertos-builtin + name: ${{ matrix.example.path }} + env: + GO: 0 + steps: + - uses: actions/checkout@v4 + with: { fetch-depth: 2 } + - run: sudo apt -y update && sudo apt -y install gcc-arm-none-eabi + - run: make -C examples/${{ matrix.example.path }} build + + +generic_examples: runs-on: ubuntu-latest strategy: fail-fast: false @@ -320,7 +372,6 @@ jobs: steps: - uses: actions/checkout@v4 with: { fetch-depth: 2 } - - run: if ./test/match_changed_files.sh '^src|^examples/${{ matrix.example.path }}'; then echo GO=1 >> $GITHUB_ENV ; fi - run: echo # nothing specific to install or do - run: make -C examples/${{ matrix.example.path }} build @@ -387,34 +438,15 @@ jobs: example: - path: infineon/infineon-xmc7200 - path: microchip/same54-xpro/device-dashboard - - path: nxp/rt1020-evk-make-baremetal-builtin - path: nxp/rt1020-evk-make-freertos-builtin - - path: nxp/frdm-mcxn947-make-baremetal-builtin - - path: nxp/frdm-mcxn947-make-freertos-builtin - - path: nxp/rt1060-evk-make-baremetal-builtin - path: nxp/rt1060-evk-make-freertos-builtin - - path: nxp/rt1170-evk-make-baremetal-builtin - path: nxp/rt1170-evk-make-freertos-builtin - path: renesas/ek-ra6m4-make-baremetal-builtin - path: rp2040/pico-rndis-dashboard - path: rp2040/pico-w - path: rp2040/pico-w5500 - - path: stm32/nucleo-f429zi-make-baremetal-builtin - - path: stm32/nucleo-f429zi-make-freertos-builtin - - path: stm32/nucleo-f746zg-make-baremetal-builtin - - path: stm32/nucleo-f746zg-make-freertos-builtin - path: stm32/nucleo-f746zg-make-freertos-tcp - path: stm32/nucleo-f746zg-make-baremetal-builtin-cmsis_driver - - path: stm32/nucleo-h563zi-make-baremetal-builtin - - path: stm32/nucleo-h563zi-make-freertos-builtin - - path: stm32/nucleo-h723zg-make-baremetal-builtin - - path: stm32/nucleo-h723zg-make-freertos-builtin - - path: stm32/nucleo-h743zi-make-baremetal-builtin - - path: stm32/nucleo-h743zi-make-freertos-builtin - - path: stm32/stm32h573i-dk-make-baremetal-builtin - - path: stm32/stm32h573i-dk-make-freertos-builtin - - path: ti/ek-tm4c1294xl-make-baremetal-builtin - - path: ti/ek-tm4c1294xl-make-freertos-builtin name: ${{ matrix.example.path }} ${{ matrix.ssl }} steps: - uses: actions/checkout@v4 diff --git a/.github/workflows/quicktest.yml b/.github/workflows/quicktest.yml index 7c38d634..75d23995 100644 --- a/.github/workflows/quicktest.yml +++ b/.github/workflows/quicktest.yml @@ -173,6 +173,67 @@ jobs: - run: make -C test clean_tutorials_mac +# wizard_examples: +# runs-on: ubuntu-latest +# strategy: +# fail-fast: false +# matrix: +# example: +# - path: esp32/esp32-idf +# name: ${{ matrix.example.path }} +# env: +# GO: 0 +# steps: +# - uses: actions/checkout@v4 +# with: { fetch-depth: 2 } +# - run: | +# if ./test/match_changed_files.sh '^src'; then +# echo GO=1 >> $GITHUB_ENV +# # nothing specific to install or do +# fi +# - if: ${{ env.GO == 1 }} +# run: make -C examples/${{ matrix.example.path }} build + + wizard_examples_arm: + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + example: + - path: nxp/frdm-mcxn947-make-baremetal-builtin + - path: nxp/frdm-mcxn947-make-freertos-builtin + - path: nxp/rt1020-evk-make-baremetal-builtin + - path: nxp/rt1060-evk-make-baremetal-builtin + - path: nxp/rt1170-evk-make-baremetal-builtin + - path: stm32/nucleo-f429zi-make-baremetal-builtin + - path: stm32/nucleo-f429zi-make-freertos-builtin + - path: stm32/nucleo-f746zg-make-baremetal-builtin + - path: stm32/nucleo-f746zg-make-freertos-builtin + - path: stm32/nucleo-h563zi-make-baremetal-builtin + - path: stm32/nucleo-h563zi-make-freertos-builtin + - path: stm32/nucleo-h723zg-make-baremetal-builtin + - path: stm32/nucleo-h723zg-make-freertos-builtin + - path: stm32/nucleo-h743zi-make-baremetal-builtin + - path: stm32/nucleo-h743zi-make-freertos-builtin + - path: stm32/stm32h573i-dk-make-baremetal-builtin + - path: stm32/stm32h573i-dk-make-freertos-builtin + - path: ti/ek-tm4c1294xl-make-baremetal-builtin + - path: ti/ek-tm4c1294xl-make-freertos-builtin + name: ${{ matrix.example.path }} + env: + GO: 0 + steps: + - uses: actions/checkout@v4 + with: { fetch-depth: 2 } + - run: | + if ./test/match_changed_files.sh '^src'; then + echo GO=1 >> $GITHUB_ENV + sudo apt -y update && sudo apt -y install gcc-arm-none-eabi + fi + - if: ${{ env.GO == 1 }} + run: make -C examples/${{ matrix.example.path }} build + + generic_examples: runs-on: ubuntu-latest strategy: @@ -243,34 +304,15 @@ jobs: example: - path: infineon/infineon-xmc7200 - path: microchip/same54-xpro/device-dashboard - - path: nxp/frdm-mcxn947-make-baremetal-builtin - - path: nxp/frdm-mcxn947-make-freertos-builtin - - path: nxp/rt1020-evk-make-baremetal-builtin - path: nxp/rt1020-evk-make-freertos-builtin - - path: nxp/rt1060-evk-make-baremetal-builtin - path: nxp/rt1060-evk-make-freertos-builtin - - path: nxp/rt1170-evk-make-baremetal-builtin - path: nxp/rt1170-evk-make-freertos-builtin - path: renesas/ek-ra6m4-make-baremetal-builtin - path: rp2040/pico-rndis-dashboard - path: rp2040/pico-w - path: rp2040/pico-w5500 - - path: stm32/nucleo-f429zi-make-baremetal-builtin - - path: stm32/nucleo-f429zi-make-freertos-builtin - - path: stm32/nucleo-f746zg-make-baremetal-builtin - - path: stm32/nucleo-f746zg-make-freertos-builtin - path: stm32/nucleo-f746zg-make-freertos-tcp - path: stm32/nucleo-f746zg-make-baremetal-builtin-cmsis_driver - - path: stm32/nucleo-h563zi-make-baremetal-builtin - - path: stm32/nucleo-h563zi-make-freertos-builtin - - path: stm32/nucleo-h723zg-make-baremetal-builtin - - path: stm32/nucleo-h723zg-make-freertos-builtin - - path: stm32/nucleo-h743zi-make-baremetal-builtin - - path: stm32/nucleo-h743zi-make-freertos-builtin - - path: stm32/stm32h573i-dk-make-baremetal-builtin - - path: stm32/stm32h573i-dk-make-freertos-builtin - - path: ti/ek-tm4c1294xl-make-baremetal-builtin - - path: ti/ek-tm4c1294xl-make-freertos-builtin name: ${{ matrix.example.path }} env: GO: 0 diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/Makefile b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/Makefile index 963231e8..aa4d9db3 100644 --- a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/Makefile +++ b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/Makefile @@ -1,45 +1,29 @@ -CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion -CFLAGS += -Wformat-truncation -fno-common # -Wconversion is not SDK-friendly -CFLAGS += -g3 -Os -ffunction-sections -fdata-sections -CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MCXN947/ -CFLAGS += -Icmsis_mcu/devices/MCXN947/drivers -CFLAGS += -DCPU_MCXN947VDF -DCPU_MCXN947VDF_cm33 -DCPU_MCXN947VDF_cm33_core0 -CFLAGS += -mcpu=cortex-m33 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 $(CFLAGS_EXTRA) -CFLAGS += -Wno-old-style-declaration -Wno-unused-parameter # due to NXP FSL code - -LDSCRIPT = link.ld -LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map - -SOURCES = main.c hal.c -SOURCES += startup.c -SOURCES += cmsis_mcu/devices/MCXN947/drivers/fsl_clock.c cmsis_mcu/devices/MCXN947/drivers/fsl_spc.c cmsis_mcu/devices/MCXN947/drivers/fsl_common_arm.c # NXP support files - -# Mongoose options are defined in mongoose_config.h -SOURCES += mongoose.c net.c packed_fs.c - -# Example specific build options. See README.md -CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\" - -ifeq ($(OS),Windows_NT) - RM = cmd /C del /Q /F /S -else - RM = rm -rf -endif +BOARD = mcxn947 +IDE = GCC+make +RTOS = baremetal +WIZARD_URL ?= http://mongoose.ws/wizard all build example: firmware.bin -firmware.bin: firmware.elf - arm-none-eabi-objcopy -O binary $< $@ +firmware.bin: wizard + make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./ -firmware.elf: cmsis_core cmsis_mcu $(SOURCES) hal.h link.ld Makefile - arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@ - arm-none-eabi-size $@ +wizard: + hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \ + && curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip + unzip wizard.zip + cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h + + +# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/ +DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/?? +update: firmware.bin + curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$< + +test update: CFLAGS_EXTRA ="-DUART_DEBUG=USART?" +test: update + curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt + grep 'READY, IP:' /tmp/output.txt # Check for network init -cmsis_core: # ARM CMSIS core headers - git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@ -cmsis_mcu: - wget -O $@.zip https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MCXN947_DFP.17.0.0.pack - mkdir $@ && cd $@ && unzip -q ../$@.zip clean: - $(RM) firmware.* *.su cmsis_core cmsis_mcu *.zip - + rm -rf firmware.* wizard* diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/README.md b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/README.md new file mode 100644 index 00000000..9448fc49 --- /dev/null +++ b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/README.md @@ -0,0 +1 @@ +See [Wizard](https://mongoose.ws/wizard/#/output?board=mcxn947&ide=GCC+make&rtos=baremetal&file=README.md) diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/hal.c b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/hal.c deleted file mode 100644 index 45560b09..00000000 --- a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/hal.c +++ /dev/null @@ -1,187 +0,0 @@ -// Copyright (c) 2024 Cesanta Software Limited -// All rights reserved - -#include "hal.h" - -static volatile uint64_t s_ticks; // Milliseconds since boot -void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms - s_ticks++; -} - -#if 0 -bool mg_random(void *buf, size_t len) { // Use on-board RNG - for (size_t n = 0; n < len; n += sizeof(uint32_t)) { - uint32_t r = rng_read(); - memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r)); - } - return true; -} -#endif - -uint64_t mg_millis(void) { // Let Mongoose use our uptime function - return s_ticks; // Return number of milliseconds since boot -} - -void hal_init(void) { - clock_init(); // Set system clock to SYS_FREQUENCY - SystemCoreClock = SYS_FREQUENCY; // Update SystemCoreClock global var - SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms - // rng_init(); // TRNG is part of ELS and there is no info on that - - uart_init(UART_DEBUG, 115200); // Initialise UART - gpio_output(LED1); // Initialise LED1 - gpio_write(LED1, 1); - gpio_output(LED2); // Initialise LED2 - gpio_write(LED2, 1); - gpio_output(LED3); // Initialise LED3 - gpio_write(LED3, 1); - ethernet_init(); // Initialise Ethernet pins -} - -#if defined(__ARMCC_VERSION) -// Keil specific - implement IO printf redirection -int fputc(int c, FILE *stream) { - if (stream == stdout || stream == stderr) uart_write_byte(UART_DEBUG, c); - return c; -} -#elif defined(__GNUC__) -// ARM GCC specific. ARM GCC is shipped with Newlib C library. -// Implement newlib syscalls: -// _sbrk() for malloc -// _write() for printf redirection -// the rest are just stubs -#include // For _fstat() - -#if !defined(__MCUXPRESSO) -uint32_t SystemCoreClock; -// evaluate your use of Secure/non-Secure and modify accordingly -void SystemInit(void) { // Called automatically by startup code - SCB->CPACR |= -#if 0 - (3UL << 0 * 2) | (3UL << 1 * 2) | // Enable PowerQuad (CPO/CP1) -#endif - (3UL << 10 * 2) | (3UL << 11 * 2); // Enable FPU - __DSB(); - __ISB(); - SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; // enable LPCAC -// Read TRM 36.1 and decide whether you really want to enable aGDET and dGDET -#if 1 - // Disable aGDET and dGDET - ITRC0->OUT_SEL[4][0] = - (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | - (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); - ITRC0->OUT_SEL[4][1] = - (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | - (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); - SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; - SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; - SPC0->GLITCH_DETECT_SC = 0x3C; - SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; - ITRC0->OUT_SEL[4][0] = - (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | - (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); - ITRC0->OUT_SEL[4][1] = - (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | - (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); - GDET0->GDET_ENABLE1 = 0; - GDET1->GDET_ENABLE1 = 0; -#endif -} -#endif - -int _fstat(int fd, struct stat *st) { - (void) fd, (void) st; - return -1; -} - -#if !defined(__MCUXPRESSO) -extern unsigned char _end[]; // End of data section, start of heap. See link.ld -static unsigned char *s_current_heap_end = _end; - -size_t hal_ram_used(void) { - return (size_t) (s_current_heap_end - _end); -} - -size_t hal_ram_free(void) { - unsigned char endofstack; - return (size_t) (&endofstack - s_current_heap_end); -} - -void *_sbrk(int incr) { - unsigned char *prev_heap; - unsigned char *heap_end = (unsigned char *) ((size_t) &heap_end - 256); - prev_heap = s_current_heap_end; - // Check how much space we got from the heap end to the stack end - if (s_current_heap_end + incr > heap_end) return (void *) -1; - s_current_heap_end += incr; - return prev_heap; -} -#endif - -int _open(const char *path) { - (void) path; - return -1; -} - -int _close(int fd) { - (void) fd; - return -1; -} - -int _isatty(int fd) { - (void) fd; - return 1; -} - -int _lseek(int fd, int ptr, int dir) { - (void) fd, (void) ptr, (void) dir; - return 0; -} - -void _exit(int status) { - (void) status; - for (;;) asm volatile("BKPT #0"); -} - -void _kill(int pid, int sig) { - (void) pid, (void) sig; -} - -int _getpid(void) { - return -1; -} - -int _write(int fd, char *ptr, int len) { - (void) fd, (void) ptr, (void) len; - if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len); - return -1; -} - -int _read(int fd, char *ptr, int len) { - (void) fd, (void) ptr, (void) len; - return -1; -} - -int _link(const char *a, const char *b) { - (void) a, (void) b; - return -1; -} - -int _unlink(const char *a) { - (void) a; - return -1; -} - -int _stat(const char *path, struct stat *st) { - (void) path, (void) st; - return -1; -} - -int mkdir(const char *path, mode_t mode) { - (void) path, (void) mode; - return -1; -} - -void _init(void) { -} -#endif // __GNUC__ diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/hal.h b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/hal.h deleted file mode 100644 index ccd8b2b3..00000000 --- a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/hal.h +++ /dev/null @@ -1,223 +0,0 @@ -// Copyright (c) 2023 Cesanta Software Limited -// All rights reserved - -#pragma once - -#include -#include -#include -#include - -#define LED1 PIN(0, 10) -#define LED2 PIN(0, 27) -#define LED3 PIN(1, 2) - -#ifndef UART_DEBUG -#define UART_DEBUG LPUART4 -#endif - -#include "MCXN947_cm33_core0.h" - -#define BIT(x) (1UL << (x)) -#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set)) -#define PIN(bank, num) ((bank << 8) | (num)) -#define PINNO(pin) (pin & 255) -#define PINBANK(pin) (pin >> 8) - -void hal_init(void); -size_t hal_ram_free(void); -size_t hal_ram_used(void); - -static inline void spin(volatile uint32_t count) { - while (count--) (void) 0; -} - -#define SYS_FREQUENCY 150000000UL - -enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT }; -enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN }; -enum { GPIO_SPEED_LOW, GPIO_SPEED_HIGH }; -enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP }; -static inline GPIO_Type *gpio_bank(uint16_t pin) { - static GPIO_Type *const g[] = GPIO_BASE_PTRS; - return g[PINBANK(pin)]; -} - -static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type, - uint8_t speed, uint8_t pull, uint8_t af) { - static PORT_Type *const p[] = PORT_BASE_PTRS; - PORT_Type *port = p[PINBANK(pin)]; - GPIO_Type *gpio = gpio_bank(pin); - uint32_t mask = (uint32_t) BIT(PINNO(pin)); - bool dopull = pull > 0; - if (dopull) --pull; - if (gpio != GPIO5) { - SYSCON->AHBCLKCTRL0 |= - (1 << (SYSCON_AHBCLKCTRL0_GPIO0_SHIFT + PINBANK(pin))) | - (1 << (SYSCON_AHBCLKCTRL0_PORT0_SHIFT + PINBANK(pin))); - }; - port->PCR[PINNO(pin)] = PORT_PCR_IBE(1) | PORT_PCR_MUX(af) | PORT_PCR_DSE(1) | - PORT_PCR_ODE(type) | - PORT_PCR_SRE(speed != GPIO_SPEED_HIGH) | - PORT_PCR_PE(dopull) | PORT_PCR_PS(pull); - gpio->ICR[PINNO(pin)] = GPIO_ICR_ISF_MASK; - if (mode == GPIO_MODE_INPUT) { - gpio->PDDR &= ~mask; - } else { - gpio->PDDR |= mask; - } -} - -static inline void gpio_input(uint16_t pin) { - gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW, - GPIO_PULL_NONE, 0); -} -static inline void gpio_output(uint16_t pin) { - gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW, - GPIO_PULL_NONE, 0); -} - -static inline bool gpio_read(uint16_t pin) { - GPIO_Type *gpio = gpio_bank(pin); - return gpio->PDR[PINNO(pin)]; -} - -static inline void gpio_write(uint16_t pin, bool value) { - GPIO_Type *gpio = gpio_bank(pin); - if (value) { - gpio->PDR[PINNO(pin)] = 1; - } else { - gpio->PDR[PINNO(pin)] = 0; - } -} - -static inline void gpio_toggle(uint16_t pin) { - GPIO_Type *gpio = gpio_bank(pin); - uint32_t mask = (uint32_t) BIT(PINNO(pin)); - gpio->PTOR = mask; -} - -// MCU-Link UART (P1_9/8; FC4_P1/0) -// Arduino J1_2/4 UART (P4_3/2; FC2_P3/2) -// 33.3.23 LP_FLEXCOMM clocking -// 66.2.4 LP_FLEXCOMM init -// 66.5 LPUART -static inline void uart_init(LPUART_Type *uart, unsigned long baud) { - static LP_FLEXCOMM_Type *const f[] = LP_FLEXCOMM_BASE_PTRS; - uint8_t af = 2, fc = 0; // Alternate function, FlexComm instance - uint16_t pr = 0, pt = 0; // pins - uint32_t freq = 12000000; // fro_12_m - if (uart == LPUART2) fc = 2, pt = PIN(4, 3), pr = PIN(4, 2); - if (uart == LPUART4) fc = 4, pt = PIN(1, 9), pr = PIN(1, 8); - - SYSCON->AHBCLKCTRL1 |= (1 << (SYSCON_AHBCLKCTRL1_FC0_SHIFT + fc)); - SYSCON->PRESETCTRL1 |= (1 << (SYSCON_PRESETCTRL1_FC0_RST_SHIFT + fc)); - SYSCON->PRESETCTRL1 &= ~(1 << (SYSCON_PRESETCTRL1_FC0_RST_SHIFT + fc)); - SYSCON->FCCLKSEL[fc] = SYSCON_FCCLKSEL_SEL(2); // clock from FRO_12M / 1 - SYSCON->FLEXCOMMCLKDIV[fc] = SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(0); - LP_FLEXCOMM_Type *flexcomm = f[fc]; - flexcomm->PSELID = LP_FLEXCOMM_PSELID_PERSEL(1); // configure as UART - gpio_init(pt, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW, - GPIO_PULL_UP, af); - gpio_init(pr, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW, - GPIO_PULL_UP, af); - - uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults - uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; - // use a weird oversample ratio of 26x to fit specs, standard 16x won't do - CLRSET(uart->BAUD, - LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK, - LPUART_BAUD_OSR(26 - 1) | LPUART_BAUD_SBR(freq / (26 * baud))); - CLRSET(uart->CTRL, - LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | - LPUART_CTRL_IDLECFG_MASK, - LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) | - LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit - uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK; -} - -static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) { - uart->DATA = byte; - while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1); -} -static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) { - while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++); -} - -static inline void rng_init(void) { -} -static inline uint32_t rng_read(void) { - return 42; -} - -// - PHY and MAC clocked via a 50MHz oscillator, P1_4 (ENET0_TXCLK) -// - 33.3.30 ENET clocking -// - SMI clocked from AHB module clock (CSR) -// - PHY RST connected to P5_8 -// - PHY RXD0,1,DV = 1 on RST enable autonegotiation, no hw pull-ups -static inline void ethernet_init(void) { - // '0' in clk_rmii, set for RMII mode - SYSCON->ENETRMIICLKSEL = SYSCON_ENETRMIICLKSEL_SEL(0); - SYSCON->ENETRMIICLKDIV = SYSCON_ENETRMIICLKDIV_DIV(0); - SYSCON->AHBCLKCTRL2 |= SYSCON_AHBCLKCTRL2_ENET_MASK; // enable bus clk - SYSCON0->PRESETCTRL2 = SYSCON_PRESETCTRL2_ENET_RST_MASK; // reset MAC - SYSCON0->PRESETCTRL2 &= ~SYSCON_PRESETCTRL2_ENET_RST_MASK; // then set RMII - SYSCON0->ENET_PHY_INTF_SEL |= SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_MASK; - gpio_init(PIN(5, 8), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW, - GPIO_PULL_NONE, 0); // set P5_8 as GPIO (PHY \RST) - gpio_write(PIN(5, 8), 0); // reset PHY - gpio_init(PIN(1, 4), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_NONE, 9); // set P1_4 as ENET0_TXCLK - gpio_init(PIN(1, 5), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_NONE, 9); // set P1_5 as ENET0_TXEN - gpio_init(PIN(1, 6), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_NONE, 9); // set P1_6 as ENET0_TXD0 - gpio_init(PIN(1, 7), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_NONE, 9); // set P1_7 as ENET0_TXD1 - gpio_init(PIN(1, 13), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_UP, 9); // set P1_13 as ENET0_RXDV - gpio_init(PIN(1, 14), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_UP, 9); // set P1_14 as ENET0_RXD0 - gpio_init(PIN(1, 15), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_UP, 9); // set P1_15 as ENET0_RXD1 - gpio_init(PIN(1, 20), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_NONE, 9); // set P1_20 as ENET0_MDC - gpio_init(PIN(1, 21), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_NONE, 9); // set P1_21 as ENET0_MDIO - spin(10000); // keep PHY RST low for a while - gpio_write(PIN(5, 8), 1); // deassert RST - NVIC_EnableIRQ(ETHERNET_IRQn); // Setup Ethernet IRQ handler -} - -#include "fsl_clock.h" -#include "fsl_spc.h" - -// 33.2 Figure 127 SCG main clock -static inline void clock_init(void) { - SYSCON->AHBCLKCTRL2 |= SYSCON_AHBCLKCTRL2_SCG_MASK; // enable SCG clk - CLRSET(SCG0->RCCR, SCG_CSR_SCS_MASK, SCG_CSR_SCS(2)); // clock main_clock - spc_active_mode_dcdc_option_t dcdc = { - .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, - .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength}; - SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdc); // Set DCDC to 1.2 V - spc_active_mode_core_ldo_option_t ldo = { - .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage, - .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength}; - SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo); // Set LDO_CORE to 1.2 V - CLRSET(FMU0->FCTRL, FMU_FCTRL_RWSC_MASK, FMU_FCTRL_RWSC(3)); // Set Flash WS - spc_sram_voltage_config_t sram = {.operateVoltage = kSPC_sramOperateAt1P2V, - .requestVoltageUpdate = true}; - SPC_SetSRAMOperateVoltage(SPC0, &sram); // Set SRAM timing for 1.2V - CLOCK_SetupFROHFClocking(48000000U); // Enable FRO HF - const pll_setup_t pll0 = {.pllctrl = SCG_APLLCTRL_SOURCE(1U) | - SCG_APLLCTRL_SELI(27U) | - SCG_APLLCTRL_SELP(13U), - .pllndiv = SCG_APLLNDIV_NDIV(8U), - .pllpdiv = SCG_APLLPDIV_PDIV(1U), - .pllmdiv = SCG_APLLMDIV_MDIV(50U), - .pllRate = 150000000U}; - CLOCK_SetPLL0Freq(&pll0); // Setup PLL0 (APLL), - CLOCK_SetPll0MonitorMode(0); // disable monitor mode - CLRSET(SCG0->RCCR, SCG_CSR_SCS_MASK, SCG_CSR_SCS(5)); // clock main_clock - SYSCON->AHBCLKDIV = SYSCON_AHBCLKDIV_DIV(0); // /1 -} diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/link.ld b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/link.ld deleted file mode 100644 index 042b9e6d..00000000 --- a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/link.ld +++ /dev/null @@ -1,30 +0,0 @@ -OUTPUT_FORMAT("elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(Reset_Handler) - -MEMORY -{ - flash(RX) : ORIGIN = 0x0, LENGTH = 0x100000 - flash2(RX) : ORIGIN = 0x100000, LENGTH = 0x100000 - sram(!RX) : ORIGIN = 0x20000000, LENGTH = 0x60000 -} - -_estack = ORIGIN(sram) + LENGTH(sram); - -SECTIONS -{ - .vectors : { FILL(256) KEEP(*(.isr_vector)) } > flash - .text : { *(.text*) } > flash - .data : { - _sdata = .; - *(.first_data) - *(.data SORT(.data.*)) - _edata = .; - } > sram AT > flash - _sidata = LOADADDR(.data); - - .bss : { _sbss = .; *(.bss SORT(.bss.*) COMMON) _ebss = .; } > sram - - . = ALIGN(8); - _end = .; - } diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/main.c b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/main.c deleted file mode 100644 index 0c3d910c..00000000 --- a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/main.c +++ /dev/null @@ -1,32 +0,0 @@ -// Copyright (c) 2024 Cesanta Software Limited -// All rights reserved - -#include "hal.h" -#include "mongoose.h" -#include "net.h" - -#define BLINK_PERIOD_MS 1000 - -static void timer_fn(void *arg) { - gpio_toggle(LED1); // Blink LED - (void) arg; // Unused -} - -int main(void) { - struct mg_mgr mgr; // Mongoose event manager - - hal_init(); // Cross-platform hardware init - - mg_mgr_init(&mgr); // Initialise it - mg_log_set(MG_LL_DEBUG); // Set log level to debug - mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mgr); - - MG_INFO(("Initialising application...")); - web_init(&mgr); - - for (;;) { - mg_mgr_poll(&mgr, 0); - } - - return 0; -} diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose.c b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose.c deleted file mode 120000 index 5e522bbc..00000000 --- a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose.c +++ /dev/null @@ -1 +0,0 @@ -../../../mongoose.c \ No newline at end of file diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose.h b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose.h deleted file mode 120000 index ee4ac823..00000000 --- a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose.h +++ /dev/null @@ -1 +0,0 @@ -../../../mongoose.h \ No newline at end of file diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose_config.h b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose_config.h deleted file mode 100644 index c5c22aac..00000000 --- a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/mongoose_config.h +++ /dev/null @@ -1,25 +0,0 @@ -#pragma once - -// See https://mongoose.ws/documentation/#build-options -#define MG_ARCH MG_ARCH_NEWLIB - -#define MG_ENABLE_TCPIP 1 -#define MG_ENABLE_DRIVER_MCXN 1 -#define MG_ENABLE_CUSTOM_MILLIS 1 -//#define MG_ENABLE_CUSTOM_RANDOM 1 -#define MG_ENABLE_PACKED_FS 1 - -// For static IP configuration, define MG_TCPIP_{IP,MASK,GW} -// By default, those are set to zero, meaning that DHCP is used -// -// #define MG_TCPIP_IP MG_IPV4(192, 168, 1, 10) -// #define MG_TCPIP_GW MG_IPV4(192, 168, 1, 1) -// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0) - -// Set custom MAC address. By default, it is randomly generated -// Using a build-time constant: -// #define MG_SET_MAC_ADDRESS(mac) do { uint8_t buf_[6] = {2,3,4,5,6,7}; memmove(mac, buf_, sizeof(buf_)); } while (0) -// -// Using custom function: -// extern void my_function(unsigned char *mac); -// #define MG_SET_MAC_ADDRESS(mac) my_function(mac) diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/net.c b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/net.c deleted file mode 120000 index fe0e6f06..00000000 --- a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/net.c +++ /dev/null @@ -1 +0,0 @@ -../../device-dashboard/net.c \ No newline at end of file diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/net.h b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/net.h deleted file mode 120000 index 9de896ef..00000000 --- a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/net.h +++ /dev/null @@ -1 +0,0 @@ -../../device-dashboard/net.h \ No newline at end of file diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/packed_fs.c b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/packed_fs.c deleted file mode 120000 index e06bf092..00000000 --- a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/packed_fs.c +++ /dev/null @@ -1 +0,0 @@ -../../device-dashboard/packed_fs.c \ No newline at end of file diff --git a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/startup.c b/examples/nxp/frdm-mcxn947-make-baremetal-builtin/startup.c deleted file mode 100644 index 0ab97c1b..00000000 --- a/examples/nxp/frdm-mcxn947-make-baremetal-builtin/startup.c +++ /dev/null @@ -1,411 +0,0 @@ -#include "MCXN947_cm33_core0.h" - -void Reset_Handler(void); // Defined below -void Dummy_Handler(void); // Defined below -void SysTick_Handler(void); // Defined in main.c -void SystemInit(void); // Defined in main.c, called by reset handler -void _estack(void); // Defined in link.ld - -#define WEAK_ALIAS __attribute__((weak, alias("Default_Handler"))) - -WEAK_ALIAS void NMI_Handler(void); -WEAK_ALIAS void HardFault_Handler(void); -WEAK_ALIAS void MemManage_Handler(void); -WEAK_ALIAS void BusFault_Handler(void); -WEAK_ALIAS void UsageFault_Handler(void); -WEAK_ALIAS void SecureFault_Handler(void); -WEAK_ALIAS void DebugMon_Handler(void); -WEAK_ALIAS void SVC_Handler(void); -WEAK_ALIAS void PendSV_Handler(void); -WEAK_ALIAS void SysTick_Handler(void); - -WEAK_ALIAS void OR_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH0_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH1_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH2_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH3_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH4_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH5_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH6_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH7_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH8_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH9_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH10_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH11_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH12_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH13_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH14_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH15_IRQHandler(void); -WEAK_ALIAS void GPIO00_IRQHandler(void); -WEAK_ALIAS void GPIO01_IRQHandler(void); -WEAK_ALIAS void GPIO10_IRQHandler(void); -WEAK_ALIAS void GPIO11_IRQHandler(void); -WEAK_ALIAS void GPIO20_IRQHandler(void); -WEAK_ALIAS void GPIO21_IRQHandler(void); -WEAK_ALIAS void GPIO30_IRQHandler(void); -WEAK_ALIAS void GPIO31_IRQHandler(void); -WEAK_ALIAS void GPIO40_IRQHandler(void); -WEAK_ALIAS void GPIO41_IRQHandler(void); -WEAK_ALIAS void GPIO50_IRQHandler(void); -WEAK_ALIAS void GPIO51_IRQHandler(void); -WEAK_ALIAS void UTICK0_IRQHandler(void); -WEAK_ALIAS void MRT0_IRQHandler(void); -WEAK_ALIAS void CTIMER0_IRQHandler(void); -WEAK_ALIAS void CTIMER1_IRQHandler(void); -WEAK_ALIAS void SCT0_IRQHandler(void); -WEAK_ALIAS void CTIMER2_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM0_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM1_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM2_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM3_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM4_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM5_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM6_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM7_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM8_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM9_IRQHandler(void); -WEAK_ALIAS void ADC0_IRQHandler(void); -WEAK_ALIAS void ADC1_IRQHandler(void); -WEAK_ALIAS void PINT0_IRQHandler(void); -WEAK_ALIAS void PDM_EVENT_IRQHandler(void); -WEAK_ALIAS void Reserved65_IRQHandler(void); -WEAK_ALIAS void USB0_FS_IRQHandler(void); -WEAK_ALIAS void USB0_DCD_IRQHandler(void); -WEAK_ALIAS void RTC_IRQHandler(void); -WEAK_ALIAS void SMARTDMA_IRQHandler(void); -WEAK_ALIAS void MAILBOX_IRQHandler(void); -WEAK_ALIAS void CTIMER3_IRQHandler(void); -WEAK_ALIAS void CTIMER4_IRQHandler(void); -WEAK_ALIAS void OS_EVENT_IRQHandler(void); -WEAK_ALIAS void FLEXSPI0_IRQHandler(void); -WEAK_ALIAS void SAI0_IRQHandler(void); -WEAK_ALIAS void SAI1_IRQHandler(void); -WEAK_ALIAS void USDHC0_IRQHandler(void); -WEAK_ALIAS void CAN0_IRQHandler(void); -WEAK_ALIAS void CAN1_IRQHandler(void); -WEAK_ALIAS void Reserved80_IRQHandler(void); -WEAK_ALIAS void Reserved81_IRQHandler(void); -WEAK_ALIAS void USB1_HS_PHY_IRQHandler(void); -WEAK_ALIAS void USB1_HS_IRQHandler(void); -WEAK_ALIAS void SEC_HYPERVISOR_CALL_IRQHandler(void); -WEAK_ALIAS void Reserved85_IRQHandler(void); -WEAK_ALIAS void PLU_IRQHandler(void); -WEAK_ALIAS void Freqme_IRQHandler(void); -WEAK_ALIAS void SEC_VIO_IRQHandler(void); -WEAK_ALIAS void ELS_IRQHandler(void); -WEAK_ALIAS void PKC_IRQHandler(void); -WEAK_ALIAS void PUF_IRQHandler(void); -WEAK_ALIAS void PQ_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH0_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH1_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH2_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH3_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH4_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH5_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH6_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH7_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH8_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH9_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH10_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH11_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH12_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH13_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH14_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH15_IRQHandler(void); -WEAK_ALIAS void CDOG0_IRQHandler(void); -WEAK_ALIAS void CDOG1_IRQHandler(void); -WEAK_ALIAS void I3C0_IRQHandler(void); -WEAK_ALIAS void I3C1_IRQHandler(void); -WEAK_ALIAS void NPU_IRQHandler(void); -WEAK_ALIAS void GDET_IRQHandler(void); -WEAK_ALIAS void VBAT0_IRQHandler(void); -WEAK_ALIAS void EWM0_IRQHandler(void); -WEAK_ALIAS void TSI_END_OF_SCAN_IRQHandler(void); -WEAK_ALIAS void TSI_OUT_OF_SCAN_IRQHandler(void); -WEAK_ALIAS void EMVSIM0_IRQHandler(void); -WEAK_ALIAS void EMVSIM1_IRQHandler(void); -WEAK_ALIAS void FLEXIO_IRQHandler(void); -WEAK_ALIAS void DAC0_IRQHandler(void); -WEAK_ALIAS void DAC1_IRQHandler(void); -WEAK_ALIAS void DAC2_IRQHandler(void); -WEAK_ALIAS void HSCMP0_IRQHandler(void); -WEAK_ALIAS void HSCMP1_IRQHandler(void); -WEAK_ALIAS void HSCMP2_IRQHandler(void); -WEAK_ALIAS void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); -WEAK_ALIAS void FLEXPWM0_FAULT_IRQHandler(void); -WEAK_ALIAS void FLEXPWM0_SUBMODULE0_IRQHandler(void); -WEAK_ALIAS void FLEXPWM0_SUBMODULE1_IRQHandler(void); -WEAK_ALIAS void FLEXPWM0_SUBMODULE2_IRQHandler(void); -WEAK_ALIAS void FLEXPWM0_SUBMODULE3_IRQHandler(void); -WEAK_ALIAS void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); -WEAK_ALIAS void FLEXPWM1_FAULT_IRQHandler(void); -WEAK_ALIAS void FLEXPWM1_SUBMODULE0_IRQHandler(void); -WEAK_ALIAS void FLEXPWM1_SUBMODULE1_IRQHandler(void); -WEAK_ALIAS void FLEXPWM1_SUBMODULE2_IRQHandler(void); -WEAK_ALIAS void FLEXPWM1_SUBMODULE3_IRQHandler(void); -WEAK_ALIAS void ENC0_COMPARE_IRQHandler(void); -WEAK_ALIAS void ENC0_HOME_IRQHandler(void); -WEAK_ALIAS void ENC0_WDG_SAB_IRQHandler(void); -WEAK_ALIAS void ENC0_IDX_IRQHandler(void); -WEAK_ALIAS void ENC1_COMPARE_IRQHandler(void); -WEAK_ALIAS void ENC1_HOME_IRQHandler(void); -WEAK_ALIAS void ENC1_WDG_SAB_IRQHandler(void); -WEAK_ALIAS void ENC1_IDX_IRQHandler(void); -WEAK_ALIAS void ITRC0_IRQHandler(void); -WEAK_ALIAS void BSP32_IRQHandler(void); -WEAK_ALIAS void ELS_ERR_IRQHandler(void); -WEAK_ALIAS void PKC_ERR_IRQHandler(void); -WEAK_ALIAS void ERM_SINGLE_BIT_ERROR_IRQHandler(void); -WEAK_ALIAS void ERM_MULTI_BIT_ERROR_IRQHandler(void); -WEAK_ALIAS void FMU0_IRQHandler(void); -WEAK_ALIAS void ETHERNET_IRQHandler(void); -WEAK_ALIAS void ETHERNET_PMT_IRQHandler(void); -WEAK_ALIAS void ETHERNET_MACLP_IRQHandler(void); -WEAK_ALIAS void SINC_FILTER_IRQHandler(void); -WEAK_ALIAS void LPTMR0_IRQHandler(void); -WEAK_ALIAS void LPTMR1_IRQHandler(void); -WEAK_ALIAS void SCG_IRQHandler(void); -WEAK_ALIAS void SPC_IRQHandler(void); -WEAK_ALIAS void WUU_IRQHandler(void); -WEAK_ALIAS void PORT_EFT_IRQHandler(void); -WEAK_ALIAS void ETB0_IRQHandler(void); -WEAK_ALIAS void SM3_IRQHandler(void); -WEAK_ALIAS void TRNG0_IRQHandler(void); -WEAK_ALIAS void WWDT0_IRQHandler(void); -WEAK_ALIAS void WWDT1_IRQHandler(void); -WEAK_ALIAS void CMC0_IRQHandler(void); -WEAK_ALIAS void CTI0_IRQHandler(void); - -__attribute__((section(".vectors"))) void (*const tab[16 + 156])(void) = { - _estack, Reset_Handler, - NMI_Handler, // NMI Handler - HardFault_Handler, // Hard Fault Handler - MemManage_Handler, // MPU Fault Handler - BusFault_Handler, // Bus Fault Handler - UsageFault_Handler, // Usage Fault Handler - SecureFault_Handler, // Secure Fault Handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - SVC_Handler, // SVCall Handler - DebugMon_Handler, // Debug Monitor Handler - 0, // Reserved - PendSV_Handler, // PendSV Handler - SysTick_Handler, // SysTick Handler - // Chip Level - MCXN947_cm33_core0 - OR_IRQHandler, // 16 : OR IRQ - EDMA_0_CH0_IRQHandler, // 17 : eDMA_0_CH0 error or transfer complete - EDMA_0_CH1_IRQHandler, // 18 : eDMA_0_CH1 error or transfer complete - EDMA_0_CH2_IRQHandler, // 19 : eDMA_0_CH2 error or transfer complete - EDMA_0_CH3_IRQHandler, // 20 : eDMA_0_CH3 error or transfer complete - EDMA_0_CH4_IRQHandler, // 21 : eDMA_0_CH4 error or transfer complete - EDMA_0_CH5_IRQHandler, // 22 : eDMA_0_CH5 error or transfer complete - EDMA_0_CH6_IRQHandler, // 23 : eDMA_0_CH6 error or transfer complete - EDMA_0_CH7_IRQHandler, // 24 : eDMA_0_CH7 error or transfer complete - EDMA_0_CH8_IRQHandler, // 25 : eDMA_0_CH8 error or transfer complete - EDMA_0_CH9_IRQHandler, // 26 : eDMA_0_CH9 error or transfer complete - EDMA_0_CH10_IRQHandler, // 27 : eDMA_0_CH10 error or transfer complete - EDMA_0_CH11_IRQHandler, // 28 : eDMA_0_CH11 error or transfer complete - EDMA_0_CH12_IRQHandler, // 29 : eDMA_0_CH12 error or transfer complete - EDMA_0_CH13_IRQHandler, // 30 : eDMA_0_CH13 error or transfer complete - EDMA_0_CH14_IRQHandler, // 31 : eDMA_0_CH14 error or transfer complete - EDMA_0_CH15_IRQHandler, // 32 : eDMA_0_CH15 error or transfer complete - GPIO00_IRQHandler, // 33 : GPIO0 interrupt 0 - GPIO01_IRQHandler, // 34 : GPIO0 interrupt 1 - GPIO10_IRQHandler, // 35 : GPIO1 interrupt 0 - GPIO11_IRQHandler, // 36 : GPIO1 interrupt 1 - GPIO20_IRQHandler, // 37 : GPIO2 interrupt 0 - GPIO21_IRQHandler, // 38 : GPIO2 interrupt 1 - GPIO30_IRQHandler, // 39 : GPIO3 interrupt 0 - GPIO31_IRQHandler, // 40 : GPIO3 interrupt 1 - GPIO40_IRQHandler, // 41 : GPIO4 interrupt 0 - GPIO41_IRQHandler, // 42 : GPIO4 interrupt 1 - GPIO50_IRQHandler, // 43 : GPIO5 interrupt 0 - GPIO51_IRQHandler, // 44 : GPIO5 interrupt 1 - UTICK0_IRQHandler, // 45 : Micro-Tick Timer interrupt - MRT0_IRQHandler, // 46 : Multi-Rate Timer interrupt - CTIMER0_IRQHandler, // 47 : Standard counter/timer 0 interrupt - CTIMER1_IRQHandler, // 48 : Standard counter/timer 1 interrupt - SCT0_IRQHandler, // 49 : SCTimer/PWM interrupt - CTIMER2_IRQHandler, // 50 : Standard counter/timer 2 interrupt - LP_FLEXCOMM0_IRQHandler, // 51 : LP_FLEXCOMM0 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM1_IRQHandler, // 52 : LP_FLEXCOMM1 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM2_IRQHandler, // 53 : LP_FLEXCOMM2 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM3_IRQHandler, // 54 : LP_FLEXCOMM3 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM4_IRQHandler, // 55 : LP_FLEXCOMM4 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM5_IRQHandler, // 56 : LP_FLEXCOMM5 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM6_IRQHandler, // 57 : LP_FLEXCOMM6 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM7_IRQHandler, // 58 : LP_FLEXCOMM7 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM8_IRQHandler, // 59 : LP_FLEXCOMM8 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM9_IRQHandler, // 60 : LP_FLEXCOMM9 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - ADC0_IRQHandler, // 61 : Analog-to-Digital Converter 0 - General Purpose - // interrupt - ADC1_IRQHandler, // 62 : Analog-to-Digital Converter 1 - General Purpose - // interrupt - PINT0_IRQHandler, // 63 : Pin Interrupt Pattern Match Interrupt - PDM_EVENT_IRQHandler, // 64 : Microphone Interface interrupt - Reserved65_IRQHandler, // 65 : Reserved interrupt - USB0_FS_IRQHandler, // 66 : Universal Serial Bus - Full Speed interrupt - USB0_DCD_IRQHandler, // 67 : Universal Serial Bus - Device Charge Detect - // interrupt - RTC_IRQHandler, // 68 : RTC Subsystem interrupt (RTC interrupt or Wake - // timer interrupt) - SMARTDMA_IRQHandler, // 69 : SmartDMA_IRQ - MAILBOX_IRQHandler, // 70 : Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU - // Mailbox interrupt1 for CPU1 - CTIMER3_IRQHandler, // 71 : Standard counter/timer 3 interrupt - CTIMER4_IRQHandler, // 72 : Standard counter/timer 4 interrupt - OS_EVENT_IRQHandler, // 73 : OS event timer interrupt - FLEXSPI0_IRQHandler, // 74 : Flexible Serial Peripheral Interface interrupt - SAI0_IRQHandler, // 75 : Serial Audio Interface 0 interrupt - SAI1_IRQHandler, // 76 : Serial Audio Interface 1 interrupt - USDHC0_IRQHandler, // 77 : Ultra Secured Digital Host Controller interrupt - CAN0_IRQHandler, // 78 : Controller Area Network 0 interrupt - CAN1_IRQHandler, // 79 : Controller Area Network 1 interrupt - Reserved80_IRQHandler, // 80 : Reserved interrupt - Reserved81_IRQHandler, // 81 : Reserved interrupt - USB1_HS_PHY_IRQHandler, // 82 : USBHS DCD or USBHS Phy interrupt - USB1_HS_IRQHandler, // 83 : USB High Speed OTG Controller interrupt - SEC_HYPERVISOR_CALL_IRQHandler, // 84 : AHB Secure Controller hypervisor - // call interrupt - Reserved85_IRQHandler, // 85 : Reserved interrupt - PLU_IRQHandler, // 86 : Programmable Logic Unit interrupt - Freqme_IRQHandler, // 87 : Frequency Measurement interrupt - SEC_VIO_IRQHandler, // 88 : Secure violation interrupt (Memory Block - // Checker interrupt or secure AHB matrix violation - // interrupt) - ELS_IRQHandler, // 89 : ELS interrupt - PKC_IRQHandler, // 90 : PKC interrupt - PUF_IRQHandler, // 91 : Physical Unclonable Function interrupt - PQ_IRQHandler, // 92 : Power Quad interrupt - EDMA_1_CH0_IRQHandler, // 93 : eDMA_1_CH0 error or transfer complete - EDMA_1_CH1_IRQHandler, // 94 : eDMA_1_CH1 error or transfer complete - EDMA_1_CH2_IRQHandler, // 95 : eDMA_1_CH2 error or transfer complete - EDMA_1_CH3_IRQHandler, // 96 : eDMA_1_CH3 error or transfer complete - EDMA_1_CH4_IRQHandler, // 97 : eDMA_1_CH4 error or transfer complete - EDMA_1_CH5_IRQHandler, // 98 : eDMA_1_CH5 error or transfer complete - EDMA_1_CH6_IRQHandler, // 99 : eDMA_1_CH6 error or transfer complete - EDMA_1_CH7_IRQHandler, // 100: eDMA_1_CH7 error or transfer complete - EDMA_1_CH8_IRQHandler, // 101: eDMA_1_CH8 error or transfer complete - EDMA_1_CH9_IRQHandler, // 102: eDMA_1_CH9 error or transfer complete - EDMA_1_CH10_IRQHandler, // 103: eDMA_1_CH10 error or transfer complete - EDMA_1_CH11_IRQHandler, // 104: eDMA_1_CH11 error or transfer complete - EDMA_1_CH12_IRQHandler, // 105: eDMA_1_CH12 error or transfer complete - EDMA_1_CH13_IRQHandler, // 106: eDMA_1_CH13 error or transfer complete - EDMA_1_CH14_IRQHandler, // 107: eDMA_1_CH14 error or transfer complete - EDMA_1_CH15_IRQHandler, // 108: eDMA_1_CH15 error or transfer complete - CDOG0_IRQHandler, // 109: Code Watchdog Timer 0 interrupt - CDOG1_IRQHandler, // 110: Code Watchdog Timer 1 interrupt - I3C0_IRQHandler, // 111: Improved Inter Integrated Circuit interrupt 0 - I3C1_IRQHandler, // 112: Improved Inter Integrated Circuit interrupt 1 - NPU_IRQHandler, // 113: NPU interrupt - GDET_IRQHandler, // 114: Digital Glitch Detect 0 interrupt or Digital - // Glitch Detect 1 interrupt - VBAT0_IRQHandler, // 115: VBAT interrupt( VBAT interrupt or digital tamper - // interrupt) - EWM0_IRQHandler, // 116: External Watchdog Monitor interrupt - TSI_END_OF_SCAN_IRQHandler, // 117: TSI End of Scan interrupt - TSI_OUT_OF_SCAN_IRQHandler, // 118: TSI Out of Scan interrupt - EMVSIM0_IRQHandler, // 119: EMVSIM0 interrupt - EMVSIM1_IRQHandler, // 120: EMVSIM1 interrupt - FLEXIO_IRQHandler, // 121: Flexible Input/Output interrupt - DAC0_IRQHandler, // 122: Digital-to-Analog Converter 0 - General Purpose - // interrupt - DAC1_IRQHandler, // 123: Digital-to-Analog Converter 1 - General Purpose - // interrupt - DAC2_IRQHandler, // 124: 14-bit Digital-to-Analog Converter interrupt - HSCMP0_IRQHandler, // 125: High-Speed comparator0 interrupt - HSCMP1_IRQHandler, // 126: High-Speed comparator1 interrupt - HSCMP2_IRQHandler, // 127: High-Speed comparator2 interrupt - FLEXPWM0_RELOAD_ERROR_IRQHandler, // 128: FlexPWM0_reload_error interrupt - FLEXPWM0_FAULT_IRQHandler, // 129: FlexPWM0_fault interrupt - FLEXPWM0_SUBMODULE0_IRQHandler, // 130: FlexPWM0 Submodule 0 - // capture/compare/reload interrupt - FLEXPWM0_SUBMODULE1_IRQHandler, // 131: FlexPWM0 Submodule 1 - // capture/compare/reload interrupt - FLEXPWM0_SUBMODULE2_IRQHandler, // 132: FlexPWM0 Submodule 2 - // capture/compare/reload interrupt - FLEXPWM0_SUBMODULE3_IRQHandler, // 133: FlexPWM0 Submodule 3 - // capture/compare/reload interrupt - FLEXPWM1_RELOAD_ERROR_IRQHandler, // 134: FlexPWM1_reload_error interrupt - FLEXPWM1_FAULT_IRQHandler, // 135: FlexPWM1_fault interrupt - FLEXPWM1_SUBMODULE0_IRQHandler, // 136: FlexPWM1 Submodule 0 - // capture/compare/reload interrupt - FLEXPWM1_SUBMODULE1_IRQHandler, // 137: FlexPWM1 Submodule 1 - // capture/compare/reload interrupt - FLEXPWM1_SUBMODULE2_IRQHandler, // 138: FlexPWM1 Submodule 2 - // capture/compare/reload interrupt - FLEXPWM1_SUBMODULE3_IRQHandler, // 139: FlexPWM1 Submodule 3 - // capture/compare/reload interrupt - ENC0_COMPARE_IRQHandler, // 140: ENC0_Compare interrupt - ENC0_HOME_IRQHandler, // 141: ENC0_Home interrupt - ENC0_WDG_SAB_IRQHandler, // 142: ENC0_WDG_IRQ/SAB interrupt - ENC0_IDX_IRQHandler, // 143: ENC0_IDX interrupt - ENC1_COMPARE_IRQHandler, // 144: ENC1_Compare interrupt - ENC1_HOME_IRQHandler, // 145: ENC1_Home interrupt - ENC1_WDG_SAB_IRQHandler, // 146: ENC1_WDG_IRQ/SAB interrupt - ENC1_IDX_IRQHandler, // 147: ENC1_IDX interrupt - ITRC0_IRQHandler, // 148: Intrusion and Tamper Response Controller - // interrupt - BSP32_IRQHandler, // 149: CoolFlux BSP32 interrupt - ELS_ERR_IRQHandler, // 150: ELS error interrupt - PKC_ERR_IRQHandler, // 151: PKC error interrupt - ERM_SINGLE_BIT_ERROR_IRQHandler, // 152: ERM Single Bit error interrupt - ERM_MULTI_BIT_ERROR_IRQHandler, // 153: ERM Multi Bit error interrupt - FMU0_IRQHandler, // 154: Flash Management Unit interrupt - ETHERNET_IRQHandler, // 155: Ethernet QoS interrupt - ETHERNET_PMT_IRQHandler, // 156: Ethernet QoS power management interrupt - ETHERNET_MACLP_IRQHandler, // 157: Ethernet QoS MAC interrupt - SINC_FILTER_IRQHandler, // 158: SINC Filter interrupt - LPTMR0_IRQHandler, // 159: Low Power Timer 0 interrupt - LPTMR1_IRQHandler, // 160: Low Power Timer 1 interrupt - SCG_IRQHandler, // 161: System Clock Generator interrupt - SPC_IRQHandler, // 162: System Power Controller interrupt - WUU_IRQHandler, // 163: Wake Up Unit interrupt - PORT_EFT_IRQHandler, // 164: PORT0~5 EFT interrupt - ETB0_IRQHandler, // 165: ETB counter expires interrupt - SM3_IRQHandler, // 166: Secure Generic Interface (SGI) SAFO interrupt - TRNG0_IRQHandler, // 167: True Random Number Generator interrupt - WWDT0_IRQHandler, // 168: Windowed Watchdog Timer 0 interrupt - WWDT1_IRQHandler, // 169: Windowed Watchdog Timer 1 interrupt - CMC0_IRQHandler, // 170: Core Mode Controller interrupt - CTI0_IRQHandler, // 171: Cross Trigger Interface interrupt -}; - -extern unsigned char _end[]; // End of data section, start of heap. See link.ld -__attribute__((naked, noreturn)) void Reset_Handler(void) { - __asm("cpsid i"); // Disable interrupts - // set SPLIM to somewhere, trick the linker - __asm volatile("MSR MSPLIM, %1 \n" - : - : "r"(tab), "r"(_end) - : "r0", "r1"); - SYSCON->ECC_ENABLE_CTRL = 0; // disable RAM ECC, must do for this link.ld - // Clear BSS section, and copy data section from flash to RAM - extern long _sbss, _ebss, _sdata, _edata, _sidata; - for (long *dst = &_sbss; dst < &_ebss; dst++) *dst = 0; - for (long *dst = &_sdata, *src = &_sidata; dst < &_edata;) *dst++ = *src++; - - SystemInit(); - - __asm("cpsie i"); // Reenable interrupts - - // Call main() - extern void main(void); - main(); - for (;;) (void) 0; // Infinite loop -} - -void Default_Handler(void) { - for (;;) (void) 0; -} diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/FreeRTOSConfig.h b/examples/nxp/frdm-mcxn947-make-freertos-builtin/FreeRTOSConfig.h deleted file mode 100644 index a3057744..00000000 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/FreeRTOSConfig.h +++ /dev/null @@ -1,44 +0,0 @@ -#pragma once - -#include "hal.h" - -#define configUSE_PREEMPTION 1 -#define configCPU_CLOCK_HZ SYS_FREQUENCY -#define configTICK_RATE_HZ 1000 -#define configMAX_PRIORITIES 5 -#define configUSE_16_BIT_TICKS 0 -#define configUSE_TICK_HOOK 0 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TIMERS 0 -#define configUSE_CO_ROUTINES 0 -#define configUSE_MALLOC_FAILED_HOOK 0 -#define configMINIMAL_STACK_SIZE 128 -#define configTOTAL_HEAP_SIZE (1024 * 128) -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_xTaskGetSchedulerState 1 // trying - -#ifdef __NVIC_PRIO_BITS -#define configPRIO_BITS __NVIC_PRIO_BITS -#else -#define configPRIO_BITS 3 -#endif -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1) -#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 3 -#define configKERNEL_INTERRUPT_PRIORITY \ - (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) - -#define configMAX_SYSCALL_INTERRUPT_PRIORITY \ - (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) - -#define configASSERT(expr) \ - if (!(expr)) printf("FAILURE %s:%d: %s\n", __FILE__, __LINE__, #expr) - -// https://www.freertos.org/2020/04/using-freertos-on-armv8-m-microcontrollers.html -#define configENABLE_FPU 1 -#define configENABLE_MPU 0 -#define configENABLE_TRUSTZONE 0 -#define configRUN_FREERTOS_SECURE_ONLY 1 - -//#define vPortSVCHandler SVC_Handler -//#define xPortPendSVHandler PendSV_Handler -//#define xPortSysTickHandler SysTick_Handler diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/Makefile b/examples/nxp/frdm-mcxn947-make-freertos-builtin/Makefile index 594de557..d9473350 100644 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/Makefile +++ b/examples/nxp/frdm-mcxn947-make-freertos-builtin/Makefile @@ -1,54 +1,29 @@ -CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion -CFLAGS += -Wformat-truncation -fno-common # -Wconversion is not SDK-friendly -CFLAGS += -g3 -Os -ffunction-sections -fdata-sections -CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MCXN947/ -CFLAGS += -Icmsis_mcu/devices/MCXN947/drivers -CFLAGS += -DCPU_MCXN947VDF -DCPU_MCXN947VDF_cm33 -DCPU_MCXN947VDF_cm33_core0 -CFLAGS += -mcpu=cortex-m33 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 $(CFLAGS_EXTRA) -CFLAGS += -Wno-old-style-declaration -Wno-unused-parameter # due to NXP FSL code - -LDSCRIPT = link.ld -LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map - -SOURCES = main.c hal.c -SOURCES += startup.c -SOURCES += cmsis_mcu/devices/MCXN947/drivers/fsl_clock.c cmsis_mcu/devices/MCXN947/drivers/fsl_spc.c cmsis_mcu/devices/MCXN947/drivers/fsl_common_arm.c # NXP support files - -# FreeRTOS. MCXN947 has a Cortex-M33 (ARMv8) core, the CM4F port can be used if TrustZone and the MPU are not to be used -SOURCES += FreeRTOS-Kernel/portable/MemMang/heap_4.c -SOURCES += FreeRTOS-Kernel/portable/GCC/ARM_CM33_NTZ/non_secure/port.c -SOURCES += FreeRTOS-Kernel/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c -CFLAGS += -IFreeRTOS-Kernel/include -CFLAGS += -IFreeRTOS-Kernel/portable/GCC/ARM_CM33_NTZ/non_secure -Wno-conversion -Wno-unused-parameter - -# Mongoose options are defined in mongoose_config.h -SOURCES += mongoose.c net.c packed_fs.c - -# Example specific build options. See README.md -CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\" - -ifeq ($(OS),Windows_NT) - RM = cmd /C del /Q /F /S -else - RM = rm -rf -endif +BOARD = mcxn947 +IDE = GCC+make +RTOS = FreeRTOS +WIZARD_URL ?= http://mongoose.ws/wizard all build example: firmware.bin -firmware.bin: firmware.elf - arm-none-eabi-objcopy -O binary $< $@ +firmware.bin: wizard + make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./ -firmware.elf: FreeRTOS-Kernel cmsis_core cmsis_mcu $(SOURCES) hal.h link.ld mongoose_config.h FreeRTOSConfig.h Makefile - arm-none-eabi-gcc $(SOURCES) $(wildcard FreeRTOS-Kernel/*.c) $(CFLAGS) $(LDFLAGS) -o $@ - arm-none-eabi-size $@ +wizard: + hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \ + && curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip + unzip wizard.zip + cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h + + +# Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/ +DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/?? +update: firmware.bin + curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$< + +test update: CFLAGS_EXTRA ="-DUART_DEBUG=USART?" +test: update + curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt + grep 'READY, IP:' /tmp/output.txt # Check for network init -cmsis_core: # ARM CMSIS core headers - git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@ -cmsis_mcu: - wget -O $@.zip https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MCXN947_DFP.17.0.0.pack - mkdir $@ && cd $@ && unzip -q ../$@.zip -FreeRTOS-Kernel: # FreeRTOS sources - git clone --depth 1 -b V10.5.0 https://github.com/FreeRTOS/FreeRTOS-Kernel $@ clean: - $(RM) firmware.* *.su cmsis_core cmsis_mcu *.zip FreeRTOS-Kernel - + rm -rf firmware.* wizard* diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/README.md b/examples/nxp/frdm-mcxn947-make-freertos-builtin/README.md new file mode 100644 index 00000000..4c54cccd --- /dev/null +++ b/examples/nxp/frdm-mcxn947-make-freertos-builtin/README.md @@ -0,0 +1 @@ +See [Wizard](https://mongoose.ws/wizard/#/output?board=mcxn947&ide=GCC+make&rtos=FreeRTOS&file=README.md) diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/hal.c b/examples/nxp/frdm-mcxn947-make-freertos-builtin/hal.c deleted file mode 100644 index a1ff1914..00000000 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/hal.c +++ /dev/null @@ -1,184 +0,0 @@ -// Copyright (c) 2024 Cesanta Software Limited -// All rights reserved - -#include "hal.h" - -#if 0 -static volatile uint64_t s_ticks; // Milliseconds since boot -void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms - s_ticks++; -} - -bool mg_random(void *buf, size_t len) { // Use on-board RNG - for (size_t n = 0; n < len; n += sizeof(uint32_t)) { - uint32_t r = rng_read(); - memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r)); - } - return true; -} - -uint64_t mg_millis(void) { // Let Mongoose use our uptime function - return s_ticks; // Return number of milliseconds since boot -} -#endif - -void hal_init(void) { - clock_init(); // Set system clock to SYS_FREQUENCY - SystemCoreClock = SYS_FREQUENCY; // Update SystemCoreClock global var -// SysTick_Config(SystemCoreClock / 1000); // Sys tick every 1ms - // rng_init(); // TRNG is part of ELS and there is no info on that - - uart_init(UART_DEBUG, 115200); // Initialise UART - gpio_output(LED1); // Initialise LED1 - gpio_write(LED1, 1); - gpio_output(LED2); // Initialise LED2 - gpio_write(LED2, 1); - gpio_output(LED3); // Initialise LED3 - gpio_write(LED3, 1); - ethernet_init(); // Initialise Ethernet pins -} - -#if defined(__ARMCC_VERSION) -// Keil specific - implement IO printf redirection -int fputc(int c, FILE *stream) { - if (stream == stdout || stream == stderr) uart_write_byte(UART_DEBUG, c); - return c; -} -#elif defined(__GNUC__) -// ARM GCC specific. ARM GCC is shipped with Newlib C library. -// Implement newlib syscalls: -// _sbrk() for malloc -// _write() for printf redirection -// the rest are just stubs -#include // For _fstat() - -#if !defined(__MCUXPRESSO) -uint32_t SystemCoreClock; -// evaluate your use of Secure/non-Secure and modify accordingly -void SystemInit(void) { // Called automatically by startup code - SCB->CPACR |= -#if 0 - (3UL << 0 * 2) | (3UL << 1 * 2) | // Enable PowerQuad (CPO/CP1) -#endif - (3UL << 10 * 2) | (3UL << 11 * 2); // Enable FPU - __DSB(); - __ISB(); - SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; // enable LPCAC -// Read TRM 36.1 and decide whether you really want to enable aGDET and dGDET -#if 1 - // Disable aGDET and dGDET - ITRC0->OUT_SEL[4][0] = - (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | - (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); - ITRC0->OUT_SEL[4][1] = - (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | - (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); - SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; - SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; - SPC0->GLITCH_DETECT_SC = 0x3C; - SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; - ITRC0->OUT_SEL[4][0] = - (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | - (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); - ITRC0->OUT_SEL[4][1] = - (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | - (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); - GDET0->GDET_ENABLE1 = 0; - GDET1->GDET_ENABLE1 = 0; -#endif -} -#endif - -int _fstat(int fd, struct stat *st) { - (void) fd, (void) st; - return -1; -} - -#if !defined(__MCUXPRESSO) -extern unsigned char _end[]; // End of data section, start of heap. See link.ld -static unsigned char *s_current_heap_end = _end; - -size_t hal_ram_used(void) { - return (size_t) (s_current_heap_end - _end); -} - -size_t hal_ram_free(void) { - unsigned char endofstack; - return (size_t) (&endofstack - s_current_heap_end); -} - -void *_sbrk(int incr) { - unsigned char *prev_heap; - prev_heap = s_current_heap_end; - s_current_heap_end += incr; - return prev_heap; -} -#endif - -int _open(const char *path) { - (void) path; - return -1; -} - -int _close(int fd) { - (void) fd; - return -1; -} - -int _isatty(int fd) { - (void) fd; - return 1; -} - -int _lseek(int fd, int ptr, int dir) { - (void) fd, (void) ptr, (void) dir; - return 0; -} - -void _exit(int status) { - (void) status; - for (;;) asm volatile("BKPT #0"); -} - -void _kill(int pid, int sig) { - (void) pid, (void) sig; -} - -int _getpid(void) { - return -1; -} - -int _write(int fd, char *ptr, int len) { - (void) fd, (void) ptr, (void) len; - if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len); - return -1; -} - -int _read(int fd, char *ptr, int len) { - (void) fd, (void) ptr, (void) len; - return -1; -} - -int _link(const char *a, const char *b) { - (void) a, (void) b; - return -1; -} - -int _unlink(const char *a) { - (void) a; - return -1; -} - -int _stat(const char *path, struct stat *st) { - (void) path, (void) st; - return -1; -} - -int mkdir(const char *path, mode_t mode) { - (void) path, (void) mode; - return -1; -} - -void _init(void) { -} -#endif // __GNUC__ diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/hal.h b/examples/nxp/frdm-mcxn947-make-freertos-builtin/hal.h deleted file mode 100644 index ccd8b2b3..00000000 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/hal.h +++ /dev/null @@ -1,223 +0,0 @@ -// Copyright (c) 2023 Cesanta Software Limited -// All rights reserved - -#pragma once - -#include -#include -#include -#include - -#define LED1 PIN(0, 10) -#define LED2 PIN(0, 27) -#define LED3 PIN(1, 2) - -#ifndef UART_DEBUG -#define UART_DEBUG LPUART4 -#endif - -#include "MCXN947_cm33_core0.h" - -#define BIT(x) (1UL << (x)) -#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set)) -#define PIN(bank, num) ((bank << 8) | (num)) -#define PINNO(pin) (pin & 255) -#define PINBANK(pin) (pin >> 8) - -void hal_init(void); -size_t hal_ram_free(void); -size_t hal_ram_used(void); - -static inline void spin(volatile uint32_t count) { - while (count--) (void) 0; -} - -#define SYS_FREQUENCY 150000000UL - -enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT }; -enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN }; -enum { GPIO_SPEED_LOW, GPIO_SPEED_HIGH }; -enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP }; -static inline GPIO_Type *gpio_bank(uint16_t pin) { - static GPIO_Type *const g[] = GPIO_BASE_PTRS; - return g[PINBANK(pin)]; -} - -static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type, - uint8_t speed, uint8_t pull, uint8_t af) { - static PORT_Type *const p[] = PORT_BASE_PTRS; - PORT_Type *port = p[PINBANK(pin)]; - GPIO_Type *gpio = gpio_bank(pin); - uint32_t mask = (uint32_t) BIT(PINNO(pin)); - bool dopull = pull > 0; - if (dopull) --pull; - if (gpio != GPIO5) { - SYSCON->AHBCLKCTRL0 |= - (1 << (SYSCON_AHBCLKCTRL0_GPIO0_SHIFT + PINBANK(pin))) | - (1 << (SYSCON_AHBCLKCTRL0_PORT0_SHIFT + PINBANK(pin))); - }; - port->PCR[PINNO(pin)] = PORT_PCR_IBE(1) | PORT_PCR_MUX(af) | PORT_PCR_DSE(1) | - PORT_PCR_ODE(type) | - PORT_PCR_SRE(speed != GPIO_SPEED_HIGH) | - PORT_PCR_PE(dopull) | PORT_PCR_PS(pull); - gpio->ICR[PINNO(pin)] = GPIO_ICR_ISF_MASK; - if (mode == GPIO_MODE_INPUT) { - gpio->PDDR &= ~mask; - } else { - gpio->PDDR |= mask; - } -} - -static inline void gpio_input(uint16_t pin) { - gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW, - GPIO_PULL_NONE, 0); -} -static inline void gpio_output(uint16_t pin) { - gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW, - GPIO_PULL_NONE, 0); -} - -static inline bool gpio_read(uint16_t pin) { - GPIO_Type *gpio = gpio_bank(pin); - return gpio->PDR[PINNO(pin)]; -} - -static inline void gpio_write(uint16_t pin, bool value) { - GPIO_Type *gpio = gpio_bank(pin); - if (value) { - gpio->PDR[PINNO(pin)] = 1; - } else { - gpio->PDR[PINNO(pin)] = 0; - } -} - -static inline void gpio_toggle(uint16_t pin) { - GPIO_Type *gpio = gpio_bank(pin); - uint32_t mask = (uint32_t) BIT(PINNO(pin)); - gpio->PTOR = mask; -} - -// MCU-Link UART (P1_9/8; FC4_P1/0) -// Arduino J1_2/4 UART (P4_3/2; FC2_P3/2) -// 33.3.23 LP_FLEXCOMM clocking -// 66.2.4 LP_FLEXCOMM init -// 66.5 LPUART -static inline void uart_init(LPUART_Type *uart, unsigned long baud) { - static LP_FLEXCOMM_Type *const f[] = LP_FLEXCOMM_BASE_PTRS; - uint8_t af = 2, fc = 0; // Alternate function, FlexComm instance - uint16_t pr = 0, pt = 0; // pins - uint32_t freq = 12000000; // fro_12_m - if (uart == LPUART2) fc = 2, pt = PIN(4, 3), pr = PIN(4, 2); - if (uart == LPUART4) fc = 4, pt = PIN(1, 9), pr = PIN(1, 8); - - SYSCON->AHBCLKCTRL1 |= (1 << (SYSCON_AHBCLKCTRL1_FC0_SHIFT + fc)); - SYSCON->PRESETCTRL1 |= (1 << (SYSCON_PRESETCTRL1_FC0_RST_SHIFT + fc)); - SYSCON->PRESETCTRL1 &= ~(1 << (SYSCON_PRESETCTRL1_FC0_RST_SHIFT + fc)); - SYSCON->FCCLKSEL[fc] = SYSCON_FCCLKSEL_SEL(2); // clock from FRO_12M / 1 - SYSCON->FLEXCOMMCLKDIV[fc] = SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(0); - LP_FLEXCOMM_Type *flexcomm = f[fc]; - flexcomm->PSELID = LP_FLEXCOMM_PSELID_PERSEL(1); // configure as UART - gpio_init(pt, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW, - GPIO_PULL_UP, af); - gpio_init(pr, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW, - GPIO_PULL_UP, af); - - uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults - uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; - // use a weird oversample ratio of 26x to fit specs, standard 16x won't do - CLRSET(uart->BAUD, - LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK, - LPUART_BAUD_OSR(26 - 1) | LPUART_BAUD_SBR(freq / (26 * baud))); - CLRSET(uart->CTRL, - LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | - LPUART_CTRL_IDLECFG_MASK, - LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) | - LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit - uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK; -} - -static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) { - uart->DATA = byte; - while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1); -} -static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) { - while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++); -} - -static inline void rng_init(void) { -} -static inline uint32_t rng_read(void) { - return 42; -} - -// - PHY and MAC clocked via a 50MHz oscillator, P1_4 (ENET0_TXCLK) -// - 33.3.30 ENET clocking -// - SMI clocked from AHB module clock (CSR) -// - PHY RST connected to P5_8 -// - PHY RXD0,1,DV = 1 on RST enable autonegotiation, no hw pull-ups -static inline void ethernet_init(void) { - // '0' in clk_rmii, set for RMII mode - SYSCON->ENETRMIICLKSEL = SYSCON_ENETRMIICLKSEL_SEL(0); - SYSCON->ENETRMIICLKDIV = SYSCON_ENETRMIICLKDIV_DIV(0); - SYSCON->AHBCLKCTRL2 |= SYSCON_AHBCLKCTRL2_ENET_MASK; // enable bus clk - SYSCON0->PRESETCTRL2 = SYSCON_PRESETCTRL2_ENET_RST_MASK; // reset MAC - SYSCON0->PRESETCTRL2 &= ~SYSCON_PRESETCTRL2_ENET_RST_MASK; // then set RMII - SYSCON0->ENET_PHY_INTF_SEL |= SYSCON_ENET_PHY_INTF_SEL_PHY_SEL_MASK; - gpio_init(PIN(5, 8), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_LOW, - GPIO_PULL_NONE, 0); // set P5_8 as GPIO (PHY \RST) - gpio_write(PIN(5, 8), 0); // reset PHY - gpio_init(PIN(1, 4), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_NONE, 9); // set P1_4 as ENET0_TXCLK - gpio_init(PIN(1, 5), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_NONE, 9); // set P1_5 as ENET0_TXEN - gpio_init(PIN(1, 6), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_NONE, 9); // set P1_6 as ENET0_TXD0 - gpio_init(PIN(1, 7), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_NONE, 9); // set P1_7 as ENET0_TXD1 - gpio_init(PIN(1, 13), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_UP, 9); // set P1_13 as ENET0_RXDV - gpio_init(PIN(1, 14), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_UP, 9); // set P1_14 as ENET0_RXD0 - gpio_init(PIN(1, 15), GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_UP, 9); // set P1_15 as ENET0_RXD1 - gpio_init(PIN(1, 20), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_NONE, 9); // set P1_20 as ENET0_MDC - gpio_init(PIN(1, 21), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, - GPIO_PULL_NONE, 9); // set P1_21 as ENET0_MDIO - spin(10000); // keep PHY RST low for a while - gpio_write(PIN(5, 8), 1); // deassert RST - NVIC_EnableIRQ(ETHERNET_IRQn); // Setup Ethernet IRQ handler -} - -#include "fsl_clock.h" -#include "fsl_spc.h" - -// 33.2 Figure 127 SCG main clock -static inline void clock_init(void) { - SYSCON->AHBCLKCTRL2 |= SYSCON_AHBCLKCTRL2_SCG_MASK; // enable SCG clk - CLRSET(SCG0->RCCR, SCG_CSR_SCS_MASK, SCG_CSR_SCS(2)); // clock main_clock - spc_active_mode_dcdc_option_t dcdc = { - .DCDCVoltage = kSPC_DCDC_OverdriveVoltage, - .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength}; - SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdc); // Set DCDC to 1.2 V - spc_active_mode_core_ldo_option_t ldo = { - .CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage, - .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength}; - SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo); // Set LDO_CORE to 1.2 V - CLRSET(FMU0->FCTRL, FMU_FCTRL_RWSC_MASK, FMU_FCTRL_RWSC(3)); // Set Flash WS - spc_sram_voltage_config_t sram = {.operateVoltage = kSPC_sramOperateAt1P2V, - .requestVoltageUpdate = true}; - SPC_SetSRAMOperateVoltage(SPC0, &sram); // Set SRAM timing for 1.2V - CLOCK_SetupFROHFClocking(48000000U); // Enable FRO HF - const pll_setup_t pll0 = {.pllctrl = SCG_APLLCTRL_SOURCE(1U) | - SCG_APLLCTRL_SELI(27U) | - SCG_APLLCTRL_SELP(13U), - .pllndiv = SCG_APLLNDIV_NDIV(8U), - .pllpdiv = SCG_APLLPDIV_PDIV(1U), - .pllmdiv = SCG_APLLMDIV_MDIV(50U), - .pllRate = 150000000U}; - CLOCK_SetPLL0Freq(&pll0); // Setup PLL0 (APLL), - CLOCK_SetPll0MonitorMode(0); // disable monitor mode - CLRSET(SCG0->RCCR, SCG_CSR_SCS_MASK, SCG_CSR_SCS(5)); // clock main_clock - SYSCON->AHBCLKDIV = SYSCON_AHBCLKDIV_DIV(0); // /1 -} diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/link.ld b/examples/nxp/frdm-mcxn947-make-freertos-builtin/link.ld deleted file mode 100644 index 042b9e6d..00000000 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/link.ld +++ /dev/null @@ -1,30 +0,0 @@ -OUTPUT_FORMAT("elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(Reset_Handler) - -MEMORY -{ - flash(RX) : ORIGIN = 0x0, LENGTH = 0x100000 - flash2(RX) : ORIGIN = 0x100000, LENGTH = 0x100000 - sram(!RX) : ORIGIN = 0x20000000, LENGTH = 0x60000 -} - -_estack = ORIGIN(sram) + LENGTH(sram); - -SECTIONS -{ - .vectors : { FILL(256) KEEP(*(.isr_vector)) } > flash - .text : { *(.text*) } > flash - .data : { - _sdata = .; - *(.first_data) - *(.data SORT(.data.*)) - _edata = .; - } > sram AT > flash - _sidata = LOADADDR(.data); - - .bss : { _sbss = .; *(.bss SORT(.bss.*) COMMON) _ebss = .; } > sram - - . = ALIGN(8); - _end = .; - } diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/main.c b/examples/nxp/frdm-mcxn947-make-freertos-builtin/main.c deleted file mode 100644 index 7a4d42c6..00000000 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/main.c +++ /dev/null @@ -1,42 +0,0 @@ -// Copyright (c) 2024 Cesanta Software Limited -// All rights reserved - -#include "hal.h" -#include "mongoose.h" -#include "net.h" - -#define BLINK_PERIOD_MS 1000 // LED blinking period in millis - -static void server(void *args) { - struct mg_mgr mgr; // Initialise Mongoose event manager - mg_mgr_init(&mgr); // and attach it to the interface - mg_log_set(MG_LL_DEBUG); // Set log level - - MG_INFO(("Initialising application...")); - web_init(&mgr); - - MG_INFO(("Starting event loop")); - for (;;) mg_mgr_poll(&mgr, 1); // Infinite event loop - (void) args; -} - -static void blinker(void *args) { - gpio_output(LED1); - for (;;) { - gpio_toggle(LED1); - vTaskDelay(pdMS_TO_TICKS(BLINK_PERIOD_MS)); - } - (void) args; -} - -int main(void) { - - hal_init(); // Cross-platform hardware init - - // Start tasks. NOTE: stack sizes are in 32-bit words - xTaskCreate(blinker, "blinker", 128, ":)", configMAX_PRIORITIES - 1, NULL); - xTaskCreate(server, "server", 2048, 0, configMAX_PRIORITIES - 1, NULL); - - vTaskStartScheduler(); // This blocks - return 0; -} diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/mongoose.c b/examples/nxp/frdm-mcxn947-make-freertos-builtin/mongoose.c deleted file mode 120000 index 5e522bbc..00000000 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/mongoose.c +++ /dev/null @@ -1 +0,0 @@ -../../../mongoose.c \ No newline at end of file diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/mongoose.h b/examples/nxp/frdm-mcxn947-make-freertos-builtin/mongoose.h deleted file mode 120000 index ee4ac823..00000000 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/mongoose.h +++ /dev/null @@ -1 +0,0 @@ -../../../mongoose.h \ No newline at end of file diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/mongoose_config.h b/examples/nxp/frdm-mcxn947-make-freertos-builtin/mongoose_config.h deleted file mode 100644 index f8da4241..00000000 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/mongoose_config.h +++ /dev/null @@ -1,26 +0,0 @@ -#pragma once - -#include // we are not using lwIP - -// See https://mongoose.ws/documentation/#build-options -#define MG_ARCH MG_ARCH_FREERTOS - -#define MG_ENABLE_TCPIP 1 -#define MG_ENABLE_DRIVER_MCXN 1 -//#define MG_ENABLE_CUSTOM_RANDOM 1 -#define MG_ENABLE_PACKED_FS 1 - -// For static IP configuration, define MG_TCPIP_{IP,MASK,GW} -// By default, those are set to zero, meaning that DHCP is used -// -// #define MG_TCPIP_IP MG_IPV4(192, 168, 1, 10) -// #define MG_TCPIP_GW MG_IPV4(192, 168, 1, 1) -// #define MG_TCPIP_MASK MG_IPV4(255, 255, 255, 0) - -// Set custom MAC address. By default, it is randomly generated -// Using a build-time constant: -// #define MG_SET_MAC_ADDRESS(mac) do { uint8_t buf_[6] = {2,3,4,5,6,7}; memmove(mac, buf_, sizeof(buf_)); } while (0) -// -// Using custom function: -// extern void my_function(unsigned char *mac); -// #define MG_SET_MAC_ADDRESS(mac) my_function(mac) diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/net.c b/examples/nxp/frdm-mcxn947-make-freertos-builtin/net.c deleted file mode 120000 index fe0e6f06..00000000 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/net.c +++ /dev/null @@ -1 +0,0 @@ -../../device-dashboard/net.c \ No newline at end of file diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/net.h b/examples/nxp/frdm-mcxn947-make-freertos-builtin/net.h deleted file mode 120000 index 9de896ef..00000000 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/net.h +++ /dev/null @@ -1 +0,0 @@ -../../device-dashboard/net.h \ No newline at end of file diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/packed_fs.c b/examples/nxp/frdm-mcxn947-make-freertos-builtin/packed_fs.c deleted file mode 120000 index e06bf092..00000000 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/packed_fs.c +++ /dev/null @@ -1 +0,0 @@ -../../device-dashboard/packed_fs.c \ No newline at end of file diff --git a/examples/nxp/frdm-mcxn947-make-freertos-builtin/startup.c b/examples/nxp/frdm-mcxn947-make-freertos-builtin/startup.c deleted file mode 100644 index 0ab97c1b..00000000 --- a/examples/nxp/frdm-mcxn947-make-freertos-builtin/startup.c +++ /dev/null @@ -1,411 +0,0 @@ -#include "MCXN947_cm33_core0.h" - -void Reset_Handler(void); // Defined below -void Dummy_Handler(void); // Defined below -void SysTick_Handler(void); // Defined in main.c -void SystemInit(void); // Defined in main.c, called by reset handler -void _estack(void); // Defined in link.ld - -#define WEAK_ALIAS __attribute__((weak, alias("Default_Handler"))) - -WEAK_ALIAS void NMI_Handler(void); -WEAK_ALIAS void HardFault_Handler(void); -WEAK_ALIAS void MemManage_Handler(void); -WEAK_ALIAS void BusFault_Handler(void); -WEAK_ALIAS void UsageFault_Handler(void); -WEAK_ALIAS void SecureFault_Handler(void); -WEAK_ALIAS void DebugMon_Handler(void); -WEAK_ALIAS void SVC_Handler(void); -WEAK_ALIAS void PendSV_Handler(void); -WEAK_ALIAS void SysTick_Handler(void); - -WEAK_ALIAS void OR_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH0_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH1_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH2_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH3_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH4_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH5_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH6_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH7_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH8_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH9_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH10_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH11_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH12_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH13_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH14_IRQHandler(void); -WEAK_ALIAS void EDMA_0_CH15_IRQHandler(void); -WEAK_ALIAS void GPIO00_IRQHandler(void); -WEAK_ALIAS void GPIO01_IRQHandler(void); -WEAK_ALIAS void GPIO10_IRQHandler(void); -WEAK_ALIAS void GPIO11_IRQHandler(void); -WEAK_ALIAS void GPIO20_IRQHandler(void); -WEAK_ALIAS void GPIO21_IRQHandler(void); -WEAK_ALIAS void GPIO30_IRQHandler(void); -WEAK_ALIAS void GPIO31_IRQHandler(void); -WEAK_ALIAS void GPIO40_IRQHandler(void); -WEAK_ALIAS void GPIO41_IRQHandler(void); -WEAK_ALIAS void GPIO50_IRQHandler(void); -WEAK_ALIAS void GPIO51_IRQHandler(void); -WEAK_ALIAS void UTICK0_IRQHandler(void); -WEAK_ALIAS void MRT0_IRQHandler(void); -WEAK_ALIAS void CTIMER0_IRQHandler(void); -WEAK_ALIAS void CTIMER1_IRQHandler(void); -WEAK_ALIAS void SCT0_IRQHandler(void); -WEAK_ALIAS void CTIMER2_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM0_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM1_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM2_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM3_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM4_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM5_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM6_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM7_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM8_IRQHandler(void); -WEAK_ALIAS void LP_FLEXCOMM9_IRQHandler(void); -WEAK_ALIAS void ADC0_IRQHandler(void); -WEAK_ALIAS void ADC1_IRQHandler(void); -WEAK_ALIAS void PINT0_IRQHandler(void); -WEAK_ALIAS void PDM_EVENT_IRQHandler(void); -WEAK_ALIAS void Reserved65_IRQHandler(void); -WEAK_ALIAS void USB0_FS_IRQHandler(void); -WEAK_ALIAS void USB0_DCD_IRQHandler(void); -WEAK_ALIAS void RTC_IRQHandler(void); -WEAK_ALIAS void SMARTDMA_IRQHandler(void); -WEAK_ALIAS void MAILBOX_IRQHandler(void); -WEAK_ALIAS void CTIMER3_IRQHandler(void); -WEAK_ALIAS void CTIMER4_IRQHandler(void); -WEAK_ALIAS void OS_EVENT_IRQHandler(void); -WEAK_ALIAS void FLEXSPI0_IRQHandler(void); -WEAK_ALIAS void SAI0_IRQHandler(void); -WEAK_ALIAS void SAI1_IRQHandler(void); -WEAK_ALIAS void USDHC0_IRQHandler(void); -WEAK_ALIAS void CAN0_IRQHandler(void); -WEAK_ALIAS void CAN1_IRQHandler(void); -WEAK_ALIAS void Reserved80_IRQHandler(void); -WEAK_ALIAS void Reserved81_IRQHandler(void); -WEAK_ALIAS void USB1_HS_PHY_IRQHandler(void); -WEAK_ALIAS void USB1_HS_IRQHandler(void); -WEAK_ALIAS void SEC_HYPERVISOR_CALL_IRQHandler(void); -WEAK_ALIAS void Reserved85_IRQHandler(void); -WEAK_ALIAS void PLU_IRQHandler(void); -WEAK_ALIAS void Freqme_IRQHandler(void); -WEAK_ALIAS void SEC_VIO_IRQHandler(void); -WEAK_ALIAS void ELS_IRQHandler(void); -WEAK_ALIAS void PKC_IRQHandler(void); -WEAK_ALIAS void PUF_IRQHandler(void); -WEAK_ALIAS void PQ_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH0_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH1_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH2_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH3_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH4_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH5_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH6_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH7_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH8_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH9_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH10_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH11_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH12_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH13_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH14_IRQHandler(void); -WEAK_ALIAS void EDMA_1_CH15_IRQHandler(void); -WEAK_ALIAS void CDOG0_IRQHandler(void); -WEAK_ALIAS void CDOG1_IRQHandler(void); -WEAK_ALIAS void I3C0_IRQHandler(void); -WEAK_ALIAS void I3C1_IRQHandler(void); -WEAK_ALIAS void NPU_IRQHandler(void); -WEAK_ALIAS void GDET_IRQHandler(void); -WEAK_ALIAS void VBAT0_IRQHandler(void); -WEAK_ALIAS void EWM0_IRQHandler(void); -WEAK_ALIAS void TSI_END_OF_SCAN_IRQHandler(void); -WEAK_ALIAS void TSI_OUT_OF_SCAN_IRQHandler(void); -WEAK_ALIAS void EMVSIM0_IRQHandler(void); -WEAK_ALIAS void EMVSIM1_IRQHandler(void); -WEAK_ALIAS void FLEXIO_IRQHandler(void); -WEAK_ALIAS void DAC0_IRQHandler(void); -WEAK_ALIAS void DAC1_IRQHandler(void); -WEAK_ALIAS void DAC2_IRQHandler(void); -WEAK_ALIAS void HSCMP0_IRQHandler(void); -WEAK_ALIAS void HSCMP1_IRQHandler(void); -WEAK_ALIAS void HSCMP2_IRQHandler(void); -WEAK_ALIAS void FLEXPWM0_RELOAD_ERROR_IRQHandler(void); -WEAK_ALIAS void FLEXPWM0_FAULT_IRQHandler(void); -WEAK_ALIAS void FLEXPWM0_SUBMODULE0_IRQHandler(void); -WEAK_ALIAS void FLEXPWM0_SUBMODULE1_IRQHandler(void); -WEAK_ALIAS void FLEXPWM0_SUBMODULE2_IRQHandler(void); -WEAK_ALIAS void FLEXPWM0_SUBMODULE3_IRQHandler(void); -WEAK_ALIAS void FLEXPWM1_RELOAD_ERROR_IRQHandler(void); -WEAK_ALIAS void FLEXPWM1_FAULT_IRQHandler(void); -WEAK_ALIAS void FLEXPWM1_SUBMODULE0_IRQHandler(void); -WEAK_ALIAS void FLEXPWM1_SUBMODULE1_IRQHandler(void); -WEAK_ALIAS void FLEXPWM1_SUBMODULE2_IRQHandler(void); -WEAK_ALIAS void FLEXPWM1_SUBMODULE3_IRQHandler(void); -WEAK_ALIAS void ENC0_COMPARE_IRQHandler(void); -WEAK_ALIAS void ENC0_HOME_IRQHandler(void); -WEAK_ALIAS void ENC0_WDG_SAB_IRQHandler(void); -WEAK_ALIAS void ENC0_IDX_IRQHandler(void); -WEAK_ALIAS void ENC1_COMPARE_IRQHandler(void); -WEAK_ALIAS void ENC1_HOME_IRQHandler(void); -WEAK_ALIAS void ENC1_WDG_SAB_IRQHandler(void); -WEAK_ALIAS void ENC1_IDX_IRQHandler(void); -WEAK_ALIAS void ITRC0_IRQHandler(void); -WEAK_ALIAS void BSP32_IRQHandler(void); -WEAK_ALIAS void ELS_ERR_IRQHandler(void); -WEAK_ALIAS void PKC_ERR_IRQHandler(void); -WEAK_ALIAS void ERM_SINGLE_BIT_ERROR_IRQHandler(void); -WEAK_ALIAS void ERM_MULTI_BIT_ERROR_IRQHandler(void); -WEAK_ALIAS void FMU0_IRQHandler(void); -WEAK_ALIAS void ETHERNET_IRQHandler(void); -WEAK_ALIAS void ETHERNET_PMT_IRQHandler(void); -WEAK_ALIAS void ETHERNET_MACLP_IRQHandler(void); -WEAK_ALIAS void SINC_FILTER_IRQHandler(void); -WEAK_ALIAS void LPTMR0_IRQHandler(void); -WEAK_ALIAS void LPTMR1_IRQHandler(void); -WEAK_ALIAS void SCG_IRQHandler(void); -WEAK_ALIAS void SPC_IRQHandler(void); -WEAK_ALIAS void WUU_IRQHandler(void); -WEAK_ALIAS void PORT_EFT_IRQHandler(void); -WEAK_ALIAS void ETB0_IRQHandler(void); -WEAK_ALIAS void SM3_IRQHandler(void); -WEAK_ALIAS void TRNG0_IRQHandler(void); -WEAK_ALIAS void WWDT0_IRQHandler(void); -WEAK_ALIAS void WWDT1_IRQHandler(void); -WEAK_ALIAS void CMC0_IRQHandler(void); -WEAK_ALIAS void CTI0_IRQHandler(void); - -__attribute__((section(".vectors"))) void (*const tab[16 + 156])(void) = { - _estack, Reset_Handler, - NMI_Handler, // NMI Handler - HardFault_Handler, // Hard Fault Handler - MemManage_Handler, // MPU Fault Handler - BusFault_Handler, // Bus Fault Handler - UsageFault_Handler, // Usage Fault Handler - SecureFault_Handler, // Secure Fault Handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - SVC_Handler, // SVCall Handler - DebugMon_Handler, // Debug Monitor Handler - 0, // Reserved - PendSV_Handler, // PendSV Handler - SysTick_Handler, // SysTick Handler - // Chip Level - MCXN947_cm33_core0 - OR_IRQHandler, // 16 : OR IRQ - EDMA_0_CH0_IRQHandler, // 17 : eDMA_0_CH0 error or transfer complete - EDMA_0_CH1_IRQHandler, // 18 : eDMA_0_CH1 error or transfer complete - EDMA_0_CH2_IRQHandler, // 19 : eDMA_0_CH2 error or transfer complete - EDMA_0_CH3_IRQHandler, // 20 : eDMA_0_CH3 error or transfer complete - EDMA_0_CH4_IRQHandler, // 21 : eDMA_0_CH4 error or transfer complete - EDMA_0_CH5_IRQHandler, // 22 : eDMA_0_CH5 error or transfer complete - EDMA_0_CH6_IRQHandler, // 23 : eDMA_0_CH6 error or transfer complete - EDMA_0_CH7_IRQHandler, // 24 : eDMA_0_CH7 error or transfer complete - EDMA_0_CH8_IRQHandler, // 25 : eDMA_0_CH8 error or transfer complete - EDMA_0_CH9_IRQHandler, // 26 : eDMA_0_CH9 error or transfer complete - EDMA_0_CH10_IRQHandler, // 27 : eDMA_0_CH10 error or transfer complete - EDMA_0_CH11_IRQHandler, // 28 : eDMA_0_CH11 error or transfer complete - EDMA_0_CH12_IRQHandler, // 29 : eDMA_0_CH12 error or transfer complete - EDMA_0_CH13_IRQHandler, // 30 : eDMA_0_CH13 error or transfer complete - EDMA_0_CH14_IRQHandler, // 31 : eDMA_0_CH14 error or transfer complete - EDMA_0_CH15_IRQHandler, // 32 : eDMA_0_CH15 error or transfer complete - GPIO00_IRQHandler, // 33 : GPIO0 interrupt 0 - GPIO01_IRQHandler, // 34 : GPIO0 interrupt 1 - GPIO10_IRQHandler, // 35 : GPIO1 interrupt 0 - GPIO11_IRQHandler, // 36 : GPIO1 interrupt 1 - GPIO20_IRQHandler, // 37 : GPIO2 interrupt 0 - GPIO21_IRQHandler, // 38 : GPIO2 interrupt 1 - GPIO30_IRQHandler, // 39 : GPIO3 interrupt 0 - GPIO31_IRQHandler, // 40 : GPIO3 interrupt 1 - GPIO40_IRQHandler, // 41 : GPIO4 interrupt 0 - GPIO41_IRQHandler, // 42 : GPIO4 interrupt 1 - GPIO50_IRQHandler, // 43 : GPIO5 interrupt 0 - GPIO51_IRQHandler, // 44 : GPIO5 interrupt 1 - UTICK0_IRQHandler, // 45 : Micro-Tick Timer interrupt - MRT0_IRQHandler, // 46 : Multi-Rate Timer interrupt - CTIMER0_IRQHandler, // 47 : Standard counter/timer 0 interrupt - CTIMER1_IRQHandler, // 48 : Standard counter/timer 1 interrupt - SCT0_IRQHandler, // 49 : SCTimer/PWM interrupt - CTIMER2_IRQHandler, // 50 : Standard counter/timer 2 interrupt - LP_FLEXCOMM0_IRQHandler, // 51 : LP_FLEXCOMM0 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM1_IRQHandler, // 52 : LP_FLEXCOMM1 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM2_IRQHandler, // 53 : LP_FLEXCOMM2 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM3_IRQHandler, // 54 : LP_FLEXCOMM3 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM4_IRQHandler, // 55 : LP_FLEXCOMM4 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM5_IRQHandler, // 56 : LP_FLEXCOMM5 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM6_IRQHandler, // 57 : LP_FLEXCOMM6 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM7_IRQHandler, // 58 : LP_FLEXCOMM7 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM8_IRQHandler, // 59 : LP_FLEXCOMM8 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - LP_FLEXCOMM9_IRQHandler, // 60 : LP_FLEXCOMM9 (LPSPI interrupt or LPI2C - // interrupt or LPUART Receive/Transmit interrupt) - ADC0_IRQHandler, // 61 : Analog-to-Digital Converter 0 - General Purpose - // interrupt - ADC1_IRQHandler, // 62 : Analog-to-Digital Converter 1 - General Purpose - // interrupt - PINT0_IRQHandler, // 63 : Pin Interrupt Pattern Match Interrupt - PDM_EVENT_IRQHandler, // 64 : Microphone Interface interrupt - Reserved65_IRQHandler, // 65 : Reserved interrupt - USB0_FS_IRQHandler, // 66 : Universal Serial Bus - Full Speed interrupt - USB0_DCD_IRQHandler, // 67 : Universal Serial Bus - Device Charge Detect - // interrupt - RTC_IRQHandler, // 68 : RTC Subsystem interrupt (RTC interrupt or Wake - // timer interrupt) - SMARTDMA_IRQHandler, // 69 : SmartDMA_IRQ - MAILBOX_IRQHandler, // 70 : Inter-CPU Mailbox interrupt0 for CPU0 Inter-CPU - // Mailbox interrupt1 for CPU1 - CTIMER3_IRQHandler, // 71 : Standard counter/timer 3 interrupt - CTIMER4_IRQHandler, // 72 : Standard counter/timer 4 interrupt - OS_EVENT_IRQHandler, // 73 : OS event timer interrupt - FLEXSPI0_IRQHandler, // 74 : Flexible Serial Peripheral Interface interrupt - SAI0_IRQHandler, // 75 : Serial Audio Interface 0 interrupt - SAI1_IRQHandler, // 76 : Serial Audio Interface 1 interrupt - USDHC0_IRQHandler, // 77 : Ultra Secured Digital Host Controller interrupt - CAN0_IRQHandler, // 78 : Controller Area Network 0 interrupt - CAN1_IRQHandler, // 79 : Controller Area Network 1 interrupt - Reserved80_IRQHandler, // 80 : Reserved interrupt - Reserved81_IRQHandler, // 81 : Reserved interrupt - USB1_HS_PHY_IRQHandler, // 82 : USBHS DCD or USBHS Phy interrupt - USB1_HS_IRQHandler, // 83 : USB High Speed OTG Controller interrupt - SEC_HYPERVISOR_CALL_IRQHandler, // 84 : AHB Secure Controller hypervisor - // call interrupt - Reserved85_IRQHandler, // 85 : Reserved interrupt - PLU_IRQHandler, // 86 : Programmable Logic Unit interrupt - Freqme_IRQHandler, // 87 : Frequency Measurement interrupt - SEC_VIO_IRQHandler, // 88 : Secure violation interrupt (Memory Block - // Checker interrupt or secure AHB matrix violation - // interrupt) - ELS_IRQHandler, // 89 : ELS interrupt - PKC_IRQHandler, // 90 : PKC interrupt - PUF_IRQHandler, // 91 : Physical Unclonable Function interrupt - PQ_IRQHandler, // 92 : Power Quad interrupt - EDMA_1_CH0_IRQHandler, // 93 : eDMA_1_CH0 error or transfer complete - EDMA_1_CH1_IRQHandler, // 94 : eDMA_1_CH1 error or transfer complete - EDMA_1_CH2_IRQHandler, // 95 : eDMA_1_CH2 error or transfer complete - EDMA_1_CH3_IRQHandler, // 96 : eDMA_1_CH3 error or transfer complete - EDMA_1_CH4_IRQHandler, // 97 : eDMA_1_CH4 error or transfer complete - EDMA_1_CH5_IRQHandler, // 98 : eDMA_1_CH5 error or transfer complete - EDMA_1_CH6_IRQHandler, // 99 : eDMA_1_CH6 error or transfer complete - EDMA_1_CH7_IRQHandler, // 100: eDMA_1_CH7 error or transfer complete - EDMA_1_CH8_IRQHandler, // 101: eDMA_1_CH8 error or transfer complete - EDMA_1_CH9_IRQHandler, // 102: eDMA_1_CH9 error or transfer complete - EDMA_1_CH10_IRQHandler, // 103: eDMA_1_CH10 error or transfer complete - EDMA_1_CH11_IRQHandler, // 104: eDMA_1_CH11 error or transfer complete - EDMA_1_CH12_IRQHandler, // 105: eDMA_1_CH12 error or transfer complete - EDMA_1_CH13_IRQHandler, // 106: eDMA_1_CH13 error or transfer complete - EDMA_1_CH14_IRQHandler, // 107: eDMA_1_CH14 error or transfer complete - EDMA_1_CH15_IRQHandler, // 108: eDMA_1_CH15 error or transfer complete - CDOG0_IRQHandler, // 109: Code Watchdog Timer 0 interrupt - CDOG1_IRQHandler, // 110: Code Watchdog Timer 1 interrupt - I3C0_IRQHandler, // 111: Improved Inter Integrated Circuit interrupt 0 - I3C1_IRQHandler, // 112: Improved Inter Integrated Circuit interrupt 1 - NPU_IRQHandler, // 113: NPU interrupt - GDET_IRQHandler, // 114: Digital Glitch Detect 0 interrupt or Digital - // Glitch Detect 1 interrupt - VBAT0_IRQHandler, // 115: VBAT interrupt( VBAT interrupt or digital tamper - // interrupt) - EWM0_IRQHandler, // 116: External Watchdog Monitor interrupt - TSI_END_OF_SCAN_IRQHandler, // 117: TSI End of Scan interrupt - TSI_OUT_OF_SCAN_IRQHandler, // 118: TSI Out of Scan interrupt - EMVSIM0_IRQHandler, // 119: EMVSIM0 interrupt - EMVSIM1_IRQHandler, // 120: EMVSIM1 interrupt - FLEXIO_IRQHandler, // 121: Flexible Input/Output interrupt - DAC0_IRQHandler, // 122: Digital-to-Analog Converter 0 - General Purpose - // interrupt - DAC1_IRQHandler, // 123: Digital-to-Analog Converter 1 - General Purpose - // interrupt - DAC2_IRQHandler, // 124: 14-bit Digital-to-Analog Converter interrupt - HSCMP0_IRQHandler, // 125: High-Speed comparator0 interrupt - HSCMP1_IRQHandler, // 126: High-Speed comparator1 interrupt - HSCMP2_IRQHandler, // 127: High-Speed comparator2 interrupt - FLEXPWM0_RELOAD_ERROR_IRQHandler, // 128: FlexPWM0_reload_error interrupt - FLEXPWM0_FAULT_IRQHandler, // 129: FlexPWM0_fault interrupt - FLEXPWM0_SUBMODULE0_IRQHandler, // 130: FlexPWM0 Submodule 0 - // capture/compare/reload interrupt - FLEXPWM0_SUBMODULE1_IRQHandler, // 131: FlexPWM0 Submodule 1 - // capture/compare/reload interrupt - FLEXPWM0_SUBMODULE2_IRQHandler, // 132: FlexPWM0 Submodule 2 - // capture/compare/reload interrupt - FLEXPWM0_SUBMODULE3_IRQHandler, // 133: FlexPWM0 Submodule 3 - // capture/compare/reload interrupt - FLEXPWM1_RELOAD_ERROR_IRQHandler, // 134: FlexPWM1_reload_error interrupt - FLEXPWM1_FAULT_IRQHandler, // 135: FlexPWM1_fault interrupt - FLEXPWM1_SUBMODULE0_IRQHandler, // 136: FlexPWM1 Submodule 0 - // capture/compare/reload interrupt - FLEXPWM1_SUBMODULE1_IRQHandler, // 137: FlexPWM1 Submodule 1 - // capture/compare/reload interrupt - FLEXPWM1_SUBMODULE2_IRQHandler, // 138: FlexPWM1 Submodule 2 - // capture/compare/reload interrupt - FLEXPWM1_SUBMODULE3_IRQHandler, // 139: FlexPWM1 Submodule 3 - // capture/compare/reload interrupt - ENC0_COMPARE_IRQHandler, // 140: ENC0_Compare interrupt - ENC0_HOME_IRQHandler, // 141: ENC0_Home interrupt - ENC0_WDG_SAB_IRQHandler, // 142: ENC0_WDG_IRQ/SAB interrupt - ENC0_IDX_IRQHandler, // 143: ENC0_IDX interrupt - ENC1_COMPARE_IRQHandler, // 144: ENC1_Compare interrupt - ENC1_HOME_IRQHandler, // 145: ENC1_Home interrupt - ENC1_WDG_SAB_IRQHandler, // 146: ENC1_WDG_IRQ/SAB interrupt - ENC1_IDX_IRQHandler, // 147: ENC1_IDX interrupt - ITRC0_IRQHandler, // 148: Intrusion and Tamper Response Controller - // interrupt - BSP32_IRQHandler, // 149: CoolFlux BSP32 interrupt - ELS_ERR_IRQHandler, // 150: ELS error interrupt - PKC_ERR_IRQHandler, // 151: PKC error interrupt - ERM_SINGLE_BIT_ERROR_IRQHandler, // 152: ERM Single Bit error interrupt - ERM_MULTI_BIT_ERROR_IRQHandler, // 153: ERM Multi Bit error interrupt - FMU0_IRQHandler, // 154: Flash Management Unit interrupt - ETHERNET_IRQHandler, // 155: Ethernet QoS interrupt - ETHERNET_PMT_IRQHandler, // 156: Ethernet QoS power management interrupt - ETHERNET_MACLP_IRQHandler, // 157: Ethernet QoS MAC interrupt - SINC_FILTER_IRQHandler, // 158: SINC Filter interrupt - LPTMR0_IRQHandler, // 159: Low Power Timer 0 interrupt - LPTMR1_IRQHandler, // 160: Low Power Timer 1 interrupt - SCG_IRQHandler, // 161: System Clock Generator interrupt - SPC_IRQHandler, // 162: System Power Controller interrupt - WUU_IRQHandler, // 163: Wake Up Unit interrupt - PORT_EFT_IRQHandler, // 164: PORT0~5 EFT interrupt - ETB0_IRQHandler, // 165: ETB counter expires interrupt - SM3_IRQHandler, // 166: Secure Generic Interface (SGI) SAFO interrupt - TRNG0_IRQHandler, // 167: True Random Number Generator interrupt - WWDT0_IRQHandler, // 168: Windowed Watchdog Timer 0 interrupt - WWDT1_IRQHandler, // 169: Windowed Watchdog Timer 1 interrupt - CMC0_IRQHandler, // 170: Core Mode Controller interrupt - CTI0_IRQHandler, // 171: Cross Trigger Interface interrupt -}; - -extern unsigned char _end[]; // End of data section, start of heap. See link.ld -__attribute__((naked, noreturn)) void Reset_Handler(void) { - __asm("cpsid i"); // Disable interrupts - // set SPLIM to somewhere, trick the linker - __asm volatile("MSR MSPLIM, %1 \n" - : - : "r"(tab), "r"(_end) - : "r0", "r1"); - SYSCON->ECC_ENABLE_CTRL = 0; // disable RAM ECC, must do for this link.ld - // Clear BSS section, and copy data section from flash to RAM - extern long _sbss, _ebss, _sdata, _edata, _sidata; - for (long *dst = &_sbss; dst < &_ebss; dst++) *dst = 0; - for (long *dst = &_sdata, *src = &_sidata; dst < &_edata;) *dst++ = *src++; - - SystemInit(); - - __asm("cpsie i"); // Reenable interrupts - - // Call main() - extern void main(void); - main(); - for (;;) (void) 0; // Infinite loop -} - -void Default_Handler(void) { - for (;;) (void) 0; -} diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/Makefile b/examples/nxp/rt1020-evk-make-baremetal-builtin/Makefile index c0279a55..a57e8c79 100644 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/Makefile +++ b/examples/nxp/rt1020-evk-make-baremetal-builtin/Makefile @@ -1,85 +1,29 @@ -CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion -CFLAGS += -Wformat-truncation -fno-common # -Wconversion is not SDK-friendly -CFLAGS += -g3 -Os -ffunction-sections -fdata-sections -CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MIMXRT1021 -CFLAGS += -Icmsis_mcu/devices/MIMXRT1021/drivers -DCPU_MIMXRT1021DAG5A -CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA) -LDSCRIPT = link.ld -LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map +BOARD = rt1020 +IDE = GCC+make +RTOS = baremetal +WIZARD_URL ?= http://mongoose.ws/wizard -SOURCES = main.c syscalls.c sysinit.c -SOURCES += cmsis_mcu/devices/MIMXRT1021/gcc/startup_MIMXRT1021.S # NXP startup file. Compiler-dependent! -CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS # Make startup code work as expected - -# Mongoose options are defined in mongoose_config.h -SOURCES += mongoose.c net.c packed_fs.c - -# Example specific build options. See README.md -CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\" - -ifeq ($(OS),Windows_NT) - RM = cmd /C del /Q /F /S -else - RM = rm -rf -endif - -all build example update: SOURCES += flash_image.c all build example: firmware.bin -ram: LDSCRIPT = link_ram.ld -ram: firmware.bin +firmware.bin: wizard + make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./ -firmware.bin: firmware.elf - arm-none-eabi-objcopy -O binary $< $@ +wizard: + hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \ + && curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip + unzip wizard.zip + cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h -firmware.elf: cmsis_core cmsis_mcu $(SOURCES) hal.h link_ram.ld link.ld Makefile - arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@ - arm-none-eabi-size $@ - -flash: firmware.bin -# flash - -cmsis_core: # ARM CMSIS core headers - git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@ -cmsis_mcu: - curl -sL https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1021_DFP.17.0.0.pack -o $@.zip - mkdir $@ && cd $@ && unzip -q ../$@.zip -mbedtls: # mbedTLS library - git clone --depth 1 -b v2.28.2 https://github.com/mbed-tls/mbedtls $@ - -ifeq ($(TLS), mbedtls) -CFLAGS += -DMG_TLS=MG_TLS_MBED -Wno-conversion -Imbedtls/include -CFLAGS += -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" mbedtls/library/*.c -firmware.elf: mbedtls -endif # Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/ DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/4 update: firmware.bin curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$< -update updateram: CFLAGS += -DUART_DEBUG=LPUART2 - +test update: CFLAGS_EXTRA ="-DUART_DEBUG=LPUART2" test: update - curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt + curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt grep 'READY, IP:' /tmp/output.txt # Check for network init - -updateram: ram - curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @firmware.bin - curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}' - curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0003 wm,e000edfc,1 wm,e000ed0c,5fa0004"}' - curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}' - PC=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,4"}' | jq -r .resp[5:]` && \ - SP=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,0"}' | jq -r .resp[5:]` && \ - REQ="wm,e000ed08,0 wr,d,$$SP wr,f,$$PC" && \ - curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"'"$$REQ"'"}' - curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0001"}' - -testram: updateram - curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt - grep 'READY, IP:' /tmp/output.txt # Check for network init - - clean: - $(RM) firmware.* *.su cmsis_core cmsis_mcu mbedtls *.zip + rm -rf firmware.* wizard* diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/README.md b/examples/nxp/rt1020-evk-make-baremetal-builtin/README.md new file mode 100644 index 00000000..d3468433 --- /dev/null +++ b/examples/nxp/rt1020-evk-make-baremetal-builtin/README.md @@ -0,0 +1 @@ +See [Wizard](https://mongoose.ws/wizard/#/output?board=rt1020&ide=GCC+make&rtos=baremetal&file=README.md) diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/dcd.h b/examples/nxp/rt1020-evk-make-baremetal-builtin/dcd.h deleted file mode 100644 index fa43ac4f..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/dcd.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright 2020-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define __DCD_DATA \ - 0xD2, 0x03, 0xE0, 0x41, 0xCC, 0x03, 0x5C, 0x04, 0x40, 0x0F, 0xC0, 0x68, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, \ - 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x74, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, \ - 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x80, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, \ - 0x40, 0x0D, 0x81, 0x00, 0x10, 0x18, 0x10, 0x1B, 0x40, 0x0F, 0xC0, 0x14, \ - 0x00, 0x0A, 0x83, 0x40, 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x1C, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x28, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x34, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x40, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x4C, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x58, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x64, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x70, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x7C, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x10, 0x40, 0x1F, 0x80, 0x88, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x94, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA0, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xAC, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x81, 0x88, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0x8C, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0x90, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x81, 0x94, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0x98, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0x9C, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x81, 0xA0, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xA4, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xA8, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x81, 0xAC, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xB0, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xB4, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x81, 0xB8, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xBC, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xC0, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x81, 0xC4, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xC8, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xCC, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x81, 0xD0, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xD4, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xD8, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x81, 0xDC, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xE0, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xE4, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x81, 0xE8, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xEC, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xF0, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x81, 0xF4, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xF8, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x81, 0xFC, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x82, 0x00, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x82, 0x04, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x82, 0x10, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x82, 0x14, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x82, 0x18, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x82, 0x1C, \ - 0x00, 0x00, 0x00, 0xE1, 0x40, 0x1F, 0x82, 0x20, 0x00, 0x00, 0x00, 0xE1, \ - 0x40, 0x1F, 0x82, 0x24, 0x00, 0x00, 0x00, 0xE1, 0x40, 0x2F, 0x00, 0x00, \ - 0x10, 0x00, 0x00, 0x04, 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, \ - 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, 0x40, 0x2F, 0x00, 0x10, \ - 0x80, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, \ - 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x04, \ - 0x00, 0x00, 0x79, 0x88, 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07, \ - 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, 0x40, 0x2F, 0x00, 0x48, \ - 0x00, 0x01, 0x09, 0x20, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, \ - 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x84, \ - 0x00, 0x88, 0x88, 0x88, 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, \ - 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x90, \ - 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, \ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, \ - 0xCC, 0x00, 0x14, 0x04, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, \ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, 0xCF, 0x00, 0x0C, 0x1C, \ - 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, \ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, \ - 0xA5, 0x5A, 0x00, 0x0C, 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, \ - 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x1C, 0x04, 0x40, 0x2F, 0x00, 0xA0, \ - 0x00, 0x00, 0x00, 0x30, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, \ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, 0xCF, 0x00, 0x0C, 0x1C, \ - 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x0C, 0x04, \ - 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/flash_image.c b/examples/nxp/rt1020-evk-make-baremetal-builtin/flash_image.c deleted file mode 100644 index 583c0606..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/flash_image.c +++ /dev/null @@ -1,61 +0,0 @@ -#include "dcd.h" // pin settings for MIMXRT1020-EVK board -#include "fsl_flexspi.h" // peripheral structures -#include "fsl_romapi.h" // peripheral structures -#include "hal.h" - -extern uint32_t __isr_vector[]; - -// RM 9.7.2 -__attribute__((section(".dcd"), used)) -const uint8_t __ivt_dcd_data[] = {__DCD_DATA}; - -// RM 9.7.1 -__attribute__((section(".dat"), used)) const uint32_t __ivt_boot_data[] = { - FlexSPI_AMBA_BASE, // boot start location - 8 * 1024 * 1024, // size - 0, // Plugin flag - 0Xffffffff // empty - extra data word -}; - -__attribute__((section(".ivt"), used)) const uint32_t __ivt[8] = { - 0x412000d1, // header: 41 - version, 2000 size, d1 tag - (uint32_t) __isr_vector, // entry - 0, // reserved - (uint32_t) __ivt_dcd_data, // dcd - (uint32_t) __ivt_boot_data, // boot data - (uint32_t) __ivt, // this is us - ivt absolute address - 0, // csf absolute address - 0, // reserved for HAB -}; - -#define __FLEXSPI_QSPI_LUT { \ - [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), \ - [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),\ - [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),\ - [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),\ - [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),\ - [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),\ - [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),\ - [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),\ - [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),\ -} - -// MIMXRT1060-EVKB flash chip config: S25LP064A-JBLE -__attribute__((section(".cfg"), used)) -const flexspi_nor_config_t __qspi_flash_cfg = { - .memConfig = {.tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = 1, // ReadSampleClk_LoopbackFromDqsPad - .csHoldTime = 3, - .csSetupTime = 3, - .controllerMiscOption = BIT(4), - .deviceType = 1, // serial NOR - .sflashPadType = 4, - .serialClkFreq = 7, // 133MHz - .sflashA1Size = 8 * 1024 * 1024, - .lookupTable = __FLEXSPI_QSPI_LUT}, - .pageSize = 256, - .sectorSize = 4 * 1024, - .ipcmdSerialClkFreq = 1, - .blockSize = 64 * 1024, - .isUniformBlockSize = false}; diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/hal.h b/examples/nxp/rt1020-evk-make-baremetal-builtin/hal.h deleted file mode 100644 index 2e3b2204..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/hal.h +++ /dev/null @@ -1,337 +0,0 @@ -// Copyright (c) 2023 Cesanta Software Limited -// All rights reserved -// https://www.nxp.com/webapp/Download?colCode=IMXRT1020RM -// https://cache.nxp.com/secured/assets/documents/en/user-guide/MIMXRT1020EVKHUG.pdf - -#pragma once - -#include "MIMXRT1021.h" - -#include -#include -#include -#include - -#define BIT(x) (1UL << (x)) -#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK) -#define PIN(bank, num) ((((bank) - '0') << 8) | (num)) -#define PINNO(pin) (pin & 255) -#define PINBANK(pin) (pin >> 8) - -// Use LED for blinking, GPIO_AD_B0_05. GPIO1.5 (schematics) -#define LED PIN('1', 5) - -#ifndef UART_DEBUG -#define UART_DEBUG LPUART1 -#endif - -// No settable constants, see sysinit.c -#define SYS_FREQUENCY 500000000UL - -static inline void spin(volatile uint32_t count) { - while (count--) (void) 0; -} - -enum { CLOCK_OFF = 0U, CLOCK_ON_RUN = 1U, CLOCK_ON_RUN_WAIT = 3U }; -static inline void clock_periph(uint32_t index, uint32_t shift, uint32_t val) { - volatile uint32_t *r = &CCM->CCGR0; - SETBITS(r[index], 3UL << shift, val << shift); -} - -// which peripheral feeds the pin -static inline void gpio_mux_config(uint16_t index, uint8_t af) { - IOMUXC->SW_MUX_CTL_PAD[index] = af; -} - -// which pin feeds the peripheral (2nd stage) -static inline void periph_mux_config(uint16_t index, uint8_t in) { - IOMUXC->SELECT_INPUT[index] = in; -} - -enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT }; -enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN }; -enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_MEDIUM_, GPIO_SPEED_HIGH }; -enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP }; -static inline GPIO_Type *gpio_bank(uint16_t pin) { - static const GPIO_Type *g[] = {NULL, GPIO1, GPIO2, GPIO3, NULL, GPIO5}; - return (GPIO_Type *) g[PINBANK(pin)]; -} - -// pin driver/pull-up/down configuration (ignore "keeper") -static inline void gpio_pad_config(uint16_t index, uint8_t type, uint8_t speed, - uint8_t pull) { - bool dopull = pull > 0; - if (dopull) --pull; - IOMUXC->SW_PAD_CTL_PAD[index] = - IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_ODE(type) | - IOMUXC_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH) | - IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PKE(dopull) | - IOMUXC_SW_PAD_CTL_PAD_PUS(pull) | IOMUXC_SW_PAD_CTL_PAD_DSE(7); -} - -static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type, - uint8_t speed, uint8_t pull) { - GPIO_Type *gpio = gpio_bank(pin); - uint8_t bit = (uint8_t) PINNO(pin); - uint32_t mask = (uint32_t) BIT(PINNO(pin)); - - clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s - switch (PINBANK(pin)) { - case 1: - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 + bit, 5); - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 + bit, type, speed, - pull); - clock_periph(1, CCM_CCGR1_CG13_SHIFT, CLOCK_ON_RUN_WAIT); - break; - case 2: - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 + bit, 5); - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 + bit, type, speed, - pull); - clock_periph(0, CCM_CCGR0_CG15_SHIFT, CLOCK_ON_RUN_WAIT); - break; - case 3: - gpio_mux_config(bit < 13 - ? kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 + bit - : kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 + bit - 13, - 5); - gpio_pad_config(bit < 13 - ? kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 + bit - : kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 + bit - 13, - type, speed, pull); - clock_periph(2, CCM_CCGR2_CG13_SHIFT, CLOCK_ON_RUN_WAIT); - break; - case 5: - // TODO(): support sw_mux - clock_periph(1, CCM_CCGR1_CG15_SHIFT, CLOCK_ON_RUN_WAIT); - break; - default: - break; - } - - gpio->IMR &= ~mask; - if (mode == GPIO_MODE_INPUT) { - gpio->GDIR &= ~mask; - } else { - gpio->GDIR |= mask; - } -} -static inline void gpio_input(uint16_t pin) { - gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, - GPIO_PULL_NONE); -} -static inline void gpio_output(uint16_t pin) { - gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, - GPIO_PULL_NONE); -} - -static inline bool gpio_read(uint16_t pin) { - GPIO_Type *gpio = gpio_bank(pin); - uint32_t mask = (uint32_t) BIT(PINNO(pin)); - return gpio->DR & mask; -} -static inline void gpio_write(uint16_t pin, bool value) { - GPIO_Type *gpio = gpio_bank(pin); - uint32_t mask = (uint32_t) BIT(PINNO(pin)); - if (value) { - gpio->DR |= mask; - } else { - gpio->DR &= ~mask; - } -} -static inline void gpio_toggle(uint16_t pin) { - gpio_write(pin, !gpio_read(pin)); -} - -// 14.5 Table 14-4: uart_clk_root -// see sysinit.c for clocks, (14.7.9: defaults to PLL3/6/1 = 80MHz) -static inline void uart_init(LPUART_Type *uart, unsigned long baud) { - uint8_t af = 2; // Alternate function - uint16_t mr = 0, pr = 0, mt = 0, pt = 0; // pins - uint32_t freq = 80000000; // uart_clk_root frequency - if (uart == LPUART1) - mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06, - pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06, - mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07, - pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07; - if (uart == LPUART2) - mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08, - pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08, - mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09, - pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09; - - if (uart == LPUART1) clock_periph(5, CCM_CCGR5_CG12_SHIFT, CLOCK_ON_RUN_WAIT); - if (uart == LPUART2) clock_periph(0, CCM_CCGR0_CG14_SHIFT, CLOCK_ON_RUN_WAIT); - clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s - gpio_mux_config(mt, af); - gpio_pad_config(pt, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); - gpio_mux_config(mr, af); - gpio_pad_config(pr, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); - - uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults - uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; - SETBITS(uart->BAUD, - LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK, - LPUART_BAUD_OSR(16 - 1) | - LPUART_BAUD_SBR(freq / (16 * baud))); // Rx sample at 16x - SETBITS(uart->CTRL, - LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | - LPUART_CTRL_IDLECFG_MASK, - LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) | - LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit - uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK; -} - -static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) { - uart->DATA = byte; - while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1); -} -static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) { - while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++); -} -static inline int uart_read_ready(LPUART_Type *uart) { - (void) uart; - return uart->STAT & LPUART_STAT_RDRF_MASK; -} -static inline uint8_t uart_read_byte(LPUART_Type *uart) { - return (uint8_t) (uart->DATA & 255); -} - -static inline void rng_init(void) { - clock_periph(6, CCM_CCGR6_CG6_SHIFT, CLOCK_ON_RUN_WAIT); // trng_clk - SETBITS(TRNG->MCTL, - TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK | TRNG_MCTL_RST_DEF_MASK, - TRNG_MCTL_PRGM(1) | TRNG_MCTL_ERR(1) | - TRNG_MCTL_RST_DEF(1)); // reset to default values - SETBITS(TRNG->MCTL, TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK, - TRNG_MCTL_PRGM(0)); // set to run mode - (void) TRNG->ENT[TRNG_ENT_COUNT - 1]; // start new entropy generation - (void) TRNG->ENT[0]; // defect workaround -} -static inline uint32_t rng_read(void) { - static uint8_t idx = 0; - while ((TRNG->MCTL & TRNG_MCTL_ENT_VAL_MASK) == 0) (void) 0; - uint32_t data = TRNG->ENT[idx++]; // read data - idx %= TRNG_ENT_COUNT; // stay within array limits - if (idx == 0) // we've just read TRNG_ENT_COUNT - 1 - (void) TRNG->ENT[0]; // defect workaround - return data; -} - -// - PHY has no xtal, XI driven from ENET_REF_CLK1 (labeled as ENET_TX_CLK -// (GPIO_AD_B0_08)), generated by the MCU -// - PHY RST connected to GPIO1.4 (GPIO_AD_B0_04); INTRP/NAND_TREE connected to -// GPIO1.22 (GPIO_AD_B1_06) -// - 37.4 REF_CLK1 is RMII mode reference clock for Rx, Tx, and SMI; it is I/O -// - 11.4.2 IOMUXC_GPR_GPR1 bit 17: ENET_REF_CLK_DIR --> 1 ENET_REF_CLK is -// output driven by ref_enetpll0 -// - 14.6.1.3.4 Ethernet PLL (PLL6) -static inline void ethernet_init(void) { - gpio_init(PIN('1', 4), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_MEDIUM, GPIO_PULL_UP); // set GPIO1.4 as GPIO (PHY \RST) - gpio_write(PIN('1', 4), 0); // reset PHY - - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08, - 4); // set for ENET_REF_CLK1 - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08] |= - IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_ENET_RMII_SELECT_INPUT, - 1); // drive peripheral from B0_08, so RMII clock is taken - // from ENET_REF_CLK1 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09, 0); // set for RXDATA1 - periph_mux_config(kIOMUXC_ENET_RX_DATA1_SELECT_INPUT, - 1); // drive peripheral from B0_09 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10, 0); // set for RXDATA0 - periph_mux_config(kIOMUXC_ENET_RX_DATA0_SELECT_INPUT, - 1); // drive peripheral from B0_10 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11, 0); // set for CRS - periph_mux_config(kIOMUXC_ENET_RX_EN_SELECT_INPUT, - 1); // drive peripheral from B0_11 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12, 0); // set for RXERR - periph_mux_config(kIOMUXC_ENET_RX_ERR_SELECT_INPUT, - 1); // drive peripheral from B0_12 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13, 0); // set for TXEN - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14, 0); // set for TXDATA0 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15, 0); // set for TXDATA1 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, 4); // set for MDIO - periph_mux_config(kIOMUXC_ENET_MDIO_SELECT_INPUT, - 2); // drive peripheral from EMC_40 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_MEDIUM, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, 4); // set for MDC - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_MEDIUM, GPIO_PULL_UP); - - gpio_init(PIN('1', 22), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_MEDIUM, - GPIO_PULL_UP); // set GPIO1.22 as GPIO (PHY INTRP/NAND_TREE) - gpio_write(PIN('1', 22), 1); // prevent NAND_TREE - // 14.8.9 Use 500MHz reference and generate 50MHz. This is done at sysinit.c, - // as we use this source to clock the core - spin(10000); // keep PHY RST low for a while - gpio_write(PIN('1', 4), 1); // deassert RST - gpio_init(PIN('1', 22), GPIO_MODE_INPUT, 0, GPIO_SPEED_MEDIUM, - GPIO_PULL_UP); // setup IRQ (pulled-up)(not used) - - IOMUXC_GPR->GPR1 |= - IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR(1); // Set ENET_REF_CLK1 as output - clock_periph(1, CCM_CCGR1_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enet_ipg_clk - NVIC_EnableIRQ(ENET_IRQn); // Setup Ethernet IRQ handler -} - -// Helper macro for MAC generation, byte reads not allowed -#define GENERATE_LOCALLY_ADMINISTERED_MAC() \ - { \ - 2, OCOTP->CFG0 & 255, (OCOTP->CFG0 >> 10) & 255, \ - ((OCOTP->CFG0 >> 19) ^ (OCOTP->CFG1 >> 19)) & 255, \ - (OCOTP->CFG1 >> 10) & 255, OCOTP->CFG1 & 255 \ - } - -static inline void flash_init(void) { // QSPI in FlexSPI - // set pins - clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05, 1); // set for DQS - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11, 1); // set for SS - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07, 1); // set for SCLK - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_FLEXSPI_A_SCLK_SELECT_INPUT, 0); // drive peripheral from B1_07 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08, 1); // set for DATA0 - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT, 0); // drive peripheral from B1_08 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10, 1); // set for DATA1 - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT, 0); // drive peripheral from B1_10 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09, 1); // set for DATA2 - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT, 0); // drive peripheral from B1_09 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06, 1); // set for DATA3 - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT, 0); // drive peripheral from B1_06 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - // set FlexSPI clock - SETBITS(CCM->CSCMR1, CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK | CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_CSCMR1_FLEXSPI_CLK_SEL(3) | CCM_CSCMR1_FLEXSPI_PODF(3)); // select PLL3 PFD0 /4 - clock_periph(6, CCM_CCGR6_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enable -} diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/link.ld b/examples/nxp/rt1020-evk-make-baremetal-builtin/link.ld deleted file mode 100644 index 316c2c85..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/link.ld +++ /dev/null @@ -1,24 +0,0 @@ -ENTRY(Reset_Handler); -MEMORY { - flash_hdr(rx) : ORIGIN = 0x60000000, LENGTH = 8k - flash_irq(rx) : ORIGIN = 0x60002000, LENGTH = 1k - flash_code(rx) : ORIGIN = 0x60002400, LENGTH = 8183k - - itcram(rx) : ORIGIN = 0x00000000, LENGTH = 64k - dtcram(rw) : ORIGIN = 0x20000000, LENGTH = 64k - ocram(rw) : ORIGIN = 0x20200000, LENGTH = 128k -} -__StackTop = ORIGIN(dtcram) + LENGTH(dtcram); - -/* TODO(): separate itcram and go back to using dtcram for data and bss when ota is finished */ - -SECTIONS { - .hdr : { FILL(0xff) ; KEEP(*(.cfg)) . = 0x1000 ; KEEP(*(.ivt)) . = 0x1020 ; - KEEP(*(.dat)) . = 0x1030 ; KEEP(*(.dcd)) . = 0x2000 ;} >flash_hdr - .irq : { KEEP(*(.isr_vector)) } > flash_irq - .text : { *(.text* .text.*) *(.rodata*) ; } > flash_code - .data : { __data_start__ = .; *(.data SORT(.data.*)) *(.iram) __data_end__ = .; } > itcram AT > flash_code - __etext = LOADADDR(.data); - .bss : { __bss_start__ = .; *(.bss SORT(.bss.*) COMMON) __bss_end__ = .; } > itcram - _end = .; -} diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/main.c b/examples/nxp/rt1020-evk-make-baremetal-builtin/main.c deleted file mode 100644 index 1fca6513..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/main.c +++ /dev/null @@ -1,71 +0,0 @@ -// Copyright (c) 2022-2023 Cesanta Software Limited -// All rights reserved - -#include "hal.h" -#include "mongoose.h" -#include "net.h" - -#define BLINK_PERIOD_MS 1000 // LED blinking period in millis - -static volatile uint64_t s_ticks; // Milliseconds since boot -void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms - s_ticks++; -} - -uint64_t mg_millis(void) { // Let Mongoose use our uptime function - return s_ticks; // Return number of milliseconds since boot -} - -bool mg_random(void *buf, size_t len) { // Use on-board RNG - for (size_t n = 0; n < len; n += sizeof(uint32_t)) { - uint32_t r = rng_read(); - memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r)); - } - return true; -} -static void timer_fn(void *arg) { - gpio_toggle(LED); // Blink LED - struct mg_tcpip_if *ifp = arg; // And show - const char *names[] = {"down", "up", "req", "ready"}; // network stats - MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u", - names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent, - ifp->ndrop, ifp->nerr)); -} - -int main(void) { - gpio_output(LED); // Setup blue LED - uart_init(UART_DEBUG, 115200); // Initialise debug printf - ethernet_init(); // Initialise ethernet pins - MG_INFO(("Starting, CPU freq %g MHz", (double) SystemCoreClock / 1000000)); - - struct mg_mgr mgr; // Initialise - mg_mgr_init(&mgr); // Mongoose event manager - mg_log_set(MG_LL_DEBUG); // Set log level - - // Initialise Mongoose network stack - struct mg_tcpip_driver_imxrt_data driver_data = {.mdc_cr = 24, .phy_addr = 2}; - struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(), - // Uncomment below for static configuration: - // .ip = mg_htonl(MG_U32(192, 168, 0, 223)), - // .mask = mg_htonl(MG_U32(255, 255, 255, 0)), - // .gw = mg_htonl(MG_U32(192, 168, 0, 1)), - .driver = &mg_tcpip_driver_imxrt, - .driver_data = &driver_data}; - mg_tcpip_init(&mgr, &mif); - mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif); - - MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac)); - while (mif.state != MG_TCPIP_STATE_READY) { - mg_mgr_poll(&mgr, 0); - } - - MG_INFO(("Initialising application...")); - web_init(&mgr); - - MG_INFO(("Starting event loop")); - for (;;) { - mg_mgr_poll(&mgr, 0); - } - - return 0; -} diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/mongoose.c b/examples/nxp/rt1020-evk-make-baremetal-builtin/mongoose.c deleted file mode 120000 index 5e522bbc..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/mongoose.c +++ /dev/null @@ -1 +0,0 @@ -../../../mongoose.c \ No newline at end of file diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/mongoose.h b/examples/nxp/rt1020-evk-make-baremetal-builtin/mongoose.h deleted file mode 120000 index ee4ac823..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/mongoose.h +++ /dev/null @@ -1 +0,0 @@ -../../../mongoose.h \ No newline at end of file diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/mongoose_config.h b/examples/nxp/rt1020-evk-make-baremetal-builtin/mongoose_config.h deleted file mode 100644 index 9918b8f6..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/mongoose_config.h +++ /dev/null @@ -1,14 +0,0 @@ -#pragma once - -// See https://mongoose.ws/documentation/#build-options -#define MG_ARCH MG_ARCH_NEWLIB -#define MG_OTA MG_OTA_FLASH -#define MG_DEVICE MG_DEVICE_RT1020 - -#define MG_ENABLE_TCPIP 1 -#define MG_ENABLE_DRIVER_IMXRT 1 -#define MG_IO_SIZE 256 -#define MG_ENABLE_CUSTOM_MILLIS 1 -#define MG_ENABLE_CUSTOM_RANDOM 1 -#define MG_ENABLE_PACKED_FS 1 - diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/net.c b/examples/nxp/rt1020-evk-make-baremetal-builtin/net.c deleted file mode 120000 index fe0e6f06..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/net.c +++ /dev/null @@ -1 +0,0 @@ -../../device-dashboard/net.c \ No newline at end of file diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/net.h b/examples/nxp/rt1020-evk-make-baremetal-builtin/net.h deleted file mode 120000 index 9de896ef..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/net.h +++ /dev/null @@ -1 +0,0 @@ -../../device-dashboard/net.h \ No newline at end of file diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/packed_fs.c b/examples/nxp/rt1020-evk-make-baremetal-builtin/packed_fs.c deleted file mode 120000 index e06bf092..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/packed_fs.c +++ /dev/null @@ -1 +0,0 @@ -../../device-dashboard/packed_fs.c \ No newline at end of file diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/syscalls.c b/examples/nxp/rt1020-evk-make-baremetal-builtin/syscalls.c deleted file mode 100644 index 6fef1007..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/syscalls.c +++ /dev/null @@ -1,98 +0,0 @@ -#include - -#include "hal.h" - -int _fstat(int fd, struct stat *st) { - if (fd < 0) return -1; - st->st_mode = S_IFCHR; - return 0; -} - -void *_sbrk(int incr) { - extern char _end; - static unsigned char *heap = NULL; - unsigned char *prev_heap; - unsigned char x = 0, *heap_end = (unsigned char *)((size_t) &x - 512); - (void) x; - if (heap == NULL) heap = (unsigned char *) &_end; - prev_heap = heap; - if (heap + incr > heap_end) return (void *) -1; - heap += incr; - return prev_heap; -} - -int _open(const char *path) { - (void) path; - return -1; -} - -int _close(int fd) { - (void) fd; - return -1; -} - -int _isatty(int fd) { - (void) fd; - return 1; -} - -int _lseek(int fd, int ptr, int dir) { - (void) fd, (void) ptr, (void) dir; - return 0; -} - -void _exit(int status) { - (void) status; - for (;;) asm volatile("BKPT #0"); -} - -void _kill(int pid, int sig) { - (void) pid, (void) sig; -} - -int _getpid(void) { - return -1; -} - -int _write(int fd, char *ptr, int len) { - (void) fd, (void) ptr, (void) len; - if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len); - return -1; -} - -int _read(int fd, char *ptr, int len) { - (void) fd, (void) ptr, (void) len; - return -1; -} - -int _link(const char *a, const char *b) { - (void) a, (void) b; - return -1; -} - -int _unlink(const char *a) { - (void) a; - return -1; -} - -int _stat(const char *path, struct stat *st) { - (void) path, (void) st; - return -1; -} - -int mkdir(const char *path, mode_t mode) { - (void) path, (void) mode; - return -1; -} - -void _init(void) {} - -extern uint64_t mg_now(void); - -int _gettimeofday(struct timeval *tv, void *tz) { - uint64_t now = mg_now(); - (void) tz; - tv->tv_sec = (time_t) (now / 1000); - tv->tv_usec = (unsigned long) ((now % 1000) * 1000); - return 0; -} diff --git a/examples/nxp/rt1020-evk-make-baremetal-builtin/sysinit.c b/examples/nxp/rt1020-evk-make-baremetal-builtin/sysinit.c deleted file mode 100644 index 797445a6..00000000 --- a/examples/nxp/rt1020-evk-make-baremetal-builtin/sysinit.c +++ /dev/null @@ -1,82 +0,0 @@ -// Copyright (c) 2023 Cesanta Software Limited -// All rights reserved -// -// This file contains essentials required by the CMSIS: -// uint32_t SystemCoreClock - holds the system core clock value -// SystemInit() - initialises the system, e.g. sets up clocks - -#include "hal.h" - -uint32_t SystemCoreClock = SYS_FREQUENCY; - -// - 14.4, Figure 14-2: clock tree -// - 14.7.4: ARM_PODF defaults to /1 -// - 14.7.5: AHB_PODF defaults to /1; PERIPH_CLK_SEL defaults to derive clock -// from pre_periph_clk_sel -// - 14.7.6: PRE_PERIPH_CLK_SEL defaults to derive clock from PLL2 PFD3. -// - (For 528MHz operation, we need to set it to derive clock from PLL2, but -// this chip max is 500 MHz). -// - 14.6.1.3.1 System PLL (PLL2); 13.3.2.2 PLLs; 14.6.1.4 Phase Fractional -// Dividers (PFD) -// - 14.8.2: PLL2 is powered off and bypassed to 24MHz -// - 14.8.11: PFD defaults to 18/16 but Figure 14-2 shows half the value -// ("divider") -// - For 500MHz operation, we need to set PRE_PERIPH_CLK_SEL to derive clock -// from divided PLL6 -// - 14.8.9: configure PLL6 to generate a 500MHz clock -// - Datasheet 4.1.3: System frequency/Bus frequency max 500/125MHz respectively -// (AHB/IPG) -// - MCUXpresso: IPG_CLK_ROOT <= 125MHz; PERCLK_CLK_ROOT <= 62.5MHz -// - Datasheet 4.8.4.1.1/2: the processor clock frequency must exceed twice the -// ENET_RX_CLK/ENET_TX_CLK frequency. -// - Datasheet 4.8.4.2: no details for RMII (above is for MII), assumed 50MHz -// min processor clock -// - Datasheet 4.1.3, Table 11: "Overdrive" run mode requires 1.25V core voltage -// minimum -void SystemInit(void) { // Called automatically by startup code (ints masked) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU - asm("DSB"); - asm("ISB"); - // 53.4.2: Disable watchdog after reset (unlocked) - RTWDOG->CS &= ~RTWDOG_CS_EN_MASK; - RTWDOG->TOVAL = 0xFFFF; - while (RTWDOG->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock - while ((RTWDOG->CS & RTWDOG_CS_RCS_MASK) == 0) - spin(1); // wait for new config - // Set VDD_SOC to 1.25V - SETBITS(DCDC->REG3, DCDC_REG3_TRG_MASK, DCDC_REG3_TRG(0x12)); - while ((DCDC->REG0 & DCDC_REG0_STS_DC_OK_MASK) == 0) - spin(1); // Wait for DCDC_STS_DC_OK - // 14.8.9 Init 500MHz reference, clock the M7 core with it, generate 50MHz for - // ENET and RMII. - SETBITS(CCM_ANALOG->PLL_ENET, CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK, - CCM_ANALOG_PLL_ENET_BYPASS_MASK | - CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(0)); // bypass to 24MHz osc - SETBITS( - CCM_ANALOG->PLL_ENET, - CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK, - CCM_ANALOG_PLL_ENET_DIV_SELECT(1) | CCM_ANALOG_PLL_ENET_ENABLE_MASK | - CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK); // setup PLL - while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) - spin(1); // wait until it is stable - CCM_ANALOG->PLL_ENET &= - ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; // Disable Bypass (switch to PLL) - SETBITS(CCM->CBCDR, CCM_CBCDR_IPG_PODF_MASK, - CCM_CBCDR_IPG_PODF(3)); // Set IPG divider /4 (125MHz) - SETBITS(CCM->CSCMR1, CCM_CSCMR1_PERCLK_PODF_MASK, - CCM_CSCMR1_PERCLK_PODF(1)); // Set PERCLK divider /2 (62.5MHz) - SETBITS(CCM->CBCMR, CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, - CCM_CBCMR_PRE_PERIPH_CLK_SEL(3)); // run from 500MHz clock - // 14.5 Table 14-4: uart_clk_root - // 14.4: uart_clk_root = PLL3/6 or OSC; CCM_CSCDR1 (14.7.9) defaults to - // PLL3/6/1; but ROM boot code fiddles with the divider (9.5.3 Table 9-7) - CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_POWER_MASK; // Power PLL on - while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) - spin(1); // wait until it is stable - CCM_ANALOG->PLL_USB1 &= - ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; // Disable Bypass (switch to PLL) - CCM->CSCDR1 &= ~(CCM_CSCDR1_UART_CLK_SEL_MASK | CCM_CSCDR1_UART_CLK_PODF_MASK); - rng_init(); // Initialise random number generator - // NXP startup code calls SystemInit BEFORE initializing RAM... - SysTick_Config(SYS_FREQUENCY / 1000); // Sys tick every 1ms -} diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/Makefile b/examples/nxp/rt1060-evk-make-baremetal-builtin/Makefile index 324c921d..d13c2e9c 100644 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/Makefile +++ b/examples/nxp/rt1060-evk-make-baremetal-builtin/Makefile @@ -1,85 +1,29 @@ -CFLAGS = -W -Wall -Wextra -Werror -Wundef -Wshadow -Wdouble-promotion -CFLAGS += -Wformat-truncation -fno-common # -Wconversion is not SDK-friendly -CFLAGS += -g3 -Os -ffunction-sections -fdata-sections -CFLAGS += -I. -Icmsis_core/CMSIS/Core/Include -Icmsis_mcu/devices/MIMXRT1062 -CFLAGS += -Icmsis_mcu/devices/MIMXRT1062/drivers -DCPU_MIMXRT1062DVL6B -CFLAGS += -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 $(CFLAGS_EXTRA) -LDSCRIPT = link.ld -LDFLAGS ?= -T$(LDSCRIPT) -nostdlib -nostartfiles --specs nano.specs -lc -lgcc -Wl,--gc-sections -Wl,-Map=$@.map +BOARD = rt1060 +IDE = GCC+make +RTOS = baremetal +WIZARD_URL ?= http://mongoose.ws/wizard -SOURCES = main.c syscalls.c sysinit.c -SOURCES += cmsis_mcu/devices/MIMXRT1062/gcc/startup_MIMXRT1062.S # NXP startup file. Compiler-dependent! -CFLAGS += -D__ATOLLIC__ -D__STARTUP_CLEAR_BSS # Make startup code work as expected - -# Mongoose options are defined in mongoose_config.h -SOURCES += mongoose.c net.c packed_fs.c - -# Example specific build options. See README.md -CFLAGS += -DHTTP_URL=\"http://0.0.0.0/\" -DHTTPS_URL=\"https://0.0.0.0/\" - -ifeq ($(OS),Windows_NT) - RM = cmd /C del /Q /F /S -else - RM = rm -rf -endif - -all build example update: SOURCES += flash_image.c all build example: firmware.bin -ram: LDSCRIPT = link_ram.ld -ram: firmware.bin +firmware.bin: wizard + make -C wizard CFLAGS_EXTRA=$(CFLAGS_EXTRA) && mv wizard/firmware.bin ./ -firmware.bin: firmware.elf - arm-none-eabi-objcopy -O binary $< $@ +wizard: + hash=$$(curl -s -X POST -H "Content-Type: application/json" -d '{"build":{"board":"$(BOARD)","ide":"$(IDE)","rtos":"$(RTOS)"}}' $(WIZARD_URL)/api/hash | jq -r '.hash') \ + && curl -s $(WIZARD_URL)/api/zip/$(BOARD)/$(IDE)/$(RTOS)/$$hash -o wizard.zip + unzip wizard.zip + cd wizard ; rm mongoose.[ch] ; ln -s ../../../../mongoose.c ; ln -s ../../../../mongoose.h -firmware.elf: cmsis_core cmsis_mcu $(SOURCES) hal.h link_ram.ld link.ld Makefile - arm-none-eabi-gcc $(SOURCES) $(CFLAGS) $(LDFLAGS) -o $@ - arm-none-eabi-size $@ - -flash: firmware.bin -# flash - -cmsis_core: # ARM CMSIS core headers - git clone -q --depth 1 -b 5.9.0 https://github.com/ARM-software/CMSIS_5 $@ -cmsis_mcu: - curl -sL https://mcuxpresso.nxp.com/cmsis_pack/repo/NXP.MIMXRT1062_DFP.17.1.0.pack -o $@.zip - mkdir $@ && cd $@ && unzip -q ../$@.zip -mbedtls: # mbedTLS library - git clone --depth 1 -b v2.28.2 https://github.com/mbed-tls/mbedtls $@ - -ifeq ($(TLS), mbedtls) -CFLAGS += -DMG_TLS=MG_TLS_MBED -Wno-conversion -Imbedtls/include -CFLAGS += -DMBEDTLS_CONFIG_FILE=\"mbedtls_config.h\" mbedtls/library/*.c -firmware.elf: mbedtls -endif # Automated remote test. Requires env variable VCON_API_KEY set. See https://vcon.io/automated-firmware-tests/ DEVICE_URL ?= https://dash.vcon.io/api/v3/devices/13 update: firmware.bin curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @$< -update updateram: CFLAGS += -DUART_DEBUG=LPUART3 - +test update: CFLAGS_EXTRA ="-DUART_DEBUG=LPUART3" test: update - curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt + curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=15 | tee /tmp/output.txt grep 'READY, IP:' /tmp/output.txt # Check for network init - -updateram: ram - curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/ota --data-binary @firmware.bin - curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}' - curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0003 wm,e000edfc,1 wm,e000ed0c,5fa0004"}' - curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"init"}' - PC=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,4"}' | jq -r .resp[5:]` && \ - SP=`curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"rm,0"}' | jq -r .resp[5:]` && \ - REQ="wm,e000ed08,0 wr,d,$$SP wr,f,$$PC" && \ - curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"'"$$REQ"'"}' - curl -su :$(VCON_API_KEY) $(DEVICE_URL)/rpc/swd.exec -d '{"req":"wm,e000edf0,a05f0001"}' - -testram: updateram - curl --fail-with-body -su :$(VCON_API_KEY) $(DEVICE_URL)/tx?t=5 | tee /tmp/output.txt - grep 'READY, IP:' /tmp/output.txt # Check for network init - - clean: - $(RM) firmware.* *.su cmsis_core cmsis_mcu mbedtls *.zip + rm -rf firmware.* wizard* diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/README.md b/examples/nxp/rt1060-evk-make-baremetal-builtin/README.md new file mode 100644 index 00000000..c6935b61 --- /dev/null +++ b/examples/nxp/rt1060-evk-make-baremetal-builtin/README.md @@ -0,0 +1 @@ +See [Wizard](https://mongoose.ws/wizard/#/output?board=rt1060&ide=GCC+make&rtos=baremetal&file=README.md) diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/dcd.h b/examples/nxp/rt1060-evk-make-baremetal-builtin/dcd.h deleted file mode 100644 index 99597a11..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/dcd.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2020-2021 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define __DCD_DATA \ - 0xD2, 0x04, 0x10, 0x41, 0xCC, 0x03, 0x8C, 0x04, 0x40, 0x0F, 0xC0, 0x68, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, \ - 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x74, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, \ - 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0F, 0xC0, 0x80, \ - 0xFF, 0xFF, 0xFF, 0xFF, 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, \ - 0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, 0x40, 0x0F, 0xC0, 0x14, \ - 0x00, 0x01, 0x0D, 0x40, 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x1C, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x28, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x34, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x40, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x4C, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x58, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x64, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x70, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x7C, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x88, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x94, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA0, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, \ - 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xAC, \ - 0x00, 0x00, 0x00, 0x00, 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, \ - 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x08, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x14, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x20, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x2C, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x38, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x44, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x50, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x5C, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x68, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x74, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x80, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x8C, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x98, \ - 0x00, 0x01, 0x10, 0xF9, 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, \ - 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, 0x40, 0x2F, 0x00, 0x00, \ - 0x10, 0x00, 0x00, 0x04, 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, \ - 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, 0x40, 0x2F, 0x00, 0x10, \ - 0x80, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, \ - 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x1C, \ - 0x86, 0x00, 0x00, 0x1B, 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, \ - 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, 0x40, 0x2F, 0x00, 0x28, \ - 0xA8, 0x00, 0x00, 0x17, 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, \ - 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x04, \ - 0x00, 0x00, 0x79, 0xA8, 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, \ - 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, 0x40, 0x2F, 0x00, 0x48, \ - 0x00, 0x01, 0x09, 0x20, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, \ - 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, 0x40, 0x2F, 0x00, 0x84, \ - 0x00, 0x88, 0x88, 0x88, 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, \ - 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x90, \ - 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, \ - 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, \ - 0xCC, 0x00, 0x14, 0x04, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, \ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, 0xCF, 0x00, 0x0C, 0x1C, \ - 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x14, 0x04, \ - 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, 0x40, 0x2F, 0x00, 0x9C, \ - 0xA5, 0x5A, 0x00, 0x0C, 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, \ - 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x1C, 0x04, 0x40, 0x2F, 0x00, 0xA0, \ - 0x00, 0x00, 0x00, 0x33, 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, \ - 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, 0xCF, 0x00, 0x0C, 0x1C, \ - 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, 0xCC, 0x00, 0x0C, 0x04, \ - 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09 diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/flash_image.c b/examples/nxp/rt1060-evk-make-baremetal-builtin/flash_image.c deleted file mode 100644 index 009a16c4..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/flash_image.c +++ /dev/null @@ -1,61 +0,0 @@ -#include "dcd.h" // pin settings for MIMXRT1060-EVKB board -#include "fsl_flexspi.h" // peripheral structures -#include "fsl_romapi.h" // peripheral structures -#include "hal.h" - -extern uint32_t __isr_vector[]; - -// RM 9.7.2 -__attribute__((section(".dcd"), used)) -const uint8_t __ivt_dcd_data[] = {__DCD_DATA}; - -// RM 9.7.1 -__attribute__((section(".dat"), used)) const uint32_t __ivt_boot_data[] = { - FlexSPI_AMBA_BASE, // boot start location - 8 * 1024 * 1024, // size - 0, // Plugin flag - 0Xffffffff // empty - extra data word -}; - -__attribute__((section(".ivt"), used)) const uint32_t __ivt[8] = { - 0x412000d1, // header: 41 - version, 2000 size, d1 tag - (uint32_t) __isr_vector, // entry - 0, // reserved - (uint32_t) __ivt_dcd_data, // dcd - (uint32_t) __ivt_boot_data, // boot data - (uint32_t) __ivt, // this is us - ivt absolute address - 0, // csf absolute address - 0, // reserved for HAB -}; - -#define __FLEXSPI_QSPI_LUT { \ - [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), \ - [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),\ - [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),\ - [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),\ - [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18),\ - [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),\ - [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),\ - [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),\ - [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),\ -} - -// MIMXRT1060-EVKB flash chip config: IS25WP064AJBLE -__attribute__((section(".cfg"), used)) -const flexspi_nor_config_t __qspi_flash_cfg = { - .memConfig = {.tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = 1, // ReadSampleClk_LoopbackFromDqsPad - .csHoldTime = 3, - .csSetupTime = 3, - .controllerMiscOption = BIT(4), - .deviceType = 1, // serial NOR - .sflashPadType = 4, - .serialClkFreq = 7, // 120MHz - .sflashA1Size = 8 * 1024 * 1024, - .lookupTable = __FLEXSPI_QSPI_LUT}, - .pageSize = 256, - .sectorSize = 4 * 1024, - .ipcmdSerialClkFreq = 1, - .blockSize = 64 * 1024, - .isUniformBlockSize = false}; diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/hal.h b/examples/nxp/rt1060-evk-make-baremetal-builtin/hal.h deleted file mode 100644 index 5b549ae8..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/hal.h +++ /dev/null @@ -1,356 +0,0 @@ -// Copyright (c) 2023 Cesanta Software Limited -// All rights reserved -// https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMXRT1060XRM.pdf -// https://cache.nxp.com/secured/assets/documents/en/user-guide/MIMXRT1060EVKBUM.pdf - -#pragma once - -#include "MIMXRT1062.h" - -#include -#include -#include -#include - -#define BIT(x) (1UL << (x)) -#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK) -#define PIN(bank, num) ((((bank) - '0') << 8) | (num)) -#define PINNO(pin) (pin & 255) -#define PINBANK(pin) (pin >> 8) - -// Use LED for blinking, D8: GPIO_AD_B0_08. GPIO1.8 (schematics, RM) -#define LED PIN('1', 8) - -#ifndef UART_DEBUG -#define UART_DEBUG LPUART1 -#endif - -// No settable constants, see sysinit.c -#define SYS_FREQUENCY 600000000UL - -static inline void spin(volatile uint32_t count) { - while (count--) (void) 0; -} - -enum { CLOCK_OFF = 0U, CLOCK_ON_RUN = 1U, CLOCK_ON_RUN_WAIT = 3U }; -static inline void clock_periph(uint32_t index, uint32_t shift, uint32_t val) { - volatile uint32_t *r = &CCM->CCGR0; - SETBITS(r[index], 3UL << shift, val << shift); -} - -// which peripheral feeds the pin -static inline void gpio_mux_config(uint16_t index, uint8_t af) { - IOMUXC->SW_MUX_CTL_PAD[index] = af; -} - -// which pin feeds the peripheral (2nd stage) -static inline void periph_mux_config(uint16_t index, uint8_t in) { - IOMUXC->SELECT_INPUT[index] = in; -} - -enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT }; -enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN }; -enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_MEDIUM_, GPIO_SPEED_HIGH }; -enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP }; -static inline GPIO_Type *gpio_bank(uint16_t pin) { - static const GPIO_Type *g[] = {NULL, GPIO1, GPIO2, GPIO3, NULL, GPIO5}; - return (GPIO_Type *) g[PINBANK(pin)]; -} - -// pin driver/pull-up/down configuration (ignore "keeper") -static inline void gpio_pad_config(uint16_t index, uint8_t type, uint8_t speed, - uint8_t pull) { - bool dopull = pull > 0; - if (dopull) --pull; - IOMUXC->SW_PAD_CTL_PAD[index] = - IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_ODE(type) | - IOMUXC_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH) | - IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PKE(dopull) | - IOMUXC_SW_PAD_CTL_PAD_PUS(pull) | IOMUXC_SW_PAD_CTL_PAD_DSE(7); -} - -static inline void gpio_init(uint16_t pin, uint8_t mode, uint8_t type, - uint8_t speed, uint8_t pull) { - GPIO_Type *gpio = gpio_bank(pin); - uint8_t bit = (uint8_t) PINNO(pin); - uint32_t mask = (uint32_t) BIT(PINNO(pin)); - - clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s - switch (PINBANK(pin)) { - case 1: - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 + bit, 5); - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 + bit, type, speed, - pull); - clock_periph(1, CCM_CCGR1_CG13_SHIFT, CLOCK_ON_RUN_WAIT); - break; - case 2: - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 + bit, 5); - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 + bit, type, speed, - pull); - clock_periph(0, CCM_CCGR0_CG15_SHIFT, CLOCK_ON_RUN_WAIT); - break; - case 3: - gpio_mux_config(bit < 12 ? kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 + bit - : bit < 18 - ? kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 + bit - 12 - : kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 + bit - 18, - 5); - gpio_pad_config(bit < 12 ? kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 + bit - : bit < 18 - ? kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 + bit - 12 - : kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 + bit - 18, - type, speed, pull); - clock_periph(2, CCM_CCGR2_CG13_SHIFT, CLOCK_ON_RUN_WAIT); - break; - case 5: - // TODO(): support sw_mux - clock_periph(1, CCM_CCGR1_CG15_SHIFT, CLOCK_ON_RUN_WAIT); - break; - default: - break; - } - - gpio->IMR &= ~mask; - if (mode == GPIO_MODE_INPUT) { - gpio->GDIR &= ~mask; - } else { - gpio->GDIR |= mask; - } -} -static inline void gpio_input(uint16_t pin) { - gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, - GPIO_PULL_NONE); -} -static inline void gpio_output(uint16_t pin) { - gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, - GPIO_PULL_NONE); -} - -static inline bool gpio_read(uint16_t pin) { - GPIO_Type *gpio = gpio_bank(pin); - uint32_t mask = (uint32_t) BIT(PINNO(pin)); - return gpio->DR & mask; -} -static inline void gpio_write(uint16_t pin, bool value) { - GPIO_Type *gpio = gpio_bank(pin); - uint32_t mask = (uint32_t) BIT(PINNO(pin)); - if (value) { - gpio->DR |= mask; - } else { - gpio->DR &= ~mask; - } -} -static inline void gpio_toggle(uint16_t pin) { - gpio_write(pin, !gpio_read(pin)); -} - -// 14.5 Table 14-4: uart_clk_root -// see sysinit.c for clocks, (14.7.9: defaults to pll3_80m = PLL3/6/1 = 80MHz) -static inline void uart_init(LPUART_Type *uart, unsigned long baud) { - uint8_t af = 2; // Alternate function - uint16_t mr = 0, pr = 0, mt = 0, pt = 0; // pins - uint32_t freq = 80000000; // uart_clk_root frequency - if (uart == LPUART1) - mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12, - pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12, - mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13, - pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13; - if (uart == LPUART3) - mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06, - pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06, - mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07, - pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07; - - if (uart == LPUART1) clock_periph(5, CCM_CCGR5_CG12_SHIFT, CLOCK_ON_RUN_WAIT); - if (uart == LPUART3) clock_periph(0, CCM_CCGR0_CG6_SHIFT, CLOCK_ON_RUN_WAIT); - clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s - gpio_mux_config(mt, af); - gpio_pad_config(pt, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); - gpio_mux_config(mr, af); - gpio_pad_config(pr, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); - - uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults - uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; - SETBITS(uart->BAUD, - LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK, - LPUART_BAUD_OSR(16 - 1) | - LPUART_BAUD_SBR(freq / (16 * baud))); // Rx sample at 16x - SETBITS(uart->CTRL, - LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | - LPUART_CTRL_IDLECFG_MASK, - LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) | - LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit - uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK; -} - -static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) { - uart->DATA = byte; - while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1); -} -static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) { - while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++); -} -static inline int uart_read_ready(LPUART_Type *uart) { - (void) uart; - return uart->STAT & LPUART_STAT_RDRF_MASK; -} -static inline uint8_t uart_read_byte(LPUART_Type *uart) { - return (uint8_t) (uart->DATA & 255); -} - -static inline void rng_init(void) { - clock_periph(6, CCM_CCGR6_CG6_SHIFT, CLOCK_ON_RUN_WAIT); // trng_clk - SETBITS(TRNG->MCTL, - TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK | TRNG_MCTL_RST_DEF_MASK, - TRNG_MCTL_PRGM(1) | TRNG_MCTL_ERR(1) | - TRNG_MCTL_RST_DEF(1)); // reset to default values - SETBITS(TRNG->MCTL, TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK, - TRNG_MCTL_PRGM(0)); // set to run mode - (void) TRNG->ENT[TRNG_ENT_COUNT - 1]; // start new entropy generation - (void) TRNG->ENT[0]; // defect workaround -} -static inline uint32_t rng_read(void) { - static uint8_t idx = 0; - while ((TRNG->MCTL & TRNG_MCTL_ENT_VAL_MASK) == 0) (void) 0; - uint32_t data = TRNG->ENT[idx++]; // read data - idx %= TRNG_ENT_COUNT; // stay within array limits - if (idx == 0) // we've just read TRNG_ENT_COUNT - 1 - (void) TRNG->ENT[0]; // defect workaround - return data; -} - -// - PHY has no xtal, XI driven from ENET_REF_CLK1 (labeled as ENET_TX_REF_CLK -// (GPIO_AD_B1_10)), generated by the MCU -// - PHY RST connected to GPIO1.9 (GPIO_AD_B0_09); INTRP/NAND_TREE connected to -// GPIO1.10 (GPIO_AD_B0_10) -// - 41.4 REF_CLK1 is RMII mode reference clock for Rx, Tx, and SMI; it is I/O -// - 11.3.2 IOMUXC_GPR_GPR1 -// - bit 13: ENET1_CLK_SEL --> 0 ENET1 TX reference clock driven by -// ref_enetpll and output via ENET_REF_CLK1 (labeled as ENET_REF_CLK -// elsewhere) -// - bit 17: ENET1_TX_CLK_DIR --> 1 ENET1_TX_CLK output driver enabled -// - 14.6.1.3.6 Ethernet PLL (PLL6) -// - 14.8.14: configure PLL6 to generate 50MHz clocks for ENET and RMII. -static inline void ethernet_init(void) { - // setup PLL and clock ENET from it - SETBITS(CCM_ANALOG->PLL_ENET, CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK, - CCM_ANALOG_PLL_ENET_BYPASS_MASK | - CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(0)); // bypass to 24MHz osc - SETBITS( - CCM_ANALOG->PLL_ENET, - CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK, - CCM_ANALOG_PLL_ENET_DIV_SELECT(1) | CCM_ANALOG_PLL_ENET_ENABLE_MASK); - while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) - spin(1); // wait until it is stable - CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; - - gpio_init(PIN('1', 9), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_MEDIUM, GPIO_PULL_UP); // set GPIO1.9 as GPIO (PHY \RST) - gpio_write(PIN('1', 9), 0); // reset PHY - - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10, - 6); // set for ENET_REF_CLK - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10] |= - IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT, - 1); // drive peripheral from B1_10, so RMII clock is taken - // from ENET_REF_CLK - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - IOMUXC_GPR->GPR1 |= - IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(1); // Set ENET_TX_CLK as output - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04, 3); // set for RXDATA0 - periph_mux_config(kIOMUXC_ENET0_RXDATA_SELECT_INPUT, - 1); // drive peripheral from B1_04 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05, 3); // set for RXDATA1 - periph_mux_config(kIOMUXC_ENET1_RXDATA_SELECT_INPUT, - 1); // drive peripheral from B1_05 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06, 3); // set for CRS - periph_mux_config(kIOMUXC_ENET_RXEN_SELECT_INPUT, - 1); // drive peripheral from B1_06 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07, 3); // set for TXDATA0 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08, 3); // set for TXDATA1 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09, 3); // set for TXEN - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11, 3); // set for RXERR - periph_mux_config(kIOMUXC_ENET_RXERR_SELECT_INPUT, - 1); // drive peripheral from B1_11 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_HIGH, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, 4); // set for MDC - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_MEDIUM, GPIO_PULL_UP); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, 4); // set for MDIO - periph_mux_config(kIOMUXC_ENET_MDIO_SELECT_INPUT, - 1); // drive peripheral from EMC_41 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_MEDIUM, GPIO_PULL_UP); - - gpio_init(PIN('1', 10), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, - GPIO_SPEED_MEDIUM, - GPIO_PULL_UP); // set GPIO1.10 as GPIO (PHY INTRP/NAND_TREE) - gpio_write(PIN('1', 10), 1); // prevent NAND_TREE - spin(10000); // keep PHY RST low for a while - gpio_write(PIN('1', 9), 1); // deassert RST - gpio_init(PIN('1', 10), GPIO_MODE_INPUT, 0, GPIO_SPEED_MEDIUM, - GPIO_PULL_UP); // setup IRQ (pulled-up)(not used) - - clock_periph(1, CCM_CCGR1_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enet_ipg_clk - NVIC_EnableIRQ(ENET_IRQn); // Setup Ethernet IRQ handler -} - -// Helper macro for MAC generation, byte reads not allowed -#define GENERATE_LOCALLY_ADMINISTERED_MAC() \ - { \ - 2, OCOTP->CFG0 & 255, (OCOTP->CFG0 >> 10) & 255, \ - ((OCOTP->CFG0 >> 19) ^ (OCOTP->CFG1 >> 19)) & 255, \ - (OCOTP->CFG1 >> 10) & 255, OCOTP->CFG1 & 255 \ - } -// NOTE: You can fuse your own MAC and read it from OCOTP->MAC0, OCOTP->MAC1, -// OCOTP->MAC2 - -static inline void flash_init(void) { // QSPI in FlexSPI - // set pins - clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05, 1); // set for DQS - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT, 0); // drive peripheral from B1_05 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06, 1); // set for SS - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07, 1); // set for SCLK - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT, 0); // drive peripheral from B1_07 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08, 1); // set for DATA0 - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT, 0); // drive peripheral from B1_08 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09, 1); // set for DATA1 - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT, 0); // drive peripheral from B1_09 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10, 1); // set for DATA2 - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT, 0); // drive peripheral from B1_10 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11, 1); // set for DATA3 - IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin - periph_mux_config(kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT, 0); // drive peripheral from B1_11 - gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); - // set FlexSPI clock - SETBITS(CCM->CSCMR1, CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK | CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_CSCMR1_FLEXSPI_CLK_SEL(3) | CCM_CSCMR1_FLEXSPI_PODF(7)); // select PLL3 PFD0 /8 - clock_periph(6, CCM_CCGR6_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enable -} diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/link.ld b/examples/nxp/rt1060-evk-make-baremetal-builtin/link.ld deleted file mode 100644 index b4e753f3..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/link.ld +++ /dev/null @@ -1,24 +0,0 @@ -ENTRY(Reset_Handler); -MEMORY { - flash_hdr(rx) : ORIGIN = 0x60000000, LENGTH = 8k - flash_irq(rx) : ORIGIN = 0x60002000, LENGTH = 1k - flash_code(rx) : ORIGIN = 0x60002400, LENGTH = 8183k - - itcram(rx) : ORIGIN = 0x00000000, LENGTH = 128k - dtcram(rw) : ORIGIN = 0x20000000, LENGTH = 128k - ocram(rw) : ORIGIN = 0x20200000, LENGTH = 256k /* Is this cached ? */ -} -__StackTop = ORIGIN(dtcram) + LENGTH(dtcram); - -/* TODO(): separate itcram and go back to using dtcram for data and bss when ota is finished */ - -SECTIONS { - .hdr : { FILL(0xff) ; KEEP(*(.cfg)) . = 0x1000 ; KEEP(*(.ivt)) . = 0x1020 ; - KEEP(*(.dat)) . = 0x1030 ; KEEP(*(.dcd)) . = 0x2000 ;} >flash_hdr - .irq : { KEEP(*(.isr_vector)) } > flash_irq - .text : { *(.text* .text.*) *(.rodata*) ; } > flash_code - .data : { __data_start__ = .; *(.data SORT(.data.*)) *(.iram) __data_end__ = .; } > itcram AT > flash_code - __etext = LOADADDR(.data); - .bss : { __bss_start__ = .; *(.bss SORT(.bss.*) COMMON) __bss_end__ = .; } > itcram - _end = .; -} diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/main.c b/examples/nxp/rt1060-evk-make-baremetal-builtin/main.c deleted file mode 100644 index 7a66465a..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/main.c +++ /dev/null @@ -1,72 +0,0 @@ -// Copyright (c) 2022-2023 Cesanta Software Limited -// All rights reserved - -#include "hal.h" -#include "mongoose.h" -#include "net.h" - -#define BLINK_PERIOD_MS 1000 // LED blinking period in millis - -static volatile uint64_t s_ticks; // Milliseconds since boot -void SysTick_Handler(void) { // SyStick IRQ handler, triggered every 1ms - s_ticks++; -} - -uint64_t mg_millis(void) { // Let Mongoose use our uptime function - return s_ticks; // Return number of milliseconds since boot -} - -bool mg_random(void *buf, size_t len) { // Use on-board RNG - for (size_t n = 0; n < len; n += sizeof(uint32_t)) { - uint32_t r = rng_read(); - memcpy((char *) buf + n, &r, n + sizeof(r) > len ? len - n : sizeof(r)); - } - return true; -} - -static void timer_fn(void *arg) { - gpio_toggle(LED); // Blink LED - struct mg_tcpip_if *ifp = arg; // And show - const char *names[] = {"down", "up", "req", "ready"}; // network stats - MG_INFO(("Ethernet: %s, IP: %M, rx:%u, tx:%u, dr:%u, er:%u", - names[ifp->state], mg_print_ip4, &ifp->ip, ifp->nrecv, ifp->nsent, - ifp->ndrop, ifp->nerr)); -} - -int main(void) { - gpio_output(LED); // Setup blue LED - uart_init(UART_DEBUG, 115200); // Initialise debug printf - ethernet_init(); // Initialise ethernet pins - MG_INFO(("Starting, CPU freq %g MHz", (double) SystemCoreClock / 1000000)); - - struct mg_mgr mgr; // Initialise - mg_mgr_init(&mgr); // Mongoose event manager - mg_log_set(MG_LL_DEBUG); // Set log level - - // Initialise Mongoose network stack - struct mg_tcpip_driver_imxrt_data driver_data = {.mdc_cr = 24, .phy_addr = 2}; - struct mg_tcpip_if mif = {.mac = GENERATE_LOCALLY_ADMINISTERED_MAC(), - // Uncomment below for static configuration: - // .ip = mg_htonl(MG_U32(192, 168, 0, 223)), - // .mask = mg_htonl(MG_U32(255, 255, 255, 0)), - // .gw = mg_htonl(MG_U32(192, 168, 0, 1)), - .driver = &mg_tcpip_driver_imxrt, - .driver_data = &driver_data}; - mg_tcpip_init(&mgr, &mif); - mg_timer_add(&mgr, BLINK_PERIOD_MS, MG_TIMER_REPEAT, timer_fn, &mif); - - MG_INFO(("MAC: %M. Waiting for IP...", mg_print_mac, mif.mac)); - while (mif.state != MG_TCPIP_STATE_READY) { - mg_mgr_poll(&mgr, 0); - } - - MG_INFO(("Initialising application...")); - web_init(&mgr); - - MG_INFO(("Starting event loop")); - for (;;) { - mg_mgr_poll(&mgr, 0); - } - - return 0; -} diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/mongoose.c b/examples/nxp/rt1060-evk-make-baremetal-builtin/mongoose.c deleted file mode 120000 index 5e522bbc..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/mongoose.c +++ /dev/null @@ -1 +0,0 @@ -../../../mongoose.c \ No newline at end of file diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/mongoose.h b/examples/nxp/rt1060-evk-make-baremetal-builtin/mongoose.h deleted file mode 120000 index ee4ac823..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/mongoose.h +++ /dev/null @@ -1 +0,0 @@ -../../../mongoose.h \ No newline at end of file diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/mongoose_config.h b/examples/nxp/rt1060-evk-make-baremetal-builtin/mongoose_config.h deleted file mode 100644 index 55503eaa..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/mongoose_config.h +++ /dev/null @@ -1,14 +0,0 @@ -#pragma once - -// See https://mongoose.ws/documentation/#build-options -#define MG_ARCH MG_ARCH_NEWLIB -#define MG_OTA MG_OTA_FLASH -#define MG_DEVICE MG_DEVICE_RT1060 - -#define MG_ENABLE_TCPIP 1 -#define MG_ENABLE_DRIVER_IMXRT 1 -#define MG_IO_SIZE 256 -#define MG_ENABLE_CUSTOM_MILLIS 1 -#define MG_ENABLE_CUSTOM_RANDOM 1 -#define MG_ENABLE_PACKED_FS 1 - diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/net.c b/examples/nxp/rt1060-evk-make-baremetal-builtin/net.c deleted file mode 120000 index fe0e6f06..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/net.c +++ /dev/null @@ -1 +0,0 @@ -../../device-dashboard/net.c \ No newline at end of file diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/net.h b/examples/nxp/rt1060-evk-make-baremetal-builtin/net.h deleted file mode 120000 index 9de896ef..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/net.h +++ /dev/null @@ -1 +0,0 @@ -../../device-dashboard/net.h \ No newline at end of file diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/packed_fs.c b/examples/nxp/rt1060-evk-make-baremetal-builtin/packed_fs.c deleted file mode 120000 index e06bf092..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/packed_fs.c +++ /dev/null @@ -1 +0,0 @@ -../../device-dashboard/packed_fs.c \ No newline at end of file diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/syscalls.c b/examples/nxp/rt1060-evk-make-baremetal-builtin/syscalls.c deleted file mode 100644 index 6fef1007..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/syscalls.c +++ /dev/null @@ -1,98 +0,0 @@ -#include - -#include "hal.h" - -int _fstat(int fd, struct stat *st) { - if (fd < 0) return -1; - st->st_mode = S_IFCHR; - return 0; -} - -void *_sbrk(int incr) { - extern char _end; - static unsigned char *heap = NULL; - unsigned char *prev_heap; - unsigned char x = 0, *heap_end = (unsigned char *)((size_t) &x - 512); - (void) x; - if (heap == NULL) heap = (unsigned char *) &_end; - prev_heap = heap; - if (heap + incr > heap_end) return (void *) -1; - heap += incr; - return prev_heap; -} - -int _open(const char *path) { - (void) path; - return -1; -} - -int _close(int fd) { - (void) fd; - return -1; -} - -int _isatty(int fd) { - (void) fd; - return 1; -} - -int _lseek(int fd, int ptr, int dir) { - (void) fd, (void) ptr, (void) dir; - return 0; -} - -void _exit(int status) { - (void) status; - for (;;) asm volatile("BKPT #0"); -} - -void _kill(int pid, int sig) { - (void) pid, (void) sig; -} - -int _getpid(void) { - return -1; -} - -int _write(int fd, char *ptr, int len) { - (void) fd, (void) ptr, (void) len; - if (fd == 1) uart_write_buf(UART_DEBUG, ptr, (size_t) len); - return -1; -} - -int _read(int fd, char *ptr, int len) { - (void) fd, (void) ptr, (void) len; - return -1; -} - -int _link(const char *a, const char *b) { - (void) a, (void) b; - return -1; -} - -int _unlink(const char *a) { - (void) a; - return -1; -} - -int _stat(const char *path, struct stat *st) { - (void) path, (void) st; - return -1; -} - -int mkdir(const char *path, mode_t mode) { - (void) path, (void) mode; - return -1; -} - -void _init(void) {} - -extern uint64_t mg_now(void); - -int _gettimeofday(struct timeval *tv, void *tz) { - uint64_t now = mg_now(); - (void) tz; - tv->tv_sec = (time_t) (now / 1000); - tv->tv_usec = (unsigned long) ((now % 1000) * 1000); - return 0; -} diff --git a/examples/nxp/rt1060-evk-make-baremetal-builtin/sysinit.c b/examples/nxp/rt1060-evk-make-baremetal-builtin/sysinit.c deleted file mode 100644 index cfac5dae..00000000 --- a/examples/nxp/rt1060-evk-make-baremetal-builtin/sysinit.c +++ /dev/null @@ -1,79 +0,0 @@ -// Copyright (c) 2023 Cesanta Software Limited -// All rights reserved -// -// This file contains essentials required by the CMSIS: -// uint32_t SystemCoreClock - holds the system core clock value -// SystemInit() - initialises the system, e.g. sets up clocks - -#include "hal.h" - -uint32_t SystemCoreClock = SYS_FREQUENCY; - -// - 14.4, Figure 14-2: clock tree -// - 14.7.4: ARM_PODF defaults to /2; 9.5.3 Table 9-7: ROM agrees -// - 14.7.5: AHB_PODF defaults to /1; IPG_PODF defaults to /4; PERIPH_CLK_SEL -// defaults to derive clock from pre_periph_clk_sel -// - 9.5.3 Table 9-7: ROM changes IPG_PODF to /3 -// - 14.7.6: PRE_PERIPH_CLK_SEL defaults to derive clock from divided -// PLL1; 9.5.3 Table 9-7: ROM agrees -// - (For 528MHz operation, we need to set it to derive clock from PLL2) -// - 14.7.7: PER_CLK defaults to IPG/1; 9.5.3 Table 9-7: ROM changes it to IPG/2 -// - 14.6.1.3.1 ARM PLL (PLL1); 13.3.2.2 PLLs -// - 14.8.1: PLL1 is powered off and bypassed to 24MHz. Fout = 24MHz * -// div_select/2 -// - 9.5.3 Table 9-7: ROM enables this PLL and sets it up -// - For 600MHz operation, we need to set PLL1 on -// - Datasheet 4.1.3: System frequency/Bus frequency max 600/150MHz respectively -// (AHB/IPG) -// - MCUXpresso: IPG_CLK_ROOT <= 150MHz; PERCLK_CLK_ROOT <= 75MHz -// - Datasheet 4.9.4.1.1/2: the processor clock frequency must exceed twice the -// ENET_RX_CLK/ENET_TX_CLK frequency. -// - Datasheet 4.9.4.2: no details for RMII (above is for MII), assumed 50MHz -// min processor clock -// - Datasheet 4.1.3, Table 10: "Overdrive" run mode requires 1.25V core voltage -// minimum; 528 MHz does not. -void SystemInit(void) { // Called automatically by startup code (ints masked) - SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU - asm("DSB"); - asm("ISB"); - // 58.4.2: Disable watchdog after reset (unlocked) - RTWDOG->CS &= ~RTWDOG_CS_EN_MASK; - RTWDOG->TOVAL = 0xFFFF; - while (RTWDOG->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock - while ((RTWDOG->CS & RTWDOG_CS_RCS_MASK) == 0) - spin(1); // wait for new config - // Set VDD_SOC to 1.25V - SETBITS(DCDC->REG3, DCDC_REG3_TRG_MASK, DCDC_REG3_TRG(0x12)); - while ((DCDC->REG0 & DCDC_REG0_STS_DC_OK_MASK) == 0) - spin(1); // Wait for DCDC_STS_DC_OK - // ROM fiddles with AHB divider, wait and then keep bits at 0 (expected) - while (CCM->CDHIPR & CCM_CDHIPR_AHB_PODF_BUSY_MASK) spin(1); - SETBITS(CCM->CBCDR, CCM_CBCDR_IPG_PODF_MASK | CCM_CBCDR_AHB_PODF_MASK, - CCM_CBCDR_IPG_PODF(3)); // keep AHB, set IPG divider /4 (150MHz) - SETBITS(CCM->CSCMR1, CCM_CSCMR1_PERCLK_PODF_MASK, - CCM_CSCMR1_PERCLK_PODF(1)); // Set PERCLK divider /2 (75MHz) - // Set clock to 600 MHz. Power PLL on and configure divider (ROM boot code - // fiddles with the PLL, bypass first) - CCM_ANALOG->PLL_ARM |= CCM_ANALOG_PLL_ARM_BYPASS_MASK; - SETBITS(CCM_ANALOG->PLL_ARM, - CCM_ANALOG_PLL_ARM_POWERDOWN_MASK | - CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK, - CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(100)); - while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0) - spin(1); // wait until it is stable - CCM_ANALOG->PLL_ARM &= - ~CCM_ANALOG_PLL_ARM_BYPASS_MASK; // Disable Bypass (switch to PLL) - // 14.5 Table 14-4: uart_clk_root - // 14.4: uart_clk_root = PLL3/6 or OSC; CCM_CSCDR1 (14.7.9) defaults to - // PLL3/6/1; but ROM boot code fiddles with the divider (9.5.3 Table 9-7) - CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_POWER_MASK; // Power PLL on - while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) - spin(1); // wait until it is stable - CCM_ANALOG->PLL_USB1 &= - ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; // Disable Bypass (switch to PLL) - CCM->CSCDR1 &= - ~(CCM_CSCDR1_UART_CLK_SEL_MASK | CCM_CSCDR1_UART_CLK_PODF_MASK); - rng_init(); // Initialise random number generator - // NXP startup code calls SystemInit BEFORE initializing RAM... - SysTick_Config(SYS_FREQUENCY / 1000); // Sys tick every 1ms -}