// Copyright (c) 2023 Cesanta Software Limited // All rights reserved // https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMXRT1060XRM.pdf // https://cache.nxp.com/secured/assets/documents/en/user-guide/MIMXRT1060EVKBUM.pdf #pragma once #include "MIMXRT1062.h" #include #include #include #include #define BIT(x) (1UL << (x)) #define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK) #define PIN(bank, num) ((((bank) - '0') << 8) | (num)) #define PINNO(pin) (pin & 255) #define PINBANK(pin) (pin >> 8) void hal_init(void); size_t hal_ram_free(void); size_t hal_ram_used(void); bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now); uint64_t hal_get_tick(void); // No settable constants, see sysinit.c #define SYS_FREQUENCY 600000000UL static inline void spin(volatile uint32_t count) { while (count--) (void) 0; } enum { CLOCK_OFF = 0U, CLOCK_ON_RUN = 1U, CLOCK_ON_RUN_WAIT = 3U }; static inline void hal_clock_periph(uint32_t index, uint32_t shift, uint32_t val) { volatile uint32_t *r = &CCM->CCGR0; SETBITS(r[index], 3UL << shift, val << shift); } // which peripheral feeds the pin static inline void hal_gpio_mux_config(uint16_t index, uint8_t af) { IOMUXC->SW_MUX_CTL_PAD[index] = af; } // which pin feeds the peripheral (2nd stage) static inline void hal_periph_mux_config(uint16_t index, uint8_t in) { IOMUXC->SELECT_INPUT[index] = in; } enum { GPIO_MODE_INPUT, GPIO_MODE_OUTPUT }; enum { GPIO_OTYPE_PUSH_PULL, GPIO_OTYPE_OPEN_DRAIN }; enum { GPIO_SPEED_LOW, GPIO_SPEED_MEDIUM, GPIO_SPEED_MEDIUM_, GPIO_SPEED_HIGH }; enum { GPIO_PULL_NONE, GPIO_PULL_DOWN, GPIO_PULL_UP }; static inline GPIO_Type *hal_gpio_bank(uint16_t pin) { static const GPIO_Type *g[] = {NULL, GPIO1, GPIO2, GPIO3, NULL, GPIO5}; return (GPIO_Type *) g[PINBANK(pin)]; } // pin driver/pull-up/down configuration (ignore "keeper") static inline void hal_gpio_pad_config(uint16_t index, uint8_t type, uint8_t speed, uint8_t pull) { bool dopull = pull > 0; if (dopull) --pull; IOMUXC->SW_PAD_CTL_PAD[index] = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_ODE(type) | IOMUXC_SW_PAD_CTL_PAD_SRE(speed >= GPIO_SPEED_HIGH) | IOMUXC_SW_PAD_CTL_PAD_PUE(1) | IOMUXC_SW_PAD_CTL_PAD_PKE(dopull) | IOMUXC_SW_PAD_CTL_PAD_PUS(pull) | IOMUXC_SW_PAD_CTL_PAD_DSE(7); } static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type, uint8_t speed, uint8_t pull) { GPIO_Type *gpio = hal_gpio_bank(pin); uint8_t bit = (uint8_t) PINNO(pin); uint32_t mask = (uint32_t) BIT(PINNO(pin)); hal_clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s switch (PINBANK(pin)) { case 1: hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 + bit, 5); hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 + bit, type, speed, pull); hal_clock_periph(1, CCM_CCGR1_CG13_SHIFT, CLOCK_ON_RUN_WAIT); break; case 2: hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 + bit, 5); hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 + bit, type, speed, pull); hal_clock_periph(0, CCM_CCGR0_CG15_SHIFT, CLOCK_ON_RUN_WAIT); break; case 3: hal_gpio_mux_config(bit < 12 ? kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 + bit : bit < 18 ? kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 + bit - 12 : kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 + bit - 18, 5); hal_gpio_pad_config(bit < 12 ? kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 + bit : bit < 18 ? kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 + bit - 12 : kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 + bit - 18, type, speed, pull); hal_clock_periph(2, CCM_CCGR2_CG13_SHIFT, CLOCK_ON_RUN_WAIT); break; case 5: // TODO(): support sw_mux hal_clock_periph(1, CCM_CCGR1_CG15_SHIFT, CLOCK_ON_RUN_WAIT); break; default: break; } gpio->IMR &= ~mask; if (mode == GPIO_MODE_INPUT) { gpio->GDIR &= ~mask; } else { gpio->GDIR |= mask; } } static inline void hal_gpio_input(uint16_t pin) { hal_gpio_init(pin, GPIO_MODE_INPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_NONE); } static inline void hal_gpio_output(uint16_t pin) { hal_gpio_init(pin, GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_NONE); } static inline bool hal_gpio_read(uint16_t pin) { GPIO_Type *gpio = hal_gpio_bank(pin); uint32_t mask = (uint32_t) BIT(PINNO(pin)); return gpio->DR & mask; } static inline void hal_gpio_write(uint16_t pin, bool value) { GPIO_Type *gpio = hal_gpio_bank(pin); uint32_t mask = (uint32_t) BIT(PINNO(pin)); if (value) { gpio->DR |= mask; } else { gpio->DR &= ~mask; } } static inline void hal_gpio_toggle(uint16_t pin) { hal_gpio_write(pin, !hal_gpio_read(pin)); } // 14.5 Table 14-4: uart_clk_root // see sysinit.c for clocks, (14.7.9: defaults to pll3_80m = PLL3/6/1 = 80MHz) static inline void hal_uart_init(LPUART_Type *uart, unsigned long baud) { uint8_t af = 2; // Alternate function uint16_t mr = 0, pr = 0, mt = 0, pt = 0; // pins uint32_t freq = 80000000; // uart_clk_root frequency if (uart == LPUART1) mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12, pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12, mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13, pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13; if (uart == LPUART3) mt = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06, pt = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06, mr = kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07, pr = kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07; if (uart == LPUART1) hal_clock_periph(5, CCM_CCGR5_CG12_SHIFT, CLOCK_ON_RUN_WAIT); if (uart == LPUART3) hal_clock_periph(0, CCM_CCGR0_CG6_SHIFT, CLOCK_ON_RUN_WAIT); hal_clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s hal_gpio_mux_config(mt, af); hal_gpio_pad_config(pt, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); hal_gpio_mux_config(mr, af); hal_gpio_pad_config(pr, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; SETBITS(uart->BAUD, LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK, LPUART_BAUD_OSR(16 - 1) | LPUART_BAUD_SBR(freq / (16 * baud))); // Rx sample at 16x SETBITS(uart->CTRL, LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | LPUART_CTRL_IDLECFG_MASK, LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) | LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK; } static inline void hal_uart_write_byte(LPUART_Type *uart, uint8_t byte) { uart->DATA = byte; while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) spin(1); } static inline void hal_uart_write_buf(LPUART_Type *uart, char *buf, size_t len) { while (len-- > 0) hal_uart_write_byte(uart, *(uint8_t *) buf++); } static inline int hal_uart_read_ready(LPUART_Type *uart) { (void) uart; return uart->STAT & LPUART_STAT_RDRF_MASK; } static inline uint8_t hal_uart_read_byte(LPUART_Type *uart) { return (uint8_t) (uart->DATA & 255); } static inline void hal_rng_init(void) { hal_clock_periph(6, CCM_CCGR6_CG6_SHIFT, CLOCK_ON_RUN_WAIT); // trng_clk SETBITS(TRNG->MCTL, TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK | TRNG_MCTL_RST_DEF_MASK, TRNG_MCTL_PRGM(1) | TRNG_MCTL_ERR(1) | TRNG_MCTL_RST_DEF(1)); // reset to default values SETBITS(TRNG->MCTL, TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK, TRNG_MCTL_PRGM(0)); // set to run mode (void) TRNG->ENT[TRNG_ENT_COUNT - 1]; // start new entropy generation (void) TRNG->ENT[0]; // defect workaround } static inline uint32_t hal_rng_read(void) { static uint8_t idx = 0; while ((TRNG->MCTL & TRNG_MCTL_ENT_VAL_MASK) == 0) (void) 0; uint32_t data = TRNG->ENT[idx++]; // read data idx %= TRNG_ENT_COUNT; // stay within array limits if (idx == 0) // we've just read TRNG_ENT_COUNT - 1 (void) TRNG->ENT[0]; // defect workaround return data; } // - PHY has no xtal, XI driven from ENET_REF_CLK1 (labeled as ENET_TX_REF_CLK // (GPIO_AD_B1_10)), generated by the MCU // - PHY RST connected to GPIO1.9 (GPIO_AD_B0_09); INTRP/NAND_TREE connected to // GPIO1.10 (GPIO_AD_B0_10) // - 41.4 REF_CLK1 is RMII mode reference clock for Rx, Tx, and SMI; it is I/O // - 11.3.2 IOMUXC_GPR_GPR1 // - bit 13: ENET1_CLK_SEL --> 0 ENET1 TX reference clock driven by // ref_enetpll and output via ENET_REF_CLK1 (labeled as ENET_REF_CLK // elsewhere) // - bit 17: ENET1_TX_CLK_DIR --> 1 ENET1_TX_CLK output driver enabled // - 14.6.1.3.6 Ethernet PLL (PLL6) // - 14.8.14: configure PLL6 to generate 50MHz clocks for ENET and RMII. static inline void hal_ethernet_init(void) { // setup PLL and clock ENET from it SETBITS(CCM_ANALOG->PLL_ENET, CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK, CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(0)); // bypass to 24MHz osc SETBITS( CCM_ANALOG->PLL_ENET, CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK, CCM_ANALOG_PLL_ENET_DIV_SELECT(1) | CCM_ANALOG_PLL_ENET_ENABLE_MASK); while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) spin(1); // wait until it is stable CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; hal_gpio_init(PIN('1', 9), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); // set GPIO1.9 as GPIO (PHY \RST) hal_gpio_write(PIN('1', 9), 0); // reset PHY hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10, 6); // set for ENET_REF_CLK IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin hal_periph_mux_config(kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT, 1); // drive peripheral from B1_10, so RMII clock is taken // from ENET_REF_CLK hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_UP); IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(1); // Set ENET_TX_CLK as output hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04, 3); // set for RXDATA0 hal_periph_mux_config(kIOMUXC_ENET0_RXDATA_SELECT_INPUT, 1); // drive peripheral from B1_04 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_UP); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05, 3); // set for RXDATA1 hal_periph_mux_config(kIOMUXC_ENET1_RXDATA_SELECT_INPUT, 1); // drive peripheral from B1_05 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_UP); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06, 3); // set for CRS hal_periph_mux_config(kIOMUXC_ENET_RXEN_SELECT_INPUT, 1); // drive peripheral from B1_06 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_UP); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07, 3); // set for TXDATA0 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_UP); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08, 3); // set for TXDATA1 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_UP); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09, 3); // set for TXEN hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_UP); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11, 3); // set for RXERR hal_periph_mux_config(kIOMUXC_ENET_RXERR_SELECT_INPUT, 1); // drive peripheral from B1_11 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_UP); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40, 4); // set for MDC hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41, 4); // set for MDIO hal_periph_mux_config(kIOMUXC_ENET_MDIO_SELECT_INPUT, 1); // drive peripheral from EMC_41 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); hal_gpio_init(PIN('1', 10), GPIO_MODE_OUTPUT, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); // set GPIO1.10 as GPIO (PHY INTRP/NAND_TREE) hal_gpio_write(PIN('1', 10), 1); // prevent NAND_TREE spin(10000); // keep PHY RST low for a while hal_gpio_write(PIN('1', 9), 1); // deassert RST hal_gpio_init(PIN('1', 10), GPIO_MODE_INPUT, 0, GPIO_SPEED_MEDIUM, GPIO_PULL_UP); // setup IRQ (pulled-up)(not used) hal_clock_periph(1, CCM_CCGR1_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enet_ipg_clk NVIC_EnableIRQ(ENET_IRQn); // Setup Ethernet IRQ handler } static inline void hal_clock_init(void) { // 53.4.2: Disable watchdog after reset (unlocked) RTWDOG->CS &= ~RTWDOG_CS_EN_MASK; RTWDOG->TOVAL = 0xFFFF; while (RTWDOG->CS & RTWDOG_CS_ULK_MASK) spin(1); // wait for lock while ((RTWDOG->CS & RTWDOG_CS_RCS_MASK) == 0) spin(1); // wait for new config // Set VDD_SOC to 1.25V SETBITS(DCDC->REG3, DCDC_REG3_TRG_MASK, DCDC_REG3_TRG(0x12)); while ((DCDC->REG0 & DCDC_REG0_STS_DC_OK_MASK) == 0) spin(1); // Wait for DCDC_STS_DC_OK // ROM fiddles with AHB divider, wait and then keep bits at 0 (expected) while (CCM->CDHIPR & CCM_CDHIPR_AHB_PODF_BUSY_MASK) spin(1); SETBITS(CCM->CBCDR, CCM_CBCDR_IPG_PODF_MASK | CCM_CBCDR_AHB_PODF_MASK, CCM_CBCDR_IPG_PODF(3)); // keep AHB, set IPG divider /4 (150MHz) SETBITS(CCM->CSCMR1, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_CSCMR1_PERCLK_PODF(1)); // Set PERCLK divider /2 (75MHz) // Set clock to 600 MHz. Power PLL on and configure divider (ROM boot code // fiddles with the PLL, bypass first) CCM_ANALOG->PLL_ARM |= CCM_ANALOG_PLL_ARM_BYPASS_MASK; SETBITS(CCM_ANALOG->PLL_ARM, CCM_ANALOG_PLL_ARM_POWERDOWN_MASK | CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK, CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(100)); while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0) spin(1); // wait until it is stable CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK; // Disable Bypass (switch to PLL) // 14.5 Table 14-4: uart_clk_root // 14.4: uart_clk_root = PLL3/6 or OSC; CCM_CSCDR1 (14.7.9) defaults to // PLL3/6/1; but ROM boot code fiddles with the divider (9.5.3 Table 9-7) CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_POWER_MASK; // Power PLL on while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) spin(1); // wait until it is stable CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; // Disable Bypass (switch to PLL) CCM->CSCDR1 &= ~(CCM_CSCDR1_UART_CLK_SEL_MASK | CCM_CSCDR1_UART_CLK_PODF_MASK); } #if defined(__MCUXPRESSO) #undef MG_HAL_DISABLE_SYSTEM_INIT #define MG_HAL_DISABLE_SYSTEM_INIT 1 #undef MG_HAL_SBRK_NONE #define MG_HAL_SBRK_NONE 1 #endif static inline void hal_system_init(void) { extern long _siram, _eiram, _siiram; for (long *dst = &_siram, *src = &_siiram; dst < &_eiram;) *dst++ = *src++; SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); // Enable FPU __DSB(); __ISB(); } static inline void hal_flash_init(void) { // QSPI in FlexSPI // set pins hal_clock_periph(4, CCM_CCGR4_CG1_SHIFT, CLOCK_ON_RUN_WAIT); // iomuxc_ipg_clk_s hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05, 1); // set for DQS IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin hal_periph_mux_config(kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT, 0); // drive peripheral from B1_05 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06, 1); // set for SS IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07, 1); // set for SCLK IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin hal_periph_mux_config(kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT, 0); // drive peripheral from B1_07 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08, 1); // set for DATA0 IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin hal_periph_mux_config(kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT, 0); // drive peripheral from B1_08 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09, 1); // set for DATA1 IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin hal_periph_mux_config(kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT, 0); // drive peripheral from B1_09 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10, 1); // set for DATA2 IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin hal_periph_mux_config(kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT, 0); // drive peripheral from B1_10 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); hal_gpio_mux_config(kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11, 1); // set for DATA3 IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11] |= IOMUXC_SW_MUX_CTL_PAD_SION(1); // loop signal back from pin hal_periph_mux_config(kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT, 0); // drive peripheral from B1_11 hal_gpio_pad_config(kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11, GPIO_OTYPE_PUSH_PULL, GPIO_SPEED_HIGH, GPIO_PULL_NONE); // set FlexSPI clock SETBITS(CCM->CSCMR1, CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK | CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_CSCMR1_FLEXSPI_CLK_SEL(3) | CCM_CSCMR1_FLEXSPI_PODF(7)); // select PLL3 PFD0 /8 hal_clock_periph(6, CCM_CCGR6_CG5_SHIFT, CLOCK_ON_RUN_WAIT); // enable }