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65 lines
1.8 KiB
Plaintext
65 lines
1.8 KiB
Plaintext
ENTRY(Reset_Handler)
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MEMORY {
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boot_hdr (rx) : ORIGIN = 0x04000000, LENGTH = 0x0000b000
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flash_irq (rx) : ORIGIN = 0x0400b000, LENGTH = 0x00000400
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flash (rx) : ORIGIN = 0x0400b400, LENGTH = 0x00ff4c00
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itcm (rwx) : ORIGIN = 0x0ffe0000, LENGTH = 128k
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dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 128k
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ocram1 (rw) : ORIGIN = 0x204c0000, LENGTH = 256k
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}
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__StackSize = 4k;
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__StackTop = ORIGIN(dtcm) + LENGTH(dtcm);
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__StackLimit = __StackTop - __StackSize;
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SECTIONS {
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.boot_hdr : {
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FILL(0x00)
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. = 0x0400; KEEP(*(.boot_hdr.conf))
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. = 0x0800; KEEP(*(.boot_hdr.xmcd_data))
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. = 0x1000; __boot_hdr_container__ = ABSOLUTE(.); KEEP(*(.boot_hdr.container))
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. = 0xb000;
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} > boot_hdr
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.isr_vector ALIGN(1024) : { KEEP(*(.isr_vector)) } > flash_irq
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.text : { *(.text .text.*) *(.rodata .rodata.*) *(.constdata .constdata.*) } > flash
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.iram : { _siram = .; *(.iram .iram.*) . = ALIGN(4); _eiram = .; } > itcm AT > flash
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_siiram = LOADADDR(.iram);
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.data : {
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__data_start__ = .;
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*(.data SORT(.data.*)) *(.sdata SORT(.sdata.*))
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. = ALIGN(4);
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__data_end__ = .;
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} > dtcm AT > flash
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__data_flash_start = LOADADDR(.data);
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.bss (NOLOAD) : {
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__bss_start__ = .;
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*(.bss SORT(.bss.*)) *(.sbss SORT(.sbss.*)) *(COMMON)
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. = ALIGN(4);
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__bss_end__ = .;
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} > dtcm
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_end = ALIGN(8);
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/* Required by startup only; hal.c manages the dynamic heap from _end. */
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__HeapBase = _end;
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__HeapLimit = _end;
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.eth_ram (NOLOAD) : {
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. = ALIGN(64);
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__eth_ram_start__ = .;
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*(.eth_ram .eth_ram.*)
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. = ALIGN(64);
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__eth_ram_end__ = .;
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} > ocram1
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_image_size = LOADADDR(.data) + SIZEOF(.data) - ADDR(.isr_vector);
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_image_loadaddr = ADDR(.isr_vector);
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_image_offset = ADDR(.isr_vector) - __boot_hdr_container__;
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}
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