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https://github.com/cesanta/mongoose.git
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290 lines
10 KiB
C
290 lines
10 KiB
C
// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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// MCXE24x Series Reference Manual (MCXE24XRM)
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// FRDM-MCXE247 Board User Manual: UM12286
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include "MCXE247.h"
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#include <fsl_clock.h>
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#define BIT(x) (1UL << (x))
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#define CLRSET(reg, clear, set) ((reg) = ((reg) & ~(clear)) | (set))
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#define PIN(bank, num) ((((bank) - 'A') << 8) | (num))
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#define PINNO(pin) (pin & 255)
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#define PINBANK(pin) (pin >> 8)
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void hal_init(void);
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size_t hal_ram_free(void);
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size_t hal_ram_used(void);
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bool hal_timer_expired(volatile uint64_t *t, uint64_t period, uint64_t now);
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uint64_t hal_get_tick(void);
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static inline void spin(volatile uint32_t count) {
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while (count--)
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(void)0;
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}
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#define SYS_FREQUENCY 80000000UL
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enum { HAL_GPIO_MODE_INPUT, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_MODE_AF };
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enum { HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_OTYPE_OPEN_DRAIN };
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enum { HAL_GPIO_SPEED_LOW, HAL_GPIO_SPEED_HIGH };
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enum { HAL_GPIO_PULL_NONE, HAL_GPIO_PULL_DOWN, HAL_GPIO_PULL_UP };
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static inline GPIO_Type *hal_gpio_bank(uint16_t pin) {
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static GPIO_Type *const g[] = GPIO_BASE_PTRS;
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return g[PINBANK(pin)];
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}
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static inline void hal_gpio_init(uint16_t pin, uint8_t mode, uint8_t type,
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uint8_t speed, uint8_t pull, uint8_t af) {
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static PORT_Type *const p[] = PORT_BASE_PTRS;
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PORT_Type *port = p[PINBANK(pin)];
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GPIO_Type *gpio = hal_gpio_bank(pin);
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uint32_t mask = (uint32_t)BIT(PINNO(pin));
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bool dopull = pull > 0;
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if (gpio == GPIOA) {
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CLOCK_EnableClock(kCLOCK_PortA);
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} else if (gpio == GPIOB) {
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CLOCK_EnableClock(kCLOCK_PortB);
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} else if (gpio == GPIOC) {
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CLOCK_EnableClock(kCLOCK_PortC);
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} else if (gpio == GPIOD) {
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CLOCK_EnableClock(kCLOCK_PortD);
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} else if (gpio == GPIOE) {
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CLOCK_EnableClock(kCLOCK_PortE);
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}
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if (dopull)
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--pull;
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port->PCR[PINNO(pin)] = PORT_PCR_MUX(af) | PORT_PCR_DSE(1) |
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PORT_PCR_PE(dopull) | PORT_PCR_PS(pull);
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if (mode == HAL_GPIO_MODE_INPUT) {
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gpio->PDDR &= ~mask;
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} else if (mode == HAL_GPIO_MODE_OUTPUT) {
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gpio->PDDR |= mask;
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}
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(void) type, (void) speed;
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}
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static inline void hal_gpio_input(uint16_t pin) {
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hal_gpio_init(pin, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_LOW,
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HAL_GPIO_PULL_NONE, 1);
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}
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static inline void hal_gpio_output(uint16_t pin) {
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hal_gpio_init(pin, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_LOW,
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HAL_GPIO_PULL_NONE, 1);
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}
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static inline bool hal_gpio_read(uint16_t pin) {
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GPIO_Type *gpio = hal_gpio_bank(pin);
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return gpio->PDIR & PINNO(pin);
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}
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static inline void hal_gpio_write(uint16_t pin, bool value) {
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GPIO_Type *gpio = hal_gpio_bank(pin);
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if (value) {
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gpio->PDOR |= (1 << PINNO(pin));
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} else {
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gpio->PDOR &= ~(1 << PINNO(pin));
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}
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}
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static inline void hal_gpio_toggle(uint16_t pin) {
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GPIO_Type *gpio = hal_gpio_bank(pin);
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uint32_t mask = (uint32_t)BIT(PINNO(pin));
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gpio->PTOR = mask;
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}
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static inline void hal_uart_init(LPUART_Type *uart, unsigned long baud) {
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uint8_t af = 3; // Alternate function
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uint16_t pr = 0, pt = 0; // pins
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uint32_t freq = 8000000; // 8MHz (System Oscillator clock)
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uint32_t lpuart_clk;
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if (uart == LPUART2)
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lpuart_clk = kCLOCK_Lpuart2, pt = PIN('E', 12), pr = PIN('D', 17);
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if (uart == LPUART1)
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lpuart_clk = kCLOCK_Lpuart1, pt = PIN('C', 9), pr = PIN('C', 8);
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CLOCK_SetIpSrc(lpuart_clk, kCLOCK_IpSrcSysOscAsync);
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hal_gpio_init(pt, HAL_GPIO_MODE_OUTPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_LOW,
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HAL_GPIO_PULL_UP, af);
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hal_gpio_init(pr, HAL_GPIO_MODE_INPUT, HAL_GPIO_OTYPE_PUSH_PULL, HAL_GPIO_SPEED_LOW,
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HAL_GPIO_PULL_UP, af);
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CLOCK_EnableClock(lpuart_clk);
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uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults
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uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
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// use an oversample ratio of 23
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CLRSET(uart->BAUD,
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LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK,
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LPUART_BAUD_OSR(23 - 1) | LPUART_BAUD_SBR(freq / (23 * baud)));
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CLRSET(uart->CTRL,
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LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
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LPUART_CTRL_IDLECFG_MASK,
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LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) |
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LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit
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uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
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}
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static inline void hal_uart_write_byte(LPUART_Type *uart, uint8_t byte) {
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uart->DATA = byte;
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while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0)
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spin(1);
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}
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static inline void hal_uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
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while (len-- > 0)
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hal_uart_write_byte(uart, *(uint8_t *)buf++);
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}
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static inline void hal_ethernet_init(void) {
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// enable peripheral clock
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uint32_t reg = (*(volatile uint32_t *)(uint32_t)kCLOCK_Enet);
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reg = (reg & ~(PCC_CLKCFG_PCS_MASK | PCC_CLKCFG_FRAC_MASK | PCC_CLKCFG_PCD_MASK)) | PCC_CLKCFG_PCS(6) |
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PCC_CLKCFG_PCD(1) | PCC_CLKCFG_FRAC(1);
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(*(volatile uint32_t *)(uint32_t)kCLOCK_Enet) = reg & ~PCC_CLKCFG_CGC_MASK;
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(*(volatile uint32_t *)(uint32_t)kCLOCK_Enet) = reg;
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CLOCK_EnableClock(kCLOCK_Enet);
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// init pins
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hal_gpio_init(PIN('C', 3), HAL_GPIO_MODE_OUTPUT, 0, 0, HAL_GPIO_PULL_NONE, 1); // PHY_RST
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hal_gpio_write(PIN('C', 3), 1);
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hal_gpio_init(PIN('B', 4), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_MDIO
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hal_gpio_init(PIN('C', 0), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 4); // MII_RMII_RXD1
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hal_gpio_init(PIN('C', 1), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_RXD0
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hal_gpio_init(PIN('C', 17), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_RX_DV
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hal_gpio_init(PIN('C', 2), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_TXD0
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hal_gpio_init(PIN('D', 11), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_TX_CLK
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hal_gpio_init(PIN('D', 12), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_TX_EN
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hal_gpio_init(PIN('D', 7), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_TXD1
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hal_gpio_init(PIN('E', 8), HAL_GPIO_MODE_AF, 0, 0, HAL_GPIO_PULL_NONE, 5); // MII_RMII_MDC
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// reset PHY
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hal_gpio_write(PIN('C', 3), 0);
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spin(50000);
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hal_gpio_write(PIN('C', 3), 1);
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NVIC_EnableIRQ(ENET_Receive_IRQn);
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}
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static inline void hal_rtc_init(void) {
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// Configure RTC clock to generate seeds
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// Reconfigure it there as needed.
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SIM->LPOCLKS = 0x13; // LPO32K_CLK, LPO32KCLKEN, LPO1KCLKEN
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CLOCK_EnableClock(kCLOCK_Rtc0);
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// If Time Invalid Flag set, reset the RTC
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if (RTC->SR & RTC_SR_TIF_MASK) {
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RTC->CR |= RTC_CR_SWR_MASK;
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RTC->CR &= ~RTC_CR_SWR_MASK;
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}
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RTC->IER &= ~(RTC_IER_TSIC_MASK | RTC_IER_TSIE_MASK);
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RTC->SR |= RTC_SR_TCE_MASK; // Enable timer
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}
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static inline void hal_clock_init(void) {
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// init SysOsc
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SCG->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
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SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV1(1) | SCG_SOSCDIV_SOSCDIV2(1);
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SCG->SOSCCFG = BIT(2) | SCG_SOSCCFG_RANGE(2); // work mode, range
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SCG->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
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while ((SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0) spin(1);
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// init FIRC
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SCG->SIRCCSR = 0U;
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SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(0) | SCG_SIRCDIV_SIRCDIV2(2);
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SCG->SIRCCFG = SCG_SIRCCFG_RANGE(1);
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SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | BIT(0);
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while ((SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0) spin(1);
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// Change to use SIRC as system clock source
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SCG->RCCR = SCG_RCCR_DIVSLOW(3) | SCG_RCCR_SCS(2);
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while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) != 2) spin(1);
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SCG->FIRCDIV = SCG_FIRCDIV_FIRCDIV1(1) | SCG_FIRCDIV_FIRCDIV2(1);
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SCG->FIRCCFG = SCG_FIRCCFG_RANGE(0);
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SCG->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK;
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while ((SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0) spin(1);
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SCG->RCCR = SCG_RCCR_DIVSLOW(3) | SCG_RCCR_SCS(3); // Change to FIRC
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while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) != 3) spin(1);
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// init SIRC
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SCG->SIRCCSR = 0U;
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SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(1) | SCG_SIRCDIV_SIRCDIV2(2);
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SCG->SIRCCFG = SCG_SIRCCFG_RANGE(1);
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SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | BIT(2);
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while ((SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0) spin(1);
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// init SysPLL
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SCG->SPLLCSR = SCG_SPLLCSR_SPLLERR_MASK;
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SCG->SPLLDIV = SCG_SPLLDIV_SPLLDIV1(2) | SCG_SPLLDIV_SPLLDIV2(0);
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SCG->SPLLCFG = SCG_SPLLCFG_PREDIV(0) | SCG_SPLLCFG_MULT(24);
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SCG->SPLLCSR = (uint32_t)SCG_SPLLCSR_SPLLEN_MASK ;
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while ((SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK) == 0) spin(1);
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// Set SCG to SPLL mode
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SCG->RCCR = SCG_RCCR_DIVSLOW(4) | SCG_RCCR_DIVBUS(1) | SCG_RCCR_DIVCORE(1) | SCG_RCCR_SCS(6);
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while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) != 6) spin(1);
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// Set SCG CLKOUT selection.
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SCG->CLKOUTCNFG = SCG_CLKOUTCNFG_CLKOUTSEL(3);
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}
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// TRNG is part of ELS, which requires flash partitioning to work
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// Use our PRNG when the OS does not provide an alternative
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#define MG_HAL_ENABLE_PRNG 1
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static inline uint32_t hal_entropy_init(void) {
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hal_rtc_init(); // Initialize RTC
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spin(100000);
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uint32_t seed = RTC->TPR; // get seed
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spin(100000);
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seed |= (RTC->TPR << 16);
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return seed;
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}
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static inline bool hal_entropy_get(uint32_t *ent) {
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*ent = RTC->TPR;
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return true;
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}
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#if defined(__MCUXPRESSO)
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#undef MG_HAL_DISABLE_SYSTEM_INIT
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#define MG_HAL_DISABLE_SYSTEM_INIT 1
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#undef MG_HAL_SBRK_NONE
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#define MG_HAL_SBRK_NONE 1
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#endif
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static inline void hal_system_init(void) {
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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SCB->CPACR |= (3 << 20) | (3 << 22); // Enable FPU access
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#endif
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__DSB();
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__ISB();
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// Disable watchdog
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if ((WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0) {
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WDOG->CNT = WDOG_UPDATE_KEY;
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} else {
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WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU;
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WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU;
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}
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WDOG->TOVAL = 0xFFFFU;
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WDOG->CS = (uint32_t) ((WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
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LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
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LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;
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// Wait until the command completes
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while (LMEM->PCCCR & LMEM_PCCCR_GO_MASK) spin(1);
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// Enable cache
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LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
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__ISB();
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// Errata ERR050877 workaround. Enable FZ mode in the FPSCR
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__set_FPSCR(__get_FPSCR() | FPSCR_FZ_MASK);
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SYSMPU->CESR &= ~SYSMPU_CESR_VLD(1); // disable MPU
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}
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