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https://github.com/cesanta/mongoose.git
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234 lines
9.9 KiB
C
234 lines
9.9 KiB
C
#include "net_builtin.h"
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_STM32F) && \
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MG_ENABLE_DRIVER_STM32F
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struct stm32f_eth {
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volatile uint32_t MACCR, MACFFR, MACHTHR, MACHTLR, MACMIIAR, MACMIIDR, MACFCR,
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MACVLANTR, RESERVED0[2], MACRWUFFR, MACPMTCSR, RESERVED1, MACDBGR, MACSR,
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MACIMR, MACA0HR, MACA0LR, MACA1HR, MACA1LR, MACA2HR, MACA2LR, MACA3HR,
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MACA3LR, RESERVED2[40], MMCCR, MMCRIR, MMCTIR, MMCRIMR, MMCTIMR,
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RESERVED3[14], MMCTGFSCCR, MMCTGFMSCCR, RESERVED4[5], MMCTGFCR,
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RESERVED5[10], MMCRFCECR, MMCRFAECR, RESERVED6[10], MMCRGUFCR,
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RESERVED7[334], PTPTSCR, PTPSSIR, PTPTSHR, PTPTSLR, PTPTSHUR, PTPTSLUR,
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PTPTSAR, PTPTTHR, PTPTTLR, RESERVED8, PTPTSSR, PTPPPSCR, RESERVED9[564],
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DMABMR, DMATPDR, DMARPDR, DMARDLAR, DMATDLAR, DMASR, DMAOMR, DMAIER,
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DMAMFBOCR, DMARSWTR, RESERVED10[8], DMACHTDR, DMACHRDR, DMACHTBAR,
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DMACHRBAR;
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};
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#undef ETH
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#define ETH ((struct stm32f_eth *) (uintptr_t) 0x40028000)
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#define ETH_PKT_SIZE 1540 // Max frame size
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#define ETH_DESC_CNT 4 // Descriptors count
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#define ETH_DS 4 // Descriptor size (words)
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static uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
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static uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
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static uint8_t s_txno; // Current TX descriptor
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static uint8_t s_rxno; // Current RX descriptor
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static struct mg_tcpip_if *s_ifp; // MIP interface
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static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
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ETH->MACMIIAR &= (7 << 2);
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ETH->MACMIIAR |= ((uint32_t) addr << 11) | ((uint32_t) reg << 6);
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ETH->MACMIIAR |= MG_BIT(0);
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while (ETH->MACMIIAR & MG_BIT(0)) (void) 0;
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return ETH->MACMIIDR & 0xffff;
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}
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static void eth_write_phy(uint8_t addr, uint8_t reg, uint16_t val) {
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ETH->MACMIIDR = val;
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ETH->MACMIIAR &= (7 << 2);
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ETH->MACMIIAR |= ((uint32_t) addr << 11) | ((uint32_t) reg << 6) | MG_BIT(1);
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ETH->MACMIIAR |= MG_BIT(0);
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while (ETH->MACMIIAR & MG_BIT(0)) (void) 0;
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}
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static uint32_t get_hclk(void) {
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struct rcc {
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volatile uint32_t CR, PLLCFGR, CFGR;
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} *rcc = (struct rcc *) 0x40023800;
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uint32_t clk = 0, hsi = 16000000 /* 16 MHz */, hse = 8000000 /* 8MHz */;
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if (rcc->CFGR & (1 << 2)) {
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clk = hse;
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} else if (rcc->CFGR & (1 << 3)) {
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uint32_t vco, m, n, p;
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m = (rcc->PLLCFGR & (0x3f << 0)) >> 0;
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n = (rcc->PLLCFGR & (0x1ff << 6)) >> 6;
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p = (((rcc->PLLCFGR & (3 << 16)) >> 16) + 1) * 2;
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clk = (rcc->PLLCFGR & (1 << 22)) ? hse : hsi;
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vco = (uint32_t) ((uint64_t) clk * n / m);
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clk = vco / p;
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} else {
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clk = hsi;
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}
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uint32_t hpre = (rcc->CFGR & (15 << 4)) >> 4;
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if (hpre < 8) return clk;
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uint8_t ahbptab[8] = {1, 2, 3, 4, 6, 7, 8, 9}; // log2(div)
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return ((uint32_t) clk) >> ahbptab[hpre - 8];
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}
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// Guess CR from HCLK. MDC clock is generated from HCLK (AHB); as per 802.3,
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// it must not exceed 2.5MHz As the AHB clock can be (and usually is) derived
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// from the HSI (internal RC), and it can go above specs, the datasheets
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// specify a range of frequencies and activate one of a series of dividers to
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// keep the MDC clock safely below 2.5MHz. We guess a divider setting based on
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// HCLK with a +5% drift. If the user uses a different clock from our
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// defaults, needs to set the macros on top Valid for STM32F74xxx/75xxx
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// (38.8.1) and STM32F42xxx/43xxx (33.8.1) (both 4.5% worst case drift)
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static int guess_mdc_cr(void) {
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uint8_t crs[] = {2, 3, 0, 1, 4, 5}; // ETH->MACMIIAR::CR values
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uint8_t div[] = {16, 26, 42, 62, 102, 124}; // Respective HCLK dividers
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uint32_t hclk = get_hclk(); // Guess system HCLK
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int result = -1; // Invalid CR value
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if (hclk < 25000000) {
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MG_ERROR(("HCLK too low"));
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} else {
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for (int i = 0; i < 6; i++) {
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if (hclk / div[i] <= 2375000UL /* 2.5MHz - 5% */) {
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result = crs[i];
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break;
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}
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}
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if (result < 0) MG_ERROR(("HCLK too high"));
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}
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MG_DEBUG(("HCLK: %u, CR: %d", hclk, result));
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return result;
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}
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static bool mg_tcpip_driver_stm32f_init(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_stm32f_data *d =
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(struct mg_tcpip_driver_stm32f_data *) ifp->driver_data;
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uint8_t phy_addr = d == NULL ? 0 : d->phy_addr;
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s_ifp = ifp;
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// Init RX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_rxdesc[i][0] = MG_BIT(31); // Own
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s_rxdesc[i][1] = sizeof(s_rxbuf[i]) | MG_BIT(14); // 2nd address chained
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s_rxdesc[i][2] = (uint32_t) (uintptr_t) s_rxbuf[i]; // Point to data buffer
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s_rxdesc[i][3] =
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(uint32_t) (uintptr_t) s_rxdesc[(i + 1) % ETH_DESC_CNT]; // Chain
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}
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// Init TX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_txdesc[i][2] = (uint32_t) (uintptr_t) s_txbuf[i]; // Buf pointer
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s_txdesc[i][3] =
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(uint32_t) (uintptr_t) s_txdesc[(i + 1) % ETH_DESC_CNT]; // Chain
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}
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ETH->DMABMR |= MG_BIT(0); // Software reset
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while ((ETH->DMABMR & MG_BIT(0)) != 0) (void) 0; // Wait until done
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// Set MDC clock divider. If user told us the value, use it. Otherwise, guess
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int cr = (d == NULL || d->mdc_cr < 0) ? guess_mdc_cr() : d->mdc_cr;
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ETH->MACMIIAR = ((uint32_t) cr & 7) << 2;
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// NOTE(cpq): we do not use extended descriptor bit 7, and do not use
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// hardware checksum. Therefore, descriptor size is 4, not 8
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// ETH->DMABMR = MG_BIT(13) | MG_BIT(16) | MG_BIT(22) | MG_BIT(23) |
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// MG_BIT(25);
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ETH->MACIMR = MG_BIT(3) | MG_BIT(9); // Mask timestamp & PMT IT
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ETH->MACFCR = MG_BIT(7); // Disable zero quarta pause
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// ETH->MACFFR = MG_BIT(31); // Receive all
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struct mg_phy phy = {eth_read_phy, eth_write_phy};
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mg_phy_init(&phy, phy_addr, MG_PHY_CLOCKS_MAC);
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ETH->DMARDLAR = (uint32_t) (uintptr_t) s_rxdesc; // RX descriptors
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ETH->DMATDLAR = (uint32_t) (uintptr_t) s_txdesc; // RX descriptors
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ETH->DMAIER = MG_BIT(6) | MG_BIT(16); // RIE, NISE
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ETH->MACCR =
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MG_BIT(2) | MG_BIT(3) | MG_BIT(11) | MG_BIT(14); // RE, TE, Duplex, Fast
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ETH->DMAOMR =
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MG_BIT(1) | MG_BIT(13) | MG_BIT(21) | MG_BIT(25); // SR, ST, TSF, RSF
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// MAC address filtering
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ETH->MACA0HR = ((uint32_t) ifp->mac[5] << 8U) | ifp->mac[4];
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ETH->MACA0LR = (uint32_t) (ifp->mac[3] << 24) |
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((uint32_t) ifp->mac[2] << 16) |
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((uint32_t) ifp->mac[1] << 8) | ifp->mac[0];
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return true;
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}
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static size_t mg_tcpip_driver_stm32f_tx(const void *buf, size_t len,
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struct mg_tcpip_if *ifp) {
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if (len > sizeof(s_txbuf[s_txno])) {
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MG_ERROR(("Frame too big, %ld", (long) len));
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len = 0; // Frame is too big
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} else if ((s_txdesc[s_txno][0] & MG_BIT(31))) {
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ifp->nerr++;
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MG_ERROR(("No free descriptors"));
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// printf("D0 %lx SR %lx\n", (long) s_txdesc[0][0], (long) ETH->DMASR);
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len = 0; // All descriptors are busy, fail
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} else {
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][1] = (uint32_t) len; // Set data len
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s_txdesc[s_txno][0] = MG_BIT(20) | MG_BIT(28) | MG_BIT(29); // Chain,FS,LS
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s_txdesc[s_txno][0] |= MG_BIT(31); // Set OWN bit - let DMA take over
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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MG_DSB(); // ensure descriptors have been written
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ETH->DMASR = MG_BIT(2) | MG_BIT(5); // Clear any prior TBUS/TUS
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ETH->DMATPDR = 0; // and resume
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return len;
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}
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static bool mg_tcpip_driver_stm32f_up(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_stm32f_data *d =
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(struct mg_tcpip_driver_stm32f_data *) ifp->driver_data;
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uint8_t phy_addr = d == NULL ? 0 : d->phy_addr;
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uint8_t speed = MG_PHY_SPEED_10M;
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bool up = false, full_duplex = false;
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struct mg_phy phy = {eth_read_phy, eth_write_phy};
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up = mg_phy_up(&phy, phy_addr, &full_duplex, &speed);
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if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up
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// tmp = reg with flags set to the most likely situation: 100M full-duplex
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// if(link is slow or half) set flags otherwise
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// reg = tmp
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uint32_t maccr = ETH->MACCR | MG_BIT(14) | MG_BIT(11); // 100M, Full-duplex
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if (speed == MG_PHY_SPEED_10M) maccr &= ~MG_BIT(14); // 10M
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if (full_duplex == false) maccr &= ~MG_BIT(11); // Half-duplex
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ETH->MACCR = maccr; // IRQ handler does not fiddle with this register
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MG_DEBUG(("Link is %uM %s-duplex", maccr & MG_BIT(14) ? 100 : 10,
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maccr & MG_BIT(11) ? "full" : "half"));
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}
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return up;
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}
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#ifdef __riscv
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__attribute__((interrupt())) // For RISCV CH32V307, which share the same MAC
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#endif
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void ETH_IRQHandler(void);
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void ETH_IRQHandler(void) {
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if (ETH->DMASR & MG_BIT(6)) { // Frame received, loop
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ETH->DMASR = MG_BIT(16) | MG_BIT(6); // Clear flag
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for (uint32_t i = 0; i < 10; i++) { // read as they arrive but not forever
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if (s_rxdesc[s_rxno][0] & MG_BIT(31)) break; // exit when done
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if (((s_rxdesc[s_rxno][0] & (MG_BIT(8) | MG_BIT(9))) ==
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(MG_BIT(8) | MG_BIT(9))) &&
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!(s_rxdesc[s_rxno][0] & MG_BIT(15))) { // skip partial/errored frames
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uint32_t len = ((s_rxdesc[s_rxno][0] >> 16) & (MG_BIT(14) - 1));
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// printf("%lx %lu %lx %.8lx\n", s_rxno, len, s_rxdesc[s_rxno][0],
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// ETH->DMASR);
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mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp);
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}
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s_rxdesc[s_rxno][0] = MG_BIT(31);
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if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
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}
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}
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// Cleanup flags
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ETH->DMASR = MG_BIT(16) // NIS, normal interrupt summary
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| MG_BIT(7); // Clear possible RBUS while processing
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ETH->DMARPDR = 0; // and resume RX
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}
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struct mg_tcpip_driver mg_tcpip_driver_stm32f = {
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mg_tcpip_driver_stm32f_init, mg_tcpip_driver_stm32f_tx, NULL,
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mg_tcpip_driver_stm32f_up};
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#endif
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