mirror of
https://github.com/cesanta/mongoose.git
synced 2026-10-21 11:30:01 +00:00
234 lines
9.2 KiB
C
234 lines
9.2 KiB
C
#pragma once
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#if MG_ARCH == MG_ARCH_MCUXPRESSO
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#define _POSIX_TIMERS
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#include <ctype.h>
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#if !defined(MG_ENABLE_LWIP) || !MG_ENABLE_LWIP
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#include <errno.h>
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#endif
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#include <stdarg.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include <sys/types.h>
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#include <time.h>
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#include <unistd.h>
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// MCUXpresso-generated header, includes the SoC peripheral definitions.
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// NOTE: use angle brackets to prevent amalgamator ditching it
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#include <fsl_device_registers.h>
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#ifndef MG_PATH_MAX
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#define MG_PATH_MAX 100
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#endif
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#ifndef MG_ENABLE_DIRLIST
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#define MG_ENABLE_DIRLIST 0
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#endif
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#ifndef MG_ENABLE_TCPIP
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#define MG_ENABLE_TCPIP 1 // Enable built-in TCP/IP stack
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#endif
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#if MG_ENABLE_TCPIP && !defined(MG_ENABLE_DRIVER_IMXRT10) && \
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!defined(MG_ENABLE_DRIVER_IMXRT11) && !defined(MG_ENABLE_DRIVER_NETC)
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#if defined(CPU_MIMXRT1021DAG5A) || defined(CPU_MIMXRT1024DAG5A) || \
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defined(CPU_MIMXRT1042XJM5B) || defined(CPU_MIMXRT1052DVL6B) || \
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defined(CPU_MIMXRT1062DVL6B) || defined(CPU_MIMXRT1064DVL6B) || \
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defined(CPU_MIMXRT1062DVL6A) || defined(CPU_MIMXRT1064DVL6A) || \
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defined(CPU_MIMXRT1062DVMAA_cm7) || defined(CPU_MIMXRT1062DVL6A_cm7) || \
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defined(CPU_MIMXRT1062DVL6B_cm7) || defined(_MIMXRT1021_H_) || \
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defined(_MIMXRT1024_H_) || defined(_MIMXRT1042_H_) || \
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defined(_MIMXRT1052_H_) || defined(_MIMXRT1062_H_) || \
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defined(_MIMXRT1064_H_)
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#define MG_ENABLE_DRIVER_IMXRT10 1
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#elif defined(CPU_MIMXRT1176DVMAA_cm7) || defined(CPU_MIMXRT1176DVMAA_cm4) || \
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defined(_MIMXRT1176_cm7_H_) || defined(_MIMXRT1176_cm4_H_) || \
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defined(_MIMXRT1176_H_)
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#define MG_ENABLE_DRIVER_IMXRT11 1
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#elif defined(CPU_MIMXRT1186CVJ8C_cm33) || defined(MIMXRT1186_cm33_H_)
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#define MG_ENABLE_DRIVER_NETC 1
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#else
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#error Select an Ethernet driver in mongoose_config.h
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#endif
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#endif
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#ifndef MG_TLS
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#define MG_TLS MG_TLS_BUILTIN
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#endif
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#if !defined(MG_OTA) && \
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(defined(CPU_MIMXRT1021DAG5A) || defined(CPU_MIMXRT1024DAG5A) || \
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defined(_MIMXRT1021_H_) || defined(_MIMXRT1024_H_))
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#define MG_OTA MG_OTA_RT1020
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#elif !defined(MG_OTA) && \
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(defined(CPU_MIMXRT1052DVL6B) || defined(_MIMXRT1052_H_))
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#define MG_OTA MG_OTA_RT1050
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#elif !defined(MG_OTA) && \
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(defined(CPU_MIMXRT1062DVL6B) || defined(CPU_MIMXRT1062DVL6A) || \
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defined(CPU_MIMXRT1042XJM5B) || defined(_MIMXRT1042_H_) || \
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defined(CPU_MIMXRT1062DVMAA_cm7) || defined(CPU_MIMXRT1062DVL6A_cm7) || \
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defined(CPU_MIMXRT1062DVL6B_cm7) || defined(_MIMXRT1062_H_))
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#define MG_OTA MG_OTA_RT1060
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#elif !defined(MG_OTA) && \
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(defined(CPU_MIMXRT1064DVL6B) || defined(CPU_MIMXRT1064DVL6A) || \
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defined(_MIMXRT1064_H_))
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#define MG_OTA MG_OTA_RT1064
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#elif !defined(MG_OTA) && \
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(defined(CPU_MIMXRT1176DVMAA_cm7) || defined(CPU_MIMXRT1176DVMAA_cm4) || \
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defined(_MIMXRT1176_cm7_H_) || defined(_MIMXRT1176_cm4_H_) || \
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defined(_MIMXRT1176_H_))
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#define MG_OTA MG_OTA_RT1170
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#elif !defined(MG_OTA) && \
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(defined(CPU_MIMXRT1186CVJ8C_cm33) || defined(MIMXRT1186_cm33_H_))
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#define MG_OTA MG_OTA_RT1180
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#endif
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#ifndef MG_IRAM
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#if defined(CPU_MIMXRT1186CVJ8C_cm33) || defined(MIMXRT1186_cm33_H_)
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#define MG_IRAM \
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__attribute__((noinline, section(".ramfunc.$SRAM_ITC_cm33")))
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#else
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#define MG_IRAM __attribute__((noinline, section(".data_RAM2")))
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#endif
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#endif
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#ifndef MG_ETH_RAM
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#if defined(CPU_MIMXRT1186CVJ8C_cm33) || defined(MIMXRT1186_cm33_H_)
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#define MG_ETH_RAM __attribute__((section(".bss.$ETH_RAM")))
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#endif
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#endif
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#ifndef MG_SET_MAC_ADDRESS
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#if defined(MG_ENABLE_DRIVER_NETC) && MG_ENABLE_DRIVER_NETC
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// No OCOTP_FUSES present on RT1186 to generate the UUID
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#define MG_SET_MAC_ADDRESS(mac) (void) (mac)
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#else
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#if defined(MG_ENABLE_DRIVER_IMXRT11) && MG_ENABLE_DRIVER_IMXRT11
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#define MG_OCOTP_FUSES ((volatile uint32_t *) 0x40cac900)
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#else
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#define MG_OCOTP_FUSES ((volatile uint32_t *) 0x401f4410)
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#endif
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#define MG_SET_MAC_ADDRESS(mac) \
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do { \
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mac[0] = 2; \
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mac[1] = (MG_OCOTP_FUSES[0] >> 0) & 255; \
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mac[2] = (MG_OCOTP_FUSES[0] >> 10) & 255; \
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mac[3] = ((MG_OCOTP_FUSES[0] >> 19) ^ (MG_OCOTP_FUSES[4] >> 19)) & 255; \
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mac[4] = (MG_OCOTP_FUSES[4] >> 10) & 255; \
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mac[5] = (MG_OCOTP_FUSES[4] >> 0) & 255; \
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} while (0)
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#endif
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#endif
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#ifndef MG_IMXRT_WDOG1_TIMEOUT_MS
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#define MG_IMXRT_WDOG1_TIMEOUT_MS 10000U
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#endif
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#if defined(CPU_MIMXRT1186CVJ8C_cm33) || defined(MIMXRT1186_cm33_H_)
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#define MG_IMXRT_RTWDOG1_UNLOCK() \
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do { \
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if ((RTWDOG1->CS & RTWDOG_CS_CMD32EN_MASK) != 0U) { \
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RTWDOG1->CNT = RTWDOG_UPDATE_KEY; \
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} else { \
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RTWDOG1->CNT = RTWDOG_UPDATE_KEY & 0xffffU; \
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RTWDOG1->CNT = RTWDOG_UPDATE_KEY >> 16; \
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} \
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while ((RTWDOG1->CS & RTWDOG_CS_ULK_MASK) == 0U) (void) 0; \
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} while (0)
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#define MG_IMXRT_RTWDOG1_FEED() \
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do { \
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uint32_t primask_ = __get_PRIMASK(); \
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__disable_irq(); \
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if ((RTWDOG1->CS & RTWDOG_CS_CMD32EN_MASK) != 0U) { \
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RTWDOG1->CNT = RTWDOG_REFRESH_KEY; \
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} else { \
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RTWDOG1->CNT = RTWDOG_REFRESH_KEY & 0xffffU; \
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RTWDOG1->CNT = RTWDOG_REFRESH_KEY >> 16; \
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} \
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if (primask_ == 0U) __enable_irq(); \
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} while (0)
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#ifndef MG_OTA_ROLLBACK_TIMER_START
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#define MG_OTA_ROLLBACK_TIMER_START() \
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do { \
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uint32_t primask_ = __get_PRIMASK(); \
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SRC_GENERAL_REG->SRMASK &= ~SRC_GENERAL_SRMASK_WDOG1_MASK_MASK; \
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__disable_irq(); \
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MG_IMXRT_RTWDOG1_UNLOCK(); \
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RTWDOG1->WIN = 0U; \
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RTWDOG1->TOVAL = (MG_IMXRT_WDOG1_TIMEOUT_MS + 7U) / 8U; \
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RTWDOG1->CS = RTWDOG_CS_EN_MASK | RTWDOG_CS_UPDATE_MASK | \
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RTWDOG_CS_CLK(1U) | RTWDOG_CS_PRES_MASK | \
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RTWDOG_CS_CMD32EN_MASK; \
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while ((RTWDOG1->CS & RTWDOG_CS_RCS_MASK) == 0U) (void) 0; \
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if (primask_ == 0U) __enable_irq(); \
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} while (0)
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#endif
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#ifndef MG_OTA_ROLLBACK_TIMER_FEED
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#define MG_OTA_ROLLBACK_TIMER_FEED() MG_IMXRT_RTWDOG1_FEED()
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#endif
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// GPR5 survives RTWDOG global resets and is not reserved by the boot ROM.
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#ifndef MG_OTA_STATE_GET
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#define MG_OTA_STATE_GET() SRC_GENERAL_REG->GPR[5]
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#endif
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#ifndef MG_OTA_STATE_SET
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#define MG_OTA_STATE_SET(v) (SRC_GENERAL_REG->GPR[5] = (uint32_t) (v))
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#endif
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#else
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#define MG_IMXRT_WDOG1_FEED() \
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do { \
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WDOG1->WSR = 0x5555; \
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WDOG1->WSR = 0xaaaa; \
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} while (0)
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#ifndef MG_OTA_ROLLBACK_TIMER_START
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#define MG_OTA_ROLLBACK_TIMER_START() \
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do { \
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uint16_t wt_ = (uint16_t) ((MG_IMXRT_WDOG1_TIMEOUT_MS / 500) - 1); \
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if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) == 0) { \
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WDOG1->WMCR = 0; \
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WDOG1->WCR = (uint16_t) (WDOG_WCR_WDZST_MASK | WDOG_WCR_WDBG_MASK | \
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WDOG_WCR_WDE_MASK | WDOG_WCR_WDT_MASK | \
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WDOG_WCR_SRS_MASK | WDOG_WCR_WDW_MASK | \
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WDOG_WCR_WT(wt_)); \
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} \
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MG_IMXRT_WDOG1_FEED(); \
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} while (0)
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#endif
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#ifndef MG_OTA_ROLLBACK_TIMER_FEED
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#define MG_OTA_ROLLBACK_TIMER_FEED() MG_IMXRT_WDOG1_FEED()
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#endif
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#ifndef MG_OTA_STATE_GET
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#define MG_OTA_STATE_GET() SNVS->LPGPR[0]
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#endif
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#ifndef MG_OTA_STATE_SET
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#define MG_OTA_STATE_SET(v) \
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do { \
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if (SNVS->LPSR & (1u << 3)) { \
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SNVS->LPLVDR = 0x41736166u; \
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SNVS->LPSR = 1u << 3; \
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} \
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SNVS->LPGPR[0] = (uint32_t) (v); \
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} while (0)
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#endif
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#endif
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#endif
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