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47 lines
1.7 KiB
C
47 lines
1.7 KiB
C
#pragma once
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#if MG_ENABLE_TCPIP && defined(MG_ENABLE_DRIVER_IMXRT) && MG_ENABLE_DRIVER_IMXRT
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struct mg_tcpip_driver_imxrt_data {
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// MDC clock divider. MDC clock is derived from IPS Bus clock (ipg_clk),
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// must not exceed 2.5MHz. Configuration for clock range 2.36~2.50 MHz
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// 37.5.1.8.2, Table 37-46 : f = ipg_clk / (2(mdc_cr + 1))
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// ipg_clk mdc_cr VALUE
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// --------------------------
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// -1 <-- TODO() tell driver to guess the value
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// 25 MHz 4
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// 33 MHz 6
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// 40 MHz 7
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// 50 MHz 9
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// 66 MHz 13
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int mdc_cr; // Valid values: -1 to 63
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uint8_t phy_addr; // PHY address
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};
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#ifndef MG_TCPIP_PHY_ADDR
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#define MG_TCPIP_PHY_ADDR 2
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#endif
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#ifndef MG_DRIVER_MDC_CR
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#define MG_DRIVER_MDC_CR 24
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#endif
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#define MG_TCPIP_DRIVER_INIT(mgr) \
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do { \
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static struct mg_tcpip_driver_imxrt_data driver_data_; \
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static struct mg_tcpip_if mif_; \
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driver_data_.mdc_cr = MG_DRIVER_MDC_CR; \
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driver_data_.phy_addr = MG_TCPIP_PHY_ADDR; \
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mif_.ip = MG_TCPIP_IP; \
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mif_.mask = MG_TCPIP_MASK; \
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mif_.gw = MG_TCPIP_GW; \
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mif_.driver = &mg_tcpip_driver_imxrt; \
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mif_.driver_data = &driver_data_; \
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MG_SET_MAC_ADDRESS(mif_.mac); \
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mg_tcpip_init(mgr, &mif_); \
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MG_INFO(("Driver: imxrt, MAC: %M", mg_print_mac, mif_.mac)); \
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} while (0)
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#endif
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