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228 lines
10 KiB
C
228 lines
10 KiB
C
#include "net_builtin.h"
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#if MG_ENABLE_TCPIP && (MG_ENABLE_DRIVER_STM32H || MG_ENABLE_DRIVER_MCXN)
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// STM32H: vendor modded single-queue Synopsys v4.2
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// MCXNx4x: dual-queue Synopsys v5.2
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// RT1170 ENET_QOS: quad-queue Synopsys v5.1
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struct synopsys_enet_qos {
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volatile uint32_t MACCR, MACECR, MACPFR, MACWTR, MACHT0R, MACHT1R,
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RESERVED1[14], MACVTR, RESERVED2, MACVHTR, RESERVED3, MACVIR, MACIVIR,
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RESERVED4[2], MACTFCR, RESERVED5[7], MACRFCR, RESERVED6[7], MACISR,
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MACIER, MACRXTXSR, RESERVED7, MACPCSR, MACRWKPFR, RESERVED8[2], MACLCSR,
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MACLTCR, MACLETR, MAC1USTCR, RESERVED9[12], MACVR, MACDR, RESERVED10,
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MACHWF0R, MACHWF1R, MACHWF2R, RESERVED11[54], MACMDIOAR, MACMDIODR,
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RESERVED12[2], MACARPAR, RESERVED13[59], MACA0HR, MACA0LR, MACA1HR,
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MACA1LR, MACA2HR, MACA2LR, MACA3HR, MACA3LR, RESERVED14[248], MMCCR,
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MMCRIR, MMCTIR, MMCRIMR, MMCTIMR, RESERVED15[14], MMCTSCGPR, MMCTMCGPR,
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RESERVED16[5], MMCTPCGR, RESERVED17[10], MMCRCRCEPR, MMCRAEPR,
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RESERVED18[10], MMCRUPGR, RESERVED19[9], MMCTLPIMSTR, MMCTLPITCR,
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MMCRLPIMSTR, MMCRLPITCR, RESERVED20[65], MACL3L4C0R, MACL4A0R,
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RESERVED21[2], MACL3A0R0R, MACL3A1R0R, MACL3A2R0R, MACL3A3R0R,
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RESERVED22[4], MACL3L4C1R, MACL4A1R, RESERVED23[2], MACL3A0R1R,
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MACL3A1R1R, MACL3A2R1R, MACL3A3R1R, RESERVED24[108], MACTSCR, MACSSIR,
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MACSTSR, MACSTNR, MACSTSUR, MACSTNUR, MACTSAR, RESERVED25, MACTSSR,
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RESERVED26[3], MACTTSSNR, MACTTSSSR, RESERVED27[2], MACACR, RESERVED28,
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MACATSNR, MACATSSR, MACTSIACR, MACTSEACR, MACTSICNR, MACTSECNR,
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RESERVED29[4], MACPPSCR, RESERVED30[3], MACPPSTTSR, MACPPSTTNR, MACPPSIR,
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MACPPSWR, RESERVED31[12], MACPOCR, MACSPI0R, MACSPI1R, MACSPI2R, MACLMIR,
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RESERVED32[11], MTLOMR, RESERVED33[7], MTLISR, RESERVED34[55], MTLTQOMR,
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MTLTQUR, MTLTQDR, RESERVED35[8], MTLQICSR, MTLRQOMR, MTLRQMPOCR, MTLRQDR,
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RESERVED36[177], DMAMR, DMASBMR, DMAISR, DMADSR, RESERVED37[60], DMACCR,
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DMACTCR, DMACRCR, RESERVED38[2], DMACTDLAR, RESERVED39, DMACRDLAR,
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DMACTDTPR, RESERVED40, DMACRDTPR, DMACTDRLR, DMACRDRLR, DMACIER,
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DMACRIWTR, DMACSFCSR, RESERVED41, DMACCATDR, RESERVED42, DMACCARDR,
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RESERVED43, DMACCATBR, RESERVED44, DMACCARBR, DMACSR, RESERVED45[2],
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DMACMFCR;
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};
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#undef ETH
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#if MG_ENABLE_DRIVER_STM32H
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#define ETH \
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((struct synopsys_enet_qos *) (uintptr_t) (0x40000000UL + 0x00020000UL + \
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0x8000UL))
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#elif MG_ENABLE_DRIVER_MCXN
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#define ETH ((struct synopsys_enet_qos *) (uintptr_t) 0x40100000UL)
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#endif
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#define ETH_PKT_SIZE 1540 // Max frame size
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#define ETH_DESC_CNT 4 // Descriptors count
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#define ETH_DS 4 // Descriptor size (words)
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static volatile uint32_t s_rxdesc[ETH_DESC_CNT][ETH_DS]; // RX descriptors
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static volatile uint32_t s_txdesc[ETH_DESC_CNT][ETH_DS]; // TX descriptors
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static uint8_t s_rxbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // RX ethernet buffers
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static uint8_t s_txbuf[ETH_DESC_CNT][ETH_PKT_SIZE]; // TX ethernet buffers
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static struct mg_tcpip_if *s_ifp; // MIP interface
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static uint16_t eth_read_phy(uint8_t addr, uint8_t reg) {
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ETH->MACMDIOAR &= (0xF << 8);
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ETH->MACMDIOAR |= ((uint32_t) addr << 21) | ((uint32_t) reg << 16) | 3 << 2;
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ETH->MACMDIOAR |= MG_BIT(0);
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while (ETH->MACMDIOAR & MG_BIT(0)) (void) 0;
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return (uint16_t) ETH->MACMDIODR;
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}
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static void eth_write_phy(uint8_t addr, uint8_t reg, uint16_t val) {
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ETH->MACMDIODR = val;
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ETH->MACMDIOAR &= (0xF << 8);
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ETH->MACMDIOAR |= ((uint32_t) addr << 21) | ((uint32_t) reg << 16) | 1 << 2;
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ETH->MACMDIOAR |= MG_BIT(0);
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while (ETH->MACMDIOAR & MG_BIT(0)) (void) 0;
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}
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static bool mg_tcpip_driver_stm32h_init(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_stm32h_data *d =
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(struct mg_tcpip_driver_stm32h_data *) ifp->driver_data;
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s_ifp = ifp;
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uint8_t phy_addr = d == NULL ? 0 : d->phy_addr;
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uint8_t phy_conf = d == NULL ? MG_PHY_CLOCKS_MAC : d->phy_conf;
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// Init RX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_rxdesc[i][0] = (uint32_t) (uintptr_t) s_rxbuf[i]; // Point to data buffer
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s_rxdesc[i][3] = MG_BIT(31) | MG_BIT(30) | MG_BIT(24); // OWN, IOC, BUF1V
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}
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// Init TX descriptors
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for (int i = 0; i < ETH_DESC_CNT; i++) {
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s_txdesc[i][0] = (uint32_t) (uintptr_t) s_txbuf[i]; // Buf pointer
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}
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ETH->DMAMR |= MG_BIT(0); // Software reset
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for (int i = 0; i < 4; i++)
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(void) 0; // wait at least 4 clocks before reading
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while ((ETH->DMAMR & MG_BIT(0)) != 0) (void) 0; // Wait until done
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// Set MDC clock divider. Get user value, else, assume max freq
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int cr = (d == NULL || d->mdc_cr < 0) ? 7 : d->mdc_cr;
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ETH->MACMDIOAR = ((uint32_t) cr & 0xF) << 8;
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// NOTE(scaprile): We do not use timing facilities so the DMA engine does not
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// re-write buffer address
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ETH->DMAMR = 0 << 16; // use interrupt mode 0 (58.8.1) (reset value)
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ETH->DMASBMR |= MG_BIT(12); // AAL NOTE(scaprile): is this actually needed
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ETH->MACIER = 0; // Do not enable additional irq sources (reset value)
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ETH->MACTFCR = MG_BIT(7); // Disable zero-quanta pause
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// ETH->MACPFR = MG_BIT(31); // Receive all
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struct mg_phy phy = {eth_read_phy, eth_write_phy};
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mg_phy_init(&phy, phy_addr, phy_conf);
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ETH->DMACRDLAR =
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(uint32_t) (uintptr_t) s_rxdesc; // RX descriptors start address
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ETH->DMACRDRLR = ETH_DESC_CNT - 1; // ring length
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ETH->DMACRDTPR =
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(uint32_t) (uintptr_t) &s_rxdesc[ETH_DESC_CNT -
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1]; // last valid descriptor address
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ETH->DMACTDLAR =
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(uint32_t) (uintptr_t) s_txdesc; // TX descriptors start address
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ETH->DMACTDRLR = ETH_DESC_CNT - 1; // ring length
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ETH->DMACTDTPR =
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(uint32_t) (uintptr_t) s_txdesc; // first available descriptor address
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ETH->DMACCR = 0; // DSL = 0 (contiguous descriptor table) (reset value)
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#if !MG_ENABLE_DRIVER_STM32H
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MG_SET_BITS(ETH->DMACTCR, 0x3F << 16, MG_BIT(16));
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MG_SET_BITS(ETH->DMACRCR, 0x3F << 16, MG_BIT(16));
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#endif
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ETH->DMACIER = MG_BIT(6) | MG_BIT(15); // RIE, NIE
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ETH->MACCR = MG_BIT(0) | MG_BIT(1) | MG_BIT(13) | MG_BIT(14) |
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MG_BIT(15); // RE, TE, Duplex, Fast, Reserved
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#if MG_ENABLE_DRIVER_STM32H
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ETH->MTLTQOMR |= MG_BIT(1); // TSF
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ETH->MTLRQOMR |= MG_BIT(5); // RSF
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#else
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ETH->MTLTQOMR |= (7 << 16) | MG_BIT(3) | MG_BIT(1); // 2KB Q0, TSF
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ETH->MTLRQOMR |= (7 << 20) | MG_BIT(5); // 2KB Q, RSF
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MG_SET_BITS(ETH->RESERVED6[3], 3, 2); // Enable RxQ0 (MAC_RXQ_CTRL0)
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#endif
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ETH->DMACTCR |= MG_BIT(0); // ST
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ETH->DMACRCR |= MG_BIT(0); // SR
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// MAC address filtering
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ETH->MACA0HR = ((uint32_t) ifp->mac[5] << 8U) | ifp->mac[4];
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ETH->MACA0LR = (uint32_t) (ifp->mac[3] << 24) |
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((uint32_t) ifp->mac[2] << 16) |
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((uint32_t) ifp->mac[1] << 8) | ifp->mac[0];
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return true;
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}
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static uint32_t s_txno;
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static size_t mg_tcpip_driver_stm32h_tx(const void *buf, size_t len,
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struct mg_tcpip_if *ifp) {
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if (len > sizeof(s_txbuf[s_txno])) {
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MG_ERROR(("Frame too big, %ld", (long) len));
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len = 0; // Frame is too big
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} else if ((s_txdesc[s_txno][3] & MG_BIT(31))) {
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ifp->nerr++;
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MG_ERROR(("No free descriptors: %u %08X %08X %08X", s_txno,
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s_txdesc[s_txno][3], ETH->DMACSR, ETH->DMACTCR));
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for (int i = 0; i < ETH_DESC_CNT; i++) MG_ERROR(("%08X", s_txdesc[i][3]));
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len = 0; // All descriptors are busy, fail
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} else {
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memcpy(s_txbuf[s_txno], buf, len); // Copy data
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s_txdesc[s_txno][2] = (uint32_t) len; // Set data len
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s_txdesc[s_txno][3] = MG_BIT(28) | MG_BIT(29); // FD, LD
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s_txdesc[s_txno][3] |= MG_BIT(31); // Set OWN bit - let DMA take over
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if (++s_txno >= ETH_DESC_CNT) s_txno = 0;
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}
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ETH->DMACSR |= MG_BIT(2) | MG_BIT(1); // Clear any prior TBU, TPS
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ETH->DMACTDTPR = (uint32_t) (uintptr_t) &s_txdesc[s_txno]; // and resume
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return len;
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(void) ifp;
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}
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static bool mg_tcpip_driver_stm32h_up(struct mg_tcpip_if *ifp) {
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struct mg_tcpip_driver_stm32h_data *d =
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(struct mg_tcpip_driver_stm32h_data *) ifp->driver_data;
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uint8_t phy_addr = d == NULL ? 0 : d->phy_addr;
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uint8_t speed = MG_PHY_SPEED_10M;
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bool up = false, full_duplex = false;
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struct mg_phy phy = {eth_read_phy, eth_write_phy};
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up = mg_phy_up(&phy, phy_addr, &full_duplex, &speed);
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if ((ifp->state == MG_TCPIP_STATE_DOWN) && up) { // link state just went up
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// tmp = reg with flags set to the most likely situation: 100M full-duplex
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// if(link is slow or half) set flags otherwise
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// reg = tmp
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uint32_t maccr = ETH->MACCR | MG_BIT(14) | MG_BIT(13); // 100M, Full-duplex
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if (speed == MG_PHY_SPEED_10M) maccr &= ~MG_BIT(14); // 10M
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if (full_duplex == false) maccr &= ~MG_BIT(13); // Half-duplex
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ETH->MACCR = maccr; // IRQ handler does not fiddle with this register
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MG_DEBUG(("Link is %uM %s-duplex", maccr & MG_BIT(14) ? 100 : 10,
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maccr & MG_BIT(13) ? "full" : "half"));
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}
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return up;
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}
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static uint32_t s_rxno;
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#if MG_ENABLE_DRIVER_MCXN
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void ETHERNET_IRQHandler(void);
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void ETHERNET_IRQHandler(void) {
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#else
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void ETH_IRQHandler(void);
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void ETH_IRQHandler(void) {
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#endif
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if (ETH->DMACSR & MG_BIT(6)) { // Frame received, loop
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ETH->DMACSR = MG_BIT(15) | MG_BIT(6); // Clear flag
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for (uint32_t i = 0; i < 10; i++) { // read as they arrive but not forever
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if (s_rxdesc[s_rxno][3] & MG_BIT(31)) break; // exit when done
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if (((s_rxdesc[s_rxno][3] & (MG_BIT(28) | MG_BIT(29))) ==
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(MG_BIT(28) | MG_BIT(29))) &&
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!(s_rxdesc[s_rxno][3] & MG_BIT(15))) { // skip partial/errored frames
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uint32_t len = s_rxdesc[s_rxno][3] & (MG_BIT(15) - 1);
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// MG_DEBUG(("%lx %lu %lx %08lx", s_rxno, len, s_rxdesc[s_rxno][3],
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// ETH->DMACSR));
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mg_tcpip_qwrite(s_rxbuf[s_rxno], len > 4 ? len - 4 : len, s_ifp);
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}
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s_rxdesc[s_rxno][3] =
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MG_BIT(31) | MG_BIT(30) | MG_BIT(24); // OWN, IOC, BUF1V
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if (++s_rxno >= ETH_DESC_CNT) s_rxno = 0;
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}
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}
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ETH->DMACSR =
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MG_BIT(7) | MG_BIT(8); // Clear possible RBU RPS while processing
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ETH->DMACRDTPR =
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(uint32_t) (uintptr_t) &s_rxdesc[ETH_DESC_CNT - 1]; // and resume RX
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}
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struct mg_tcpip_driver mg_tcpip_driver_stm32h = {
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mg_tcpip_driver_stm32h_init, mg_tcpip_driver_stm32h_tx, NULL,
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mg_tcpip_driver_stm32h_up};
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#endif
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