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205 lines
7.1 KiB
C
205 lines
7.1 KiB
C
/*
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** ###################################################################
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** Processors: RW610ETA2I
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** RW610HNA2I
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** RW610UKA2I
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** RW612ETA2I
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** RW612HNA2I
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** RW612UKA2I
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**
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** Version: rev. 1.0, 2021-03-16
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** Build: b240715
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**
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** Abstract:
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** CMSIS Peripheral Access Layer for CRC
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**
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** Copyright 1997-2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2024 NXP
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 1.0 (2021-03-16)
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** Initial version.
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**
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** ###################################################################
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*/
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/*!
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* @file CRC.h
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* @version 1.0
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* @date 2021-03-16
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* @brief CMSIS Peripheral Access Layer for CRC
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*
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* CMSIS Peripheral Access Layer for CRC
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*/
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#if !defined(CRC_H_)
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#define CRC_H_ /**< Symbol preventing repeated inclusion */
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#if (defined(CPU_RW610ETA2I) || defined(CPU_RW610HNA2I) || defined(CPU_RW610UKA2I))
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#include "RW610_COMMON.h"
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#elif (defined(CPU_RW612ETA2I) || defined(CPU_RW612HNA2I) || defined(CPU_RW612UKA2I))
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#include "RW612_COMMON.h"
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#else
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#error "No valid CPU defined!"
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#endif
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/* ----------------------------------------------------------------------------
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-- Device Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
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* @{
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*/
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/*
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** Start of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#else
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#pragma push
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#pragma anon_unions
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#endif
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#elif defined(__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=extended
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#else
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#error Not supported compiler type
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#endif
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/* ----------------------------------------------------------------------------
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-- CRC Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
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* @{
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*/
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/** CRC - Register Layout Typedef */
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typedef struct {
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__IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
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__IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
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union { /* offset: 0x8 */
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__I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
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__O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
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};
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} CRC_Type;
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/* ----------------------------------------------------------------------------
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-- CRC Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup CRC_Register_Masks CRC Register Masks
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* @{
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*/
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/*! @name MODE - CRC mode register */
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/*! @{ */
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#define CRC_MODE_CRC_POLY_MASK (0x3U)
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#define CRC_MODE_CRC_POLY_SHIFT (0U)
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/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial */
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#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
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#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
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#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
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/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) */
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#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
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#define CRC_MODE_CMPL_WR_MASK (0x8U)
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#define CRC_MODE_CMPL_WR_SHIFT (3U)
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/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA */
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#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
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#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
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#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
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/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM */
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#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
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#define CRC_MODE_CMPL_SUM_MASK (0x20U)
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#define CRC_MODE_CMPL_SUM_SHIFT (5U)
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/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM */
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#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
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/*! @} */
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/*! @name SEED - CRC seed register */
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/*! @{ */
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#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
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#define CRC_SEED_CRC_SEED_SHIFT (0U)
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/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with
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* selected bit order and 1's complement pre-processes. A write access to this register will
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* overrule the CRC calculation in progresses.
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*/
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#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
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/*! @} */
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/*! @name SUM - CRC checksum register */
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/*! @{ */
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#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
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#define CRC_SUM_CRC_SUM_SHIFT (0U)
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/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. */
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#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
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/*! @} */
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/*! @name WR_DATA - CRC data register */
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/*! @{ */
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#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
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#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
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/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with
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* selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and
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* accept back-to-back transactions.
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*/
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#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
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/*! @} */
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/*!
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* @}
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*/ /* end of group CRC_Register_Masks */
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/*!
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* @}
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*/ /* end of group CRC_Peripheral_Access_Layer */
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/*
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** End of section using anonymous unions
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*/
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#if defined(__ARMCC_VERSION)
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#if (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic pop
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#else
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#pragma pop
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#endif
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#elif defined(__GNUC__)
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/* leave anonymous unions enabled */
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#elif defined(__IAR_SYSTEMS_ICC__)
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#pragma language=default
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#else
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#error Not supported compiler type
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#endif
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/*!
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* @}
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*/ /* end of group Peripheral_access_layer */
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#endif /* CRC_H_ */
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